layerscape: add 64b/32b target for ls1043ardb device

Add support for NXP layerscape ls1043ardb 64b/32b Dev board. LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores. ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC, I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc. 64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from NXP QorIQ SDK release. All of 4.4 kernel patches porting from SDK release or upstream. QorIQ SDK ISOs can be downloaded from this location: http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
8 years ago · c6c731fe31
parent a34f96d6cf
commit c6c731fe31
86 changed files with 171202 additions and 0 deletions
--- a/package/boot/uboot-layerscape-32b/Makefile
+++ b/package/boot/uboot-layerscape-32b/Makefile
@ -0,0 +1,87 @@
+#
+# Copyright (C) 2016 Jiang Yutang <jiangyutang1978@gmail.com>
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/image.mk
+
+PKG_NAME:=uboot-layerscape-32bit
+PKG_VERSION:=v1.0
+PKG_RELEASE:=1
+
+PKG_SOURCE_PROTO:=git
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
+PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
+PKG_SOURCE_URL:=https://github.com/fsl-jyt/uboot-ls-32b.git
+PKG_SOURCE_VERSION:=4fbf7e76eb7671d9822d0310319f6ad70d324547
+
+PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
+
+PKG_LICENSE:=GPL-2.0 GPL-2.0+
+PKG_LICENSE_FILES:=Licenses/README
+
+include $(INCLUDE_DIR)/package.mk
+
+define uboot/Default
+	TITLE:=
+	CONFIG:=
+endef
+
+define uboot/ls1043ardb
+	TITLE:=U-Boot binary $(PKG_NAME)-$(PKG_VERSION) for NXP ls1043ardb 32b Dev Board
+	CONFIG=ls1043ardb-uboot.bin
+endef
+
+UBOOTS := \
+	ls1043ardb
+
+define Package/uboot/template
+define Package/uboot-layerscape-32b-$(1)
+	SECTION:=boot
+	CATEGORY:=Boot Loaders
+	DEPENDS:= @TARGET_layerscape_32b
+	TITLE:=$(2)
+	URL:=https://github.com/fsl-jyt/uboot-ls-32b.git
+	VARIANT:=$(1)
+	MAINTAINER:=Jiang Yutang <jiangyutang1978@gmail.com>
+endef
+endef
+
+define BuildUBootPackage
+	$(eval $(uboot/Default))
+	$(eval $(uboot/$(1)))
+	$(call Package/uboot/template,$(1),$(TITLE))
+endef
+
+ifdef BUILD_VARIANT
+$(eval $(call uboot/$(BUILD_VARIANT)))
+UBOOT_CONFIG:=$(if $(CONFIG),$(CONFIG),$(BUILD_VARIANT))
+endif
+
+define Build/Configure
+endef
+
+define Build/Compile
+endef
+
+define Package/uboot/install/default
+	$(CP) $(PKG_BUILD_DIR)/$(UBOOT_CONFIG) $(KDIR)/$(1)-32b-uboot.bin
+endef
+
+define Package/uboot/install/template
+define Package/uboot-layerscape-32b-$(1)/install
+	$(call Package/uboot/install/default,$(2))
+endef
+endef
+
+$(foreach u,$(UBOOTS), \
+	$(eval $(call Package/uboot/install/template,$(u),$(u))) \
+)
+
+$(foreach u,$(UBOOTS), \
+	$(eval $(call BuildUBootPackage,$(u))) \
+	$(eval $(call BuildPackage,uboot-layerscape-32b-$(u))) \
+)
--- a/package/boot/uboot-layerscape/Makefile
+++ b/package/boot/uboot-layerscape/Makefile
@ -0,0 +1,90 @@
+#
+# Copyright (C) 2016 Jiang Yutang <jiangyutang1978@gmail.com>
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/image.mk
+
+PKG_NAME:=fsl-sdk
+PKG_VERSION:=v2.0
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
+PKG_SOURCE_URL:= \
+	http://git.freescale.com/git/cgit.cgi/ppc/sdk/u-boot.git/snapshot
+PKG_MD5SUM:=14f7ccc757bfa71c9b7fd68d24051231
+
+PKG_BUILD_DIR:=$(BUILD_DIR)/u-boot_$(PKG_NAME)-$(PKG_VERSION)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
+
+PKG_LICENSE:=GPL-2.0 GPL-2.0+
+PKG_LICENSE_FILES:=Licenses/README
+
+include $(INCLUDE_DIR)/package.mk
+
+define uboot/Default
+	TITLE:=
+	CONFIG:=
+	IMAGE:=
+endef
+
+define uboot/ls1043ardb
+	TITLE:=U-Boot $(PKG_NAME)-$(PKG_VERSION) for NXP ls1043ardb 64b Dev Board
+	CONFIG=ls1043ardb
+endef
+
+UBOOTS := \
+	ls1043ardb
+
+define Package/uboot/template
+define Package/uboot-layerscape-64b-$(1)
+	SECTION:=boot
+	CATEGORY:=Boot Loaders
+	DEPENDS:= @TARGET_layerscape_64b
+	TITLE:=$(2)
+	URL:=http://git.freescale.com/git/cgit.cgi/ppc/sdk/u-boot.git/snapshot
+	VARIANT:=$(1)
+	MAINTAINER:=Jiang Yutang <jiangyutang1978@gmail.com>
+endef
+endef
+
+define BuildUBootPackage
+	$(eval $(uboot/Default))
+	$(eval $(uboot/$(1)))
+	$(call Package/uboot/template,$(1),$(TITLE))
+endef
+
+ifdef BUILD_VARIANT
+$(eval $(call uboot/$(BUILD_VARIANT)))
+UBOOT_CONFIG:=$(if $(CONFIG),$(CONFIG),$(BUILD_VARIANT))
+UBOOT_IMAGE:=$(if $(IMAGE),$(IMAGE),u-boot-dtb.bin)
+endif
+
+define Build/Configure
+	+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \
+		$(UBOOT_CONFIG)_config
+endef
+
+define Build/Compile
+	+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \
+		CROSS_COMPILE=$(TARGET_CROSS) DTC=$(LINUX_DIR)/scripts/dtc/dtc
+endef
+
+define Package/uboot/install/default
+	$(CP) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(KDIR)/$(1)-64b-uboot.bin
+endef
+
+define Package/uboot/install/template
+define Package/uboot-layerscape-64b-$(1)/install
+	$(call Package/uboot/install/default,$(2))
+endef
+endef
+
+$(foreach u,$(UBOOTS), \
+	$(eval $(call Package/uboot/install/template,$(u),$(u))) \
+)
+
+$(foreach u,$(UBOOTS), \
+	$(eval $(call BuildUBootPackage,$(u))) \
+	$(eval $(call BuildPackage,uboot-layerscape-64b-$(u))) \
+)
--- a/package/boot/uboot-layerscape/patches/0001-armv8-Support-loading-32-bit-OS-in-AArch32-execution.patch
+++ b/package/boot/uboot-layerscape/patches/0001-armv8-Support-loading-32-bit-OS-in-AArch32-execution.patch
@ -0,0 +1,214 @@
+From e03f571b1e9564ca422134b2013d80c8373c9db2 Mon Sep 17 00:00:00 2001
+From: Alison Wang <b18965@freescale.com>
+Date: Fri, 13 May 2016 10:19:24 +0800
+Subject: [PATCH 01/93] armv8: Support loading 32-bit OS in AArch32 execution
+ state
+
+To support loading a 32-bit OS, the execution state will change from
+AArch64 to AArch32 when jumping to kernel.
+
+The architecture information will be got through checking FIT
+image, then U-Boot will load 32-bit OS or 64-bit OS automatically.
+
+Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com>
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
+---
+ arch/arm/cpu/armv8/transition.S |  100 +++++++++++++++++++++++++++++++++++++++
+ arch/arm/include/asm/system.h   |    2 +
+ arch/arm/lib/bootm.c            |   20 +++++++-
+ common/image-fit.c              |   12 ++++-
+ 4 files changed, 131 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S
+index 253a39b..9d7a17a 100644
+--- a/arch/arm/cpu/armv8/transition.S
+++ b/arch/arm/cpu/armv8/transition.S
+@@ -21,3 +21,103 @@ ENTRY(armv8_switch_to_el1)
+ 0:	ret
+ 1:	armv8_switch_to_el1_m x0, x1
+ ENDPROC(armv8_switch_to_el1)
+
+/*
+ * x0: kernel entry point
+ * x1: machine nr
+ * x2: fdt address
+ */
+ENTRY(armv8_switch_to_el2_aarch32)
+	switch_el x3, 1f, 0f, 0f
+0:	ret
+1:
+	mov	x7, x0
+	mov	x8, x1
+	mov	x9, x2
+
+	/* 32bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */
+	mov	x1, 0x1b1
+	msr	scr_el3, x1
+	msr	cptr_el3, xzr	/* Disable coprocessor traps to EL3 */
+	mov	x1, 0x33ff
+	msr	cptr_el2, x1	/* Disable coprocessor traps to EL2 */
+
+	/* Initialize Generic Timers */
+	msr	cntvoff_el2, xzr
+
+	mov	x1, #0x0830
+	movk	x1, #0x30c5, lsl #16
+	msr	sctlr_el2, x1
+
+	/* Return to AArch32 Hypervisor mode */
+	mov	x1, sp
+	msr	sp_el2, x1
+	mrs	x1, vbar_el3
+	msr	vbar_el2, x1	/* Migrate VBAR */
+	mov	x1, #0x1da
+	msr	spsr_el3, x1
+	msr	elr_el3, x7
+
+	mov	x0, #0
+	mov	x1, x8
+	mov	x2, x9
+
+	eret
+ENDPROC(armv8_switch_to_el2_aarch32)
+
+/*
+ * x0: kernel entry point
+ * x1: machine nr
+ * x2: fdt address
+ */
+ENTRY(armv8_switch_to_el1_aarch32)
+	switch_el x3, 0f, 1f, 0f
+0:	ret
+1:
+	mov	x7, x0
+	mov	x8, x1
+	mov	x9, x2
+
+	/* Initialize Generic Timers */
+	mrs	x0, cnthctl_el2
+	orr	x0, x0, #0x3		/* Enable EL1 access to timers */
+	msr	cnthctl_el2, x0
+	msr	cntvoff_el2, xzr
+
+        /* Initialize MPID/MPIDR registers */
+	mrs	x0, midr_el1
+	mrs	x1, mpidr_el1
+	msr	vpidr_el2, x0
+	msr	vmpidr_el2, x1
+
+        /* Disable coprocessor traps */
+	mov	x0, #0x33ff
+	msr	cptr_el2, x0		/* Disable coprocessor traps to EL2 */
+        msr	hstr_el2, xzr		/* Disable coprocessor traps to EL2 */
+        mov	x0, #3 << 20
+        msr	cpacr_el1, x0		/* Enable FP/SIMD at EL1 */
+
+	/* Initialize HCR_EL2 */
+	mov	x0, #(0 << 31)		/* 32bit EL1 */
+	orr	x0, x0, #(1 << 29)	/* Disable HVC */
+	msr	hcr_el2, x0
+
+	mov	x0, #0x0800
+	movk	x0, #0x30d0, lsl #16
+	msr	sctlr_el1, x0
+
+	/* Return to AArch32 Supervisor mode */
+	mov	x0, sp
+	msr	sp_el1, x0		/* Migrate SP */
+	mrs	x0, vbar_el2
+	msr	vbar_el1, x0		/* Migrate VBAR */
+	mov     x0, #0x1d3
+	msr	spsr_el2, x0
+	msr	elr_el2, x7
+
+	mov	x0, #0
+	mov	x1, x8
+	mov	x2, x9
+
+	eret
+ENDPROC(armv8_switch_to_el1_aarch32)
+diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
+index 71b3108..0ecbcf7 100644
+--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
+@@ -81,6 +81,8 @@ int __asm_flush_l3_cache(void);
+ 
+ void armv8_switch_to_el2(void);
+ void armv8_switch_to_el1(void);
+void armv8_switch_to_el2_aarch32(u64 entry_point, u64 mach_nr, u64 fdt_addr);
+void armv8_switch_to_el1_aarch32(u64 entry_point, u64 mach_nr, u64 fdt_addr);
+ void gic_init(void);
+ void gic_send_sgi(unsigned long sgino);
+ void wait_for_wakeup(void);
+diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
+index a477cae..36f2cb0 100644
+--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
+@@ -276,8 +276,24 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
+ 	announce_and_cleanup(fake);
+ 
+ 	if (!fake) {
+-		do_nonsec_virt_switch();
+-		kernel_entry(images->ft_addr, NULL, NULL, NULL);
+		if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) &&
+		    (images->os.arch == IH_ARCH_ARM)) {
+			smp_kick_all_cpus();
+			dcache_disable();
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+			armv8_switch_to_el2();
+			armv8_switch_to_el1_aarch32((u64)images->ep,
+						    (u64)gd->bd->bi_arch_number,
+						    (u64)images->ft_addr);
+#else
+			armv8_switch_to_el2_aarch32((u64)images->ep,
+						    (u64)gd->bd->bi_arch_number,
+						    (u64)images->ft_addr);
+#endif
+		} else {
+			do_nonsec_virt_switch();
+			kernel_entry(images->ft_addr, NULL, NULL, NULL);
+		}
+ 	}
+ #else
+ 	unsigned long machid = gd->bd->bi_arch_number;
+diff --git a/common/image-fit.c b/common/image-fit.c
+index c531ee7..0d54f71 100644
+--- a/common/image-fit.c
+++ b/common/image-fit.c
+@@ -1144,7 +1144,8 @@ int fit_image_check_arch(const void *fit, int noffset, uint8_t arch)
+ 	if (fit_image_get_arch(fit, noffset, &image_arch))
+ 		return 0;
+ 	return (arch == image_arch) ||
+-		(arch == IH_ARCH_I386 && image_arch == IH_ARCH_X86_64);
+		(arch == IH_ARCH_I386 && image_arch == IH_ARCH_X86_64) ||
+		(arch == IH_ARCH_ARM64 && image_arch == IH_ARCH_ARM);
+ }
+ 
+ /**
+@@ -1567,6 +1568,9 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
+ 	int type_ok, os_ok;
+ 	ulong load, data, len;
+ 	uint8_t os;
+#ifndef USE_HOSTCC
+	uint8_t os_arch;
+#endif
+ 	const char *prop_name;
+ 	int ret;
+ 
+@@ -1650,6 +1654,12 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
+ 		return -ENOEXEC;
+ 	}
+ #endif
+
+#ifndef USE_HOSTCC
+	fit_image_get_arch(fit, noffset, &os_arch);
+	images->os.arch = os_arch;
+#endif
+
+ 	if (image_type == IH_TYPE_FLATDT &&
+ 	    !fit_image_check_comp(fit, noffset, IH_COMP_NONE)) {
+ 		puts("FDT image is compressed");
+-- 
+1.7.9.5
+
--- a/package/boot/uboot-layerscape/patches/0002-armv8-SMP-support-for-loading-32-bit-OS.patch
+++ b/package/boot/uboot-layerscape/patches/0002-armv8-SMP-support-for-loading-32-bit-OS.patch
@ -0,0 +1,141 @@
+From 014f9196e18f4157232d0521f3a7502e7dbbb974 Mon Sep 17 00:00:00 2001
+From: Alison Wang <b18965@freescale.com>
+Date: Fri, 13 May 2016 13:28:07 +0800
+Subject: [PATCH 02/93] armv8: SMP support for loading 32-bit OS
+
+Spin-table method is used for secondary cores to load 32-bit OS. The
+architecture information will be got through checking FIT image and
+saved in the os_arch element of spin-table, then the secondary cores
+will check os_arch and jump to 32-bit OS or 64-bit OS automatically.
+
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
+---
+ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S  |   21 +++++++++++++++++++++
+ arch/arm/cpu/armv8/fsl-layerscape/mp.c        |   10 ++++++++++
+ arch/arm/include/asm/arch-fsl-layerscape/mp.h |    6 ++++++
+ arch/arm/lib/bootm.c                          |    5 +++++
+ 4 files changed, 42 insertions(+)
+
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+index 9c69ed1..93f4a65 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+@@ -13,6 +13,7 @@
+ #ifdef CONFIG_MP
+ #include <asm/arch/mp.h>
+ #endif
+#include <asm/u-boot.h>
+ 
+ ENTRY(lowlevel_init)
+ 	mov	x29, lr			/* Save LR */
+@@ -320,6 +321,11 @@ ENTRY(secondary_boot_func)
+         gic_wait_for_interrupt_m x0, w1
+ #endif
+ 
+	ldr	x5, [x11, #24]
+	ldr	x6, =IH_ARCH_DEFAULT
+	cmp	x6, x5
+	b.ne	slave_cpu
+
+ 	bl secondary_switch_to_el2
+ #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+ 	bl secondary_switch_to_el1
+@@ -337,6 +343,21 @@ slave_cpu:
+ 	tbz     x1, #25, cpu_is_le
+ 	rev     x0, x0                  /* BE to LE conversion */
+ cpu_is_le:
+
+	ldr	x5, [x11, #24]
+	ldr	x6, =IH_ARCH_DEFAULT
+	cmp	x6, x5
+	b.eq	1f
+
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+	bl	secondary_switch_to_el2
+	ldr	x0, [x11]
+	bl	armv8_switch_to_el1_aarch32
+#else
+	bl	armv8_switch_to_el2_aarch32
+#endif
+
+1:
+ 	br	x0			/* branch to the given address */
+ ENDPROC(secondary_boot_func)
+ 
+diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+index df7ffb8..dd91550 100644
+--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+@@ -22,6 +22,16 @@ phys_addr_t determine_mp_bootpg(void)
+ 	return (phys_addr_t)&secondary_boot_code;
+ }
+ 
+void update_os_arch_secondary_cores(uint8_t os_arch)
+{
+	u64 *table = get_spin_tbl_addr();
+	int i;
+
+	for (i = 1; i < CONFIG_MAX_CPUS; i++)
+		table[i * WORDS_PER_SPIN_TABLE_ENTRY +
+			SPIN_TABLE_ELEM_OS_ARCH_IDX] = os_arch;
+}
+
+ int fsl_layerscape_wake_seconday_cores(void)
+ {
+ 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
+index e46e076..55f0e0c 100644
+--- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
+@@ -13,6 +13,7 @@
+ *      uint64_t entry_addr;
+ *      uint64_t status;
+ *      uint64_t lpid;
+*      uint64_t os_arch;
+ * };
+ * we pad this struct to 64 bytes so each entry is in its own cacheline
+ * the actual spin table is an array of these structures
+@@ -20,6 +21,7 @@
+ #define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX	0
+ #define SPIN_TABLE_ELEM_STATUS_IDX	1
+ #define SPIN_TABLE_ELEM_LPID_IDX	2
+#define SPIN_TABLE_ELEM_OS_ARCH_IDX	3
+ #define WORDS_PER_SPIN_TABLE_ENTRY	8	/* pad to 64 bytes */
+ #define SPIN_TABLE_ELEM_SIZE		64
+ 
+@@ -35,4 +37,8 @@ phys_addr_t determine_mp_bootpg(void);
+ void secondary_boot_func(void);
+ int is_core_online(u64 cpu_id);
+ #endif
+
+#define IH_ARCH_ARM		2	/* ARM */
+#define IH_ARCH_ARM64		22	/* ARM64 */
+
+ #endif /* _FSL_LAYERSCAPE_MP_H */
+diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
+index 36f2cb0..aae8c5b 100644
+--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
+@@ -258,6 +258,10 @@ bool armv7_boot_nonsec(void)
+ }
+ #endif
+ 
+__weak void update_os_arch_secondary_cores(uint8_t os_arch)
+{
+}
+
+ /* Subcommand: GO */
+ static void boot_jump_linux(bootm_headers_t *images, int flag)
+ {
+@@ -276,6 +280,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
+ 	announce_and_cleanup(fake);
+ 
+ 	if (!fake) {
+		update_os_arch_secondary_cores(images->os.arch);
+ 		if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) &&
+ 		    (images->os.arch == IH_ARCH_ARM)) {
+ 			smp_kick_all_cpus();
+-- 
+1.7.9.5
+
--- a/package/boot/uboot-layerscape/patches/0003-armv8-aarch32-Disable-CONFIG_FSL_LS_PPA-for-loading-.patch
+++ b/package/boot/uboot-layerscape/patches/0003-armv8-aarch32-Disable-CONFIG_FSL_LS_PPA-for-loading-.patch
@ -0,0 +1,30 @@
+From f9e93719a99120e93628bf39bd997164a01afda2 Mon Sep 17 00:00:00 2001
+From: Alison Wang <b18965@freescale.com>
+Date: Fri, 13 May 2016 15:23:27 +0800
+Subject: [PATCH 03/93] armv8: aarch32: Disable CONFIG_FSL_LS_PPA for loading
+ 32-bit OS
+
+The current U-Boot doesn't support loading 32-bit OS with PPA, so
+disable CONFIG_FSL_LS_PPA so far.
+
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+---
+ include/configs/ls1043ardb.h |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
+index c1abc73..af8b441 100644
+--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
+@@ -9,7 +9,7 @@
+ 
+ #include "ls1043a_common.h"
+ 
+-#define CONFIG_FSL_LS_PPA
+#undef CONFIG_FSL_LS_PPA
+ #if defined(CONFIG_FSL_LS_PPA)
+ #define CONFIG_ARMV8_PSCI
+ #define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE		(1UL * 1024 * 1024)
+-- 
+1.7.9.5
+
--- a/package/boot/uboot-layerscape/patches/0004-armv8-Support-loading-32-bit-OS-which-is-not-in-the-.patch
+++ b/package/boot/uboot-layerscape/patches/0004-armv8-Support-loading-32-bit-OS-which-is-not-in-the-.patch
@ -0,0 +1,31 @@
+From cb5a037831053d22ce260dbec6b378f532bd2c6c Mon Sep 17 00:00:00 2001
+From: Alison Wang <b18965@freescale.com>
+Date: Tue, 21 Jun 2016 17:14:35 +0800
+Subject: [PATCH 04/93] armv8: Support loading 32-bit OS which is not in the
+ form of FIT
+
+As only FIT image is supported now, this patch is to support loading
+32-bit uImage, dtb and rootfs separately.
+
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+---
+ include/image.h |    3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/include/image.h b/include/image.h
+index 299d6d2..0ea5f8e 100644
+--- a/include/image.h
+++ b/include/image.h
+@@ -694,7 +694,8 @@ static inline int image_check_type(const image_header_t *hdr, uint8_t type)
+ }
+ static inline int image_check_arch(const image_header_t *hdr, uint8_t arch)
+ {
+-	return (image_get_arch(hdr) == arch);
+	return (image_get_arch(hdr) == arch) ||
+		(image_get_arch(hdr) == IH_ARCH_ARM && arch == IH_ARCH_ARM64);
+ }
+ static inline int image_check_os(const image_header_t *hdr, uint8_t os)
+ {
+-- 
+1.7.9.5
+
--- a/package/boot/uboot-layerscape/patches/0005-armv8-set-openwrt-lede-default-boot-env-for-ls1043ar.patch
+++ b/package/boot/uboot-layerscape/patches/0005-armv8-set-openwrt-lede-default-boot-env-for-ls1043ar.patch
@ -0,0 +1,68 @@
+From 3c22f3fcbdb9f919ebdfa87a2ec237ac2abb7e03 Mon Sep 17 00:00:00 2001
+From: Yutang Jiang <yutang.jiang@nxp.com>
+Date: Thu, 27 Oct 2016 23:45:45 +0800
+Subject: [PATCH 05/93] armv8: set openwrt/lede default boot env for
+ ls1043ardb
+
+Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
+---
+ include/configs/ls1043a_common.h |   28 +++++++++++++++++++++++++---
+ 1 file changed, 25 insertions(+), 3 deletions(-)
+
+diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
+index 68678f3..1db05bb 100644
+--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
+@@ -273,6 +273,16 @@
+ 			"5m(kernel),1m(dtb),9m(file_system)"
+ #endif
+ 
+#define WRTBOOT_DEFAULT "setenv bootargs root=/dev/mtdblock6 " \
+	"rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 " \
+	"console=ttyS0,115200 mtdparts=60000000.nor:1M(rcw),1M(u-boot)," \
+	"1M(u-boot-env),1M(fman),1M(dtb),5M(kernel),54M(rootfs),64M(otherbank)" \
+	" && cp.b 60400000 $fdtaddr 100000 && cp.b 60500000 $loadaddr 500000" \
+	" && bootm $loadaddr - $fdtaddr"
+#define WRTUPDATE_DEFAULT "tftp a0000000 <tftp_folder>/" \
+	"lede-layerscape-64b-ls1043ardb-squashfs-firmware.bin && protect off all" \
+	" && erase 60000000 +4000000 && cp.b a0000000 60000000 $filesize && reset"
+
+ /* Initial environment variables */
+ #define CONFIG_EXTRA_ENV_SETTINGS		\
+ 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+@@ -286,6 +296,19 @@
+ 	"kernel_load=0xa0000000\0"		\
+ 	"kernel_size=0x2800000\0"		\
+ 	"console=ttyAMA0,38400n8\0"		\
+	"ethaddr=00:e0:0c:00:77:00\0"	\
+	"eth1addr=00:e0:0c:00:77:01\0"	\
+	"eth2addr=00:e0:0c:00:77:02\0"	\
+	"eth3addr=00:e0:0c:00:77:03\0"	\
+	"eth4addr=00:e0:0c:00:77:04\0"	\
+	"eth5addr=00:e0:0c:00:77:05\0"	\
+	"eth6addr=00:e0:0c:00:77:06\0"	\
+	"ethact=FM1@DTSEC2\0"			\
+	"loadaddr=82000000\0"			\
+	"ramdiskaddr=88000000\0"		\
+	"fdtaddr=8f000000\0"			\
+	"wrtboot=" WRTBOOT_DEFAULT "\0"	\
+	"wrtupdate=" WRTUPDATE_DEFAULT "\0"	\
+ 	"mtdparts=" MTDPARTS_DEFAULT "\0"
+ 
+ #define CONFIG_BOOTARGS			"console=ttyS0,115200 root=/dev/ram0 " \
+@@ -296,10 +319,9 @@
+ #define CONFIG_BOOTCOMMAND		"sf probe && sf read $kernel_load "    \
+ 					"e0000 f00000 && bootm $kernel_load"
+ #else
+-#define CONFIG_BOOTCOMMAND		"cp.b $kernel_start $kernel_load "     \
+-					"$kernel_size && bootm $kernel_load"
+#define CONFIG_BOOTCOMMAND		"run wrtboot"
+ #endif
+-#define CONFIG_BOOTDELAY		10
+#define CONFIG_BOOTDELAY		3
+ 
+ /* Monitor Command Prompt */
+ #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+-- 
+1.7.9.5
+
--- a/package/firmware/fman-ucode/Makefile
+++ b/package/firmware/fman-ucode/Makefile
@ -0,0 +1,84 @@
+#
+# Copyright (C) 2016 Jiang Yutang <jiangyutang1978@gmail.com>
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/image.mk
+
+PKG_NAME:=fman-ucode
+PKG_VERSION:=fsl-sdk-v2.0
+PKG_RELEASE:=1
+
+PKG_SOURCE_PROTO:=git
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
+PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
+PKG_SOURCE_URL:=http://git.freescale.com/git/cgit.cgi/ppc/sdk/fm-ucode.git
+PKG_SOURCE_VERSION:=b19c645821941493fbef32e616b5a16404259976
+
+PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
+
+PKG_LICENSE:=GPL-2.0 GPL-2.0+
+PKG_LICENSE_FILES:=Licenses/README
+
+include $(INCLUDE_DIR)/package.mk
+
+define fman/Default
+	TITLE:=
+	CONFIG:=
+endef
+
+define fman/ls1043ardb
+	TITLE=FMAN UCODE $(PKG_NAME)-$(PKG_VERSION) for NXP ls1043ardb 64b/32b Dev Board
+	CONFIG=fsl_fman_ucode_ls1043_r1.0_108_4_5.bin
+endef
+
+FMANS := \
+	ls1043ardb
+
+define Package/fman/template
+define Package/fman-layerscape-$(1)
+	SECTION:=firmware
+	CATEGORY:=Firmware
+	DEPENDS:=@TARGET_layerscape
+	TITLE:=$(2)
+	URL:=http://git.freescale.com/git/cgit.cgi/ppc/sdk/fm-ucode.git
+	VARIANT:=$(1)
+	MAINTAINER:=Jiang Yutang <jiangyutang1978@gmail.com>
+endef
+endef
+
+define BuildFMANPackage
+	$(eval $(fman/Default))
+	$(eval $(fman/$(1)))
+	$(call Package/fman/template,$(1),$(TITLE))
+endef
+
+ifdef BUILD_VARIANT
+$(eval $(call fman/$(BUILD_VARIANT)))
+FMAN_CONFIG:=$(if $(CONFIG),$(CONFIG),$(BUILD_VARIANT))
+endif
+
+define Build/Compile
+endef
+
+define Package/fman/install/default
+	$(CP) $(PKG_BUILD_DIR)/$(FMAN_CONFIG) $(KDIR)/$(1)-fman.bin
+endef
+
+define Package/fman/install/template
+define Package/fman-layerscape-$(1)/install
+	$(call Package/fman/install/default,$(2))
+endef
+endef
+
+$(foreach f,$(FMANS), \
+	$(eval $(call Package/fman/install/template,$(f),$(f))) \
+)
+
+$(foreach f,$(FMANS), \
+	$(eval $(call BuildFMANPackage,$(f))) \
+	$(eval $(call BuildPackage,fman-layerscape-$(f))) \
+)
--- a/package/firmware/rcw/Makefile
+++ b/package/firmware/rcw/Makefile
@ -0,0 +1,87 @@
+#
+# Copyright (C) 2016 Jiang Yutang <jiangyutang1978@gmail.com>
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/image.mk
+
+PKG_NAME:=rcw
+PKG_VERSION:=v1.0
+PKG_RELEASE:=1
+
+PKG_SOURCE_PROTO:=git
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
+PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
+PKG_SOURCE_URL:=https://github.com/fsl-jyt/rcw.git
+PKG_SOURCE_VERSION:=4c74045c34375ee0cf6a9bbd57ef8f00a5a01fd6
+
+PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION)
+
+PKG_LICENSE:=GPL-2.0 GPL-2.0+
+PKG_LICENSE_FILES:=Licenses/README
+
+include $(INCLUDE_DIR)/package.mk
+
+define rcw/Default
+	TITLE:=
+	CONFIG:=
+endef
+
+define rcw/ls1043ardb
+	TITLE=RCW binary $(PKG_NAME)-$(PKG_VERSION) for NXP ls1043ardb 64b/32b Dev Board
+	CONFIG=ls1043ardb-rcw.bin
+endef
+
+RCWS := \
+	ls1043ardb
+
+define Package/rcw/template
+define Package/rcw-layerscape-$(1)
+	SECTION:=firmware
+	CATEGORY:=Firmware
+	DEPENDS:= @TARGET_layerscape
+	TITLE:=$(2)
+	URL:=http://git.freescale.com/git/cgit.cgi/ppc/sdk/rcw.git
+	VARIANT:=$(1)
+	MAINTAINER:=Jiang Yutang <jiangyutang1978@gmail.com>
+endef
+endef
+
+define BuildRCWPackage
+	$(eval $(rcw/Default))
+	$(eval $(rcw/$(1)))
+	$(call Package/rcw/template,$(1),$(TITLE))
+endef
+
+ifdef BUILD_VARIANT
+$(eval $(call rcw/$(BUILD_VARIANT)))
+RCW_CONFIG:=$(if $(CONFIG),$(CONFIG),$(BUILD_VARIANT))
+endif
+
+define Build/Configure
+endef
+
+define Build/Compile
+endef
+
+define Package/rcw/install/default
+	$(CP) $(PKG_BUILD_DIR)/$(RCW_CONFIG) $(KDIR)/$(1)-rcw.bin
+endef
+
+define Package/rcw/install/template
+define Package/rcw-layerscape-$(1)/install
+	$(call Package/rcw/install/default,$(2))
+endef
+endef
+
+$(foreach r,$(RCWS), \
+	$(eval $(call Package/rcw/install/template,$(r),$(r))) \
+)
+
+$(foreach r,$(RCWS), \
+	$(eval $(call BuildRCWPackage,$(r))) \
+	$(eval $(call BuildPackage,rcw-layerscape-$(r))) \
+)
--- a/target/linux/layerscape/32b/config-default
+++ b/target/linux/layerscape/32b/config-default
@ -0,0 +1,153 @@
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_ARCH_AXXIA is not set
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_MULTI_CPU_AUTO is not set
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_MXC=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARM=y
+# CONFIG_ARM_CPU_SUSPEND is not set
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_ARM_ERRATA_775420=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_HEAVY_MB=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_LPAE=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_PMU=y
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CLKSRC_IMX_GPT=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_HAS_ASID=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_PABRT_V7=y
+# CONFIG_CPU_THERMAL is not set
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_XZ=y
+CONFIG_DEBUG_IMX_UART_PORT=1
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+# CONFIG_DEBUG_UART_8250 is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_EDAC_ATOMIC_SCRUB=y
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+CONFIG_EXTCON=y
+CONFIG_FEC=y
+# CONFIG_FSL_QMAN_FQ_LOOKUP is not set
+# CONFIG_FTRACE_SYSCALLS is not set
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GPIO_MXC=y
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IMX_SRC=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SMP=y
+CONFIG_HZ_FIXED=0
+# CONFIG_IMX_WEIM is not set
+CONFIG_MICREL_PHY=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGHT_HAVE_PCI=y
+# CONFIG_MMC_SDHCI_ESDHC_IMX is not set
+# CONFIG_MMC_MXC is not set
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MULTI_IRQ_HANDLER=y
+CONFIG_NEON=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PAGE_OFFSET=0x80000000
+# CONFIG_PATA_IMX is not set
+CONFIG_PERF_EVENTS=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PL310_ERRATA_588369=y
+CONFIG_PL310_ERRATA_727915=y
+# CONFIG_PL310_ERRATA_753970 is not set
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_PM_OPP=y
+CONFIG_PPS=y
+# CONFIG_PROBE_EVENTS is not set
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_IMXDI is not set
+# CONFIG_RTC_DRV_MXC is not set
+# CONFIG_SERIAL_IMX is not set
+CONFIG_SMP_ON_UP=y
+CONFIG_SOC_BUS=y
+# CONFIG_SOC_IMX50 is not set
+# CONFIG_SOC_IMX51 is not set
+# CONFIG_SOC_IMX53 is not set
+# CONFIG_SOC_IMX6Q is not set
+# CONFIG_SOC_IMX6SL is not set
+# CONFIG_SOC_IMX6SX is not set
+# CONFIG_SOC_IMX6UL is not set
+# CONFIG_SOC_IMX7D is not set
+# CONFIG_SOC_LS1021A is not set
+# CONFIG_SOC_VF610 is not set
+# CONFIG_SPI_IMX is not set
+CONFIG_SRAM=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_TRACING_EVENTS_GPIO=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+# CONFIG_USB_IMX21_HCD is not set
+CONFIG_USE_OF=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZONE_DMA_FLAG=0
--- a/target/linux/layerscape/32b/profiles/00-default.mk
+++ b/target/linux/layerscape/32b/profiles/00-default.mk
@ -0,0 +1 @@
+../../64b/profiles/00-default.mk
--- a/target/linux/layerscape/32b/target.mk
+++ b/target/linux/layerscape/32b/target.mk
@ -0,0 +1,14 @@
+#
+# Copyright (C) 2016 Jiang Yutang <jiangyutang1978@gmail.com>
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+ARCH:=arm
+BOARDNAME:=layerscape 32b boards
+CPU_TYPE:=cortex-a9
+
+define Target/Description
+	Build firmware images for $(BOARDNAME) SoC devices.
+endef
--- a/target/linux/layerscape/64b/config-default
+++ b/target/linux/layerscape/64b/config-default
@ -0,0 +1,183 @@
+CONFIG_64BIT=y
+CONFIG_ACPI=y
+CONFIG_ACPI_CCA_REQUIRED=y
+# CONFIG_ACPI_CONTAINER is not set
+# CONFIG_ACPI_CUSTOM_DSDT is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_DEBUGGER is not set
+# CONFIG_ACPI_DOCK is not set
+# CONFIG_ACPI_EC_DEBUGFS is not set
+CONFIG_ACPI_FAN=y
+CONFIG_ACPI_GENERIC_GSI=y
+# CONFIG_ACPI_PCI_SLOT is not set
+CONFIG_ACPI_PROCESSOR=y
+CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
+CONFIG_ACPI_THERMAL=y
+# CONFIG_ARCH_BCM_IPROC is not set
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+# CONFIG_ARCH_EXYNOS7 is not set
+CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
+CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
+# CONFIG_ARCH_SEATTLE is not set
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+# CONFIG_ARCH_SPRD is not set
+# CONFIG_ARCH_STRATIX10 is not set
+# CONFIG_ARCH_THUNDER is not set
+CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
+CONFIG_ARCH_WANT_FRAME_POINTERS=y
+CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
+# CONFIG_ARCH_XGENE is not set
+# CONFIG_ARCH_ZYNQMP is not set
+CONFIG_ARM64=y
+# CONFIG_ARM64_16K_PAGES is not set
+CONFIG_ARM64_4K_PAGES=y
+# CONFIG_ARM64_64K_PAGES is not set
+# CONFIG_ARM64_CRYPTO is not set
+CONFIG_ARM64_ERRATUM_819472=y
+CONFIG_ARM64_ERRATUM_824069=y
+CONFIG_ARM64_ERRATUM_826319=y
+CONFIG_ARM64_ERRATUM_827319=y
+CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_845719=y
+CONFIG_ARM64_HW_AFDBM=y
+# CONFIG_ARM64_LSE_ATOMICS is not set
+CONFIG_ARM64_PAN=y
+# CONFIG_ARM64_PTDUMP is not set
+# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
+CONFIG_ARM64_VA_BITS=39
+CONFIG_ARM64_VA_BITS_39=y
+# CONFIG_ARM64_VA_BITS_48 is not set
+# CONFIG_ARMV8_DEPRECATED is not set
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+# CONFIG_ARM_PL172_MPMC is not set
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_SP805_WATCHDOG is not set
+CONFIG_ATOMIC64_SELFTEST=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_BLOCK_COMPAT=y
+CONFIG_BOUNCE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_BUILD_BIN2C=y
+# CONFIG_CAVIUM_ERRATUM_22375 is not set
+# CONFIG_CAVIUM_ERRATUM_23154 is not set
+CONFIG_CLKSRC_ACPI=y
+CONFIG_CLK_SP810=y
+CONFIG_CLK_VEXPRESS_OSC=y
+CONFIG_CMDLINE="console=ttyAMA0"
+CONFIG_COMMON_CLK_VERSATILE=y
+CONFIG_COMMON_CLK_XGENE=y
+CONFIG_COMPAT=y
+CONFIG_COMPAT_BINFMT_ELF=y
+CONFIG_COMPAT_NETLINK_MESSAGES=y
+CONFIG_COMPAT_OLD_SIGACTION=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CUSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEFAULT_IOSCHED="noop"
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DMI=y
+CONFIG_DMIID=y
+# CONFIG_DMI_SYSFS is not set
+CONFIG_EFI=y
+# CONFIG_EFIVAR_FS is not set
+CONFIG_EFI_ARMSTUB=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_PARAMS_FROM_FDT=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_STUB=y
+# CONFIG_EFI_VARS is not set
+CONFIG_FSL_MC_BUS=y
+CONFIG_FSL_QMAN_FQ_LOOKUP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIO_ACPI=y
+# CONFIG_GPIO_AMDPT is not set
+# CONFIG_GPIO_XGENE is not set
+CONFIG_GRACE_PERIOD=y
+CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
+CONFIG_HAVE_ARCH_KASAN=y
+CONFIG_HAVE_CMPXCHG_DOUBLE=y
+CONFIG_HAVE_CMPXCHG_LOCAL=y
+CONFIG_HAVE_DEBUG_BUGVERBOSE=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_HAVE_PATA_PLATFORM=y
+# CONFIG_HPET is not set
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_JBD2=y
+# CONFIG_LIQUIDIO is not set
+CONFIG_LOCKD=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_CLUT224=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_VEXPRESS_SYSREG=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NFS_FS=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NO_HZ=y
+CONFIG_PCI_BUS_ADDR_T_64BIT=y
+# CONFIG_PCI_HISI is not set
+CONFIG_PCI_LABEL=y
+# CONFIG_PHY_XGENE is not set
+# CONFIG_PMIC_OPREGION is not set
+CONFIG_PNP=y
+CONFIG_PNPACPI=y
+CONFIG_PNP_DEBUG_MESSAGES=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_PROFILING=y
+# CONFIG_POWER_RESET_VEXPRESS is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_SERIAL_8250_PNP=y
+# CONFIG_SERIAL_AMBA_PL010 is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SMC91X=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SUNRPC=y
+# CONFIG_SWAP is not set
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSVIPC_COMPAT=y
+# CONFIG_THUNDER_NIC_BGX is not set
+# CONFIG_THUNDER_NIC_PF is not set
+# CONFIG_THUNDER_NIC_VF is not set
+CONFIG_UCS2_STRING=y
+CONFIG_VEXPRESS_CONFIG=y
+CONFIG_VEXPRESS_SYSCFG=y
+CONFIG_VFAT_FS=y
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_BLK=y
+# CONFIG_VIRTIO_CONSOLE is not set
+CONFIG_VIRTIO_MMIO=y
+# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
+CONFIG_VIRTIO_NET=y
--- a/target/linux/layerscape/64b/profiles/00-default.mk
+++ b/target/linux/layerscape/64b/profiles/00-default.mk
@ -0,0 +1,14 @@
+define Profile/Default
+	NAME:=Default Profile
+	PRIORITY:=1
+endef
+
+define Profile/Default/Description
+	Default package set compatible with most boards.
+endef
+
+DEFAULT_PACKAGES+= \
+	rcw-layerscape-ls1043ardb uboot-layerscape-$(SUBTARGET)-ls1043ardb \
+	fman-layerscape-ls1043ardb
+
+$(eval $(call Profile,Default))
--- a/target/linux/layerscape/64b/target.mk
+++ b/target/linux/layerscape/64b/target.mk
@ -0,0 +1,15 @@
+#
+# Copyright (C) 2016 Jiang Yutang <jiangyutang1978@gmail.com>
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+ARCH:=aarch64
+BOARDNAME:=layerscape 64b boards
+CFLAGS:=-Os -pipe -fno-caller-saves
+
+define Target/Description
+	Build firmware images for $(BOARDNAME) SoC devices.
+endef
+
--- a/target/linux/layerscape/Makefile
+++ b/target/linux/layerscape/Makefile
@ -0,0 +1,26 @@
+#
+# Copyright (C) 2016 Jiang Yutang <jiangyutang1978@gmail.com>
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+include $(TOPDIR)/rules.mk
+
+BOARD:=layerscape
+BOARDNAME:=NXP Layerscape
+DEVICE_TYPE:=developerboard
+KERNEL_PATCHVER:=4.4
+KERNELNAME:=Image dtbs
+FEATURES:=squashfs nand usb pcie gpio
+SUBTARGETS:=64b 32b
+MAINTAINER:=Jiang Yutang <jiangyutang1978@gmail.com>
+
+include $(INCLUDE_DIR)/target.mk
+
+define Target/Description
+	Build firmware images for $(BOARDNAME) SoC devices.
+endef
+
+DEFAULT_PACKAGES += kmod-usb3 kmod-usb-dwc3 kmod-usb-storage
+
+$(eval $(call BuildTarget))
--- a/target/linux/layerscape/config-4.4
+++ b/target/linux/layerscape/config-4.4
@ -0,0 +1,296 @@
+CONFIG_AQUANTIA_PHY=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_LAYERSCAPE=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_GIC=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CAVIUM_ERRATUM_27456 is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLKSRC_PROBE=y
+CONFIG_CLK_QORIQ=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DTC=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EXT4_FS=y
+CONFIG_FAT_FS=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FMAN_ARM=y
+# CONFIG_FMAN_MIB_CNT_OVF_IRQ_EN is not set
+# CONFIG_FMAN_P1023 is not set
+# CONFIG_FMAN_P3040_P4080_P5020 is not set
+# CONFIG_FMAN_PFC is not set
+# CONFIG_FMAN_V3H is not set
+# CONFIG_FMAN_V3L is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FSL_BMAN=y
+CONFIG_FSL_BMAN_CONFIG=y
+CONFIG_FSL_BMAN_DEBUGFS=y
+# CONFIG_FSL_BMAN_TEST is not set
+CONFIG_FSL_DPA=y
+# CONFIG_FSL_DPAA_1588 is not set
+CONFIG_FSL_DPAA_ADVANCED_DRIVERS=y
+# CONFIG_FSL_DPAA_CEETM is not set
+CONFIG_FSL_DPAA_CS_THRESHOLD_10G=0x10000000
+CONFIG_FSL_DPAA_CS_THRESHOLD_1G=0x06000000
+# CONFIG_FSL_DPAA_DBG_LOOP is not set
+# CONFIG_FSL_DPAA_ETH_DEBUG is not set
+CONFIG_FSL_DPAA_ETH_DEBUGFS=y
+CONFIG_FSL_DPAA_ETH_MAX_BUF_COUNT=128
+CONFIG_FSL_DPAA_ETH_REFILL_THRESHOLD=80
+CONFIG_FSL_DPAA_ETH_USE_NDO_SELECT_QUEUE=y
+CONFIG_FSL_DPAA_GENERIC_DRIVER=y
+# CONFIG_FSL_DPAA_HOOKS is not set
+CONFIG_FSL_DPAA_INGRESS_CS_THRESHOLD=0x10000000
+# CONFIG_FSL_DPAA_MACSEC is not set
+CONFIG_FSL_DPAA_OFFLINE_PORTS=y
+# CONFIG_FSL_DPAA_TS is not set
+CONFIG_FSL_DPA_CAN_WAIT=y
+CONFIG_FSL_DPA_CAN_WAIT_SYNC=y
+# CONFIG_FSL_DPA_CHECKING is not set
+CONFIG_FSL_DPA_PIRQ_FAST=y
+CONFIG_FSL_DPA_PIRQ_SLOW=y
+CONFIG_FSL_DPA_PORTAL_SHARE=y
+CONFIG_FSL_FM_MAX_FRAME_SIZE=1522
+CONFIG_FSL_FM_RX_EXTRA_HEADROOM=64
+CONFIG_FSL_IFC=y
+CONFIG_FSL_QMAN=y
+CONFIG_FSL_QMAN_CI_SCHED_CFG_BMAN_W=2
+CONFIG_FSL_QMAN_CI_SCHED_CFG_RW_W=2
+CONFIG_FSL_QMAN_CI_SCHED_CFG_SRCCIV=4
+CONFIG_FSL_QMAN_CI_SCHED_CFG_SRQ_W=3
+CONFIG_FSL_QMAN_CONFIG=y
+CONFIG_FSL_QMAN_DEBUGFS=y
+CONFIG_FSL_QMAN_FQD_SZ=10
+CONFIG_FSL_QMAN_INIT_TIMEOUT=10
+CONFIG_FSL_QMAN_PFDR_SZ=13
+CONFIG_FSL_QMAN_PIRQ_DQRR_ITHRESH=12
+CONFIG_FSL_QMAN_PIRQ_IPERIOD=100
+CONFIG_FSL_QMAN_PIRQ_MR_ITHRESH=4
+CONFIG_FSL_QMAN_POLL_LIMIT=32
+# CONFIG_FSL_QMAN_TEST is not set
+CONFIG_FSL_SDK_DPAA_ETH=y
+CONFIG_FSL_SDK_FMAN=y
+# CONFIG_FSL_SDK_FMAN_TEST is not set
+CONFIG_FSL_USDPAA=y
+CONFIG_FSL_XGMAC_MDIO=y
+# CONFIG_FTL is not set
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+# CONFIG_GIANFAR is not set
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_MPC8XXX=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_FSL_QBMAN=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_BPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_GENERIC_RCU_GUP=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_RCU_TABLE_FREE=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+# CONFIG_HUGETLBFS is not set
+CONFIG_I2C=y
+# CONFIG_ACPI_I2C_OPREGION is not set
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_IMX=y
+# CONFIG_IMX2_WDT is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IOMMU_HELPER=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LS_SCFG_MSI=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MEMORY=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+# CONFIG_MMC_SDHCI_PCI is not set
+# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_BE_BYTE_SWAP=y
+# CONFIG_MTD_CFI_GEOMETRY is not set
+# CONFIG_MTD_CFI_NOSWAP is not set
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=4
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_MTD=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+# CONFIG_PCIEASPM_DEBUG is not set
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYLIB=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_LAYERSCAPE=y
+# CONFIG_POWER_RESET_XGENE is not set
+CONFIG_POWER_SUPPLY=y
+CONFIG_QMAN_CEETM_UPDATE_PERIOD=1000
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_SCHED_HRTICK=y
+# CONFIG_SCHED_INFO is not set
+CONFIG_SCSI=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SMP=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_FILE_CACHE is not set
+CONFIG_SQUASHFS_FILE_DIRECT=y
+# CONFIG_SQUASHFS_DECOMP_SINGLE is not set
+# CONFIG_SQUASHFS_DECOMP_MULTI is not set
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+# CONFIG_SQUASHFS_XATTR is not set
+# CONFIG_SQUASHFS_ZLIB is not set
+# CONFIG_SQUASHFS_LZ4 is not set
+# CONFIG_SQUASHFS_LZO is not set
+CONFIG_SQUASHFS_XZ=y
+# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+CONFIG_SRCU=y
+CONFIG_SWIOTLB=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TREE_RCU=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB=y
+CONFIG_VITESSE_PHY=y
+CONFIG_XPS=y
+CONFIG_ZLIB_INFLATE=y
--- a/target/linux/layerscape/image/Makefile
+++ b/target/linux/layerscape/image/Makefile
@ -0,0 +1,60 @@
+#
+# Copyright (C) 2016 Jiang Yutang <jiangyutang1978@gmail.com>
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+include $(TOPDIR)/rules.mk
+include $(INCLUDE_DIR)/image.mk
+
+define Build/append-ls-rcw
+	rm -f $@
+	dd if=$(KDIR)/$(1)-rcw.bin >> $@
+endef
+
+define Build/append-ls-uboot
+	dd if=$(KDIR)/$(1)-$(SUBTARGET)-uboot.bin >> $@
+endef
+
+define Build/append-ls-fman
+	dd if=$(KDIR)/$(1)-fman.bin >> $@
+endef
+
+define Build/append-ls-dtb
+	$(call Image/BuildDTB,$(DTS_DIR)/$(1).dts,$(DTS_DIR)/$(1).dtb)
+	dd if=$(DTS_DIR)/$(1).dtb >> $@
+endef
+
+define Device/Default
+  PROFILES = Default
+  FILESYSTEMS := squashfs
+  KERNEL := kernel-bin | gzip | uImage gzip
+  DEVICE_DTS :=
+  IMAGES = firmware.bin
+
+ifeq ($(SUBTARGET),64b)
+  KERNEL_LOADADDR = 0x80080000
+  KERNEL_ENTRY_POINT = 0x80080000
+endif
+ifeq ($(SUBTARGET),32b)
+  KERNEL_LOADADDR = 0x80008000
+  KERNEL_ENTRY_POINT = 0x80008000
+endif
+endef
+
+define Device/ls1043ardb
+  DEVICE_TITLE := ls1043ardb-$(SUBTARGET)
+  DEVICE_PACKAGES += rcw-layerscape-ls1043ardb uboot-layerscape-$(SUBTARGET)-ls1043ardb fman-layerscape-ls1043ardb
+ifeq ($(SUBTARGET),64b)
+  DEVICE_DTS = freescale/fsl-ls1043a-rdb
+endif
+ifeq ($(SUBTARGET),32b)
+  DEVICE_DTS = ../../../arm64/boot/dts/freescale/fsl-ls1043a-rdb
+endif
+  IMAGE/firmware.bin = append-ls-rcw $(1) | pad-to 1M | append-ls-uboot $(1) | pad-to 3M | \
+  					append-ls-fman $(1) | pad-to 4M | append-ls-dtb $$(DEVICE_DTS) | pad-to 5M | \
+  					append-kernel | pad-to 10M | append-rootfs | pad-to 64M | check-size 67108865
+endef
+TARGET_DEVICES += ls1043ardb
+
+$(eval $(call BuildImage))
--- a/target/linux/layerscape/patches-4.4/0051-PCI-designware-Ensure-ATU-is-enabled-before-IO-conf-.patch
+++ b/target/linux/layerscape/patches-4.4/0051-PCI-designware-Ensure-ATU-is-enabled-before-IO-conf-.patch
@ -0,0 +1,43 @@
+From 7f434723cdb6823443330cd4847d5c3b8dd30bd7 Mon Sep 17 00:00:00 2001
+From: Stanimir Varbanov <stanimir.varbanov@linaro.org>
+Date: Fri, 18 Dec 2015 14:38:55 +0200
+Subject: [PATCH 51/70] PCI: designware: Ensure ATU is enabled before IO/conf
+ space accesses
+
+Read back the ATU CR2 register to ensure ATU programming is effective
+before any subsequent I/O or config space accesses.
+
+Without this, PCI device enumeration is unreliable.
+
+[bhelgaas: changelog, comment]
+Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
+---
+ drivers/pci/host/pcie-designware.c |    8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
+@@ -154,6 +154,8 @@ static int dw_pcie_wr_own_conf(struct pc
+ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
+ 		int type, u64 cpu_addr, u64 pci_addr, u32 size)
+ {
+	u32 val;
+
+ 	dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
+ 			  PCIE_ATU_VIEWPORT);
+ 	dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
+@@ -164,6 +166,12 @@ static void dw_pcie_prog_outbound_atu(st
+ 	dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET);
+ 	dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
+ 	dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
+
+	/*
+	 * Make sure ATU enable takes effect before any subsequent config
+	 * and I/O accesses.
+	 */
+	dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val);
+ }
+ 
+ static struct irq_chip dw_msi_irq_chip = {
--- a/target/linux/layerscape/patches-4.4/0052-PCI-designware-Simplify-control-flow.patch
+++ b/target/linux/layerscape/patches-4.4/0052-PCI-designware-Simplify-control-flow.patch
@ -0,0 +1,121 @@
+From 610b32220391c9d271290bdf8f2b8fe1cf8da9a0 Mon Sep 17 00:00:00 2001
+From: Bjorn Helgaas <bhelgaas@google.com>
+Date: Tue, 5 Jan 2016 15:48:11 -0600
+Subject: [PATCH 52/70] PCI: designware: Simplify control flow
+
+Return values immediately when possible to simplify the control flow.
+
+No functional change intended.  Folded in unused variable removal as
+pointed out by Fabio Estevam <fabio.estevam@nxp.com>, Arnd Bergmann
+<arnd@arndb.de>, and Thierry Reding <thierry.reding@gmail.com>.
+
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
+---
+ drivers/pci/host/pcie-designware.c |   54 ++++++++++++------------------------
+ 1 file changed, 18 insertions(+), 36 deletions(-)
+
+--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
+@@ -128,27 +128,19 @@ static inline void dw_pcie_writel_rc(str
+ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
+ 			       u32 *val)
+ {
+-	int ret;
+-
+ 	if (pp->ops->rd_own_conf)
+-		ret = pp->ops->rd_own_conf(pp, where, size, val);
+-	else
+-		ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val);
+		return pp->ops->rd_own_conf(pp, where, size, val);
+ 
+-	return ret;
+	return dw_pcie_cfg_read(pp->dbi_base + where, size, val);
+ }
+ 
+ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
+ 			       u32 val)
+ {
+-	int ret;
+-
+ 	if (pp->ops->wr_own_conf)
+-		ret = pp->ops->wr_own_conf(pp, where, size, val);
+-	else
+-		ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val);
+		return pp->ops->wr_own_conf(pp, where, size, val);
+ 
+-	return ret;
+	return dw_pcie_cfg_write(pp->dbi_base + where, size, val);
+ }
+ 
+ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
+@@ -392,8 +384,8 @@ int dw_pcie_link_up(struct pcie_port *pp
+ {
+ 	if (pp->ops->link_up)
+ 		return pp->ops->link_up(pp);
+-	else
+-		return 0;
+
+	return 0;
+ }
+ 
+ static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
+@@ -666,46 +658,36 @@ static int dw_pcie_rd_conf(struct pci_bu
+ 			int size, u32 *val)
+ {
+ 	struct pcie_port *pp = bus->sysdata;
+-	int ret;
+ 
+ 	if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
+ 		*val = 0xffffffff;
+ 		return PCIBIOS_DEVICE_NOT_FOUND;
+ 	}
+ 
+-	if (bus->number != pp->root_bus_nr)
+-		if (pp->ops->rd_other_conf)
+-			ret = pp->ops->rd_other_conf(pp, bus, devfn,
+-						where, size, val);
+-		else
+-			ret = dw_pcie_rd_other_conf(pp, bus, devfn,
+-						where, size, val);
+-	else
+-		ret = dw_pcie_rd_own_conf(pp, where, size, val);
+	if (bus->number == pp->root_bus_nr)
+		return dw_pcie_rd_own_conf(pp, where, size, val);
+ 
+-	return ret;
+	if (pp->ops->rd_other_conf)
+		return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
+
+	return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
+ }
+ 
+ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
+ 			int where, int size, u32 val)
+ {
+ 	struct pcie_port *pp = bus->sysdata;
+-	int ret;
+ 
+ 	if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
+ 		return PCIBIOS_DEVICE_NOT_FOUND;
+ 
+-	if (bus->number != pp->root_bus_nr)
+-		if (pp->ops->wr_other_conf)
+-			ret = pp->ops->wr_other_conf(pp, bus, devfn,
+-						where, size, val);
+-		else
+-			ret = dw_pcie_wr_other_conf(pp, bus, devfn,
+-						where, size, val);
+-	else
+-		ret = dw_pcie_wr_own_conf(pp, where, size, val);
+	if (bus->number == pp->root_bus_nr)
+		return dw_pcie_wr_own_conf(pp, where, size, val);
+ 
+-	return ret;
+	if (pp->ops->wr_other_conf)
+		return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
+
+	return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
+ }
+ 
+ static struct pci_ops dw_pcie_ops = {
--- a/target/linux/layerscape/patches-4.4/0053-PCI-designware-Make-config-accessor-override-checkin.patch
+++ b/target/linux/layerscape/patches-4.4/0053-PCI-designware-Make-config-accessor-override-checkin.patch
@ -0,0 +1,71 @@
+From 6882f9eef932e6f5cc3c57115e3d7d4b5bc19662 Mon Sep 17 00:00:00 2001
+From: Bjorn Helgaas <bhelgaas@google.com>
+Date: Tue, 5 Jan 2016 15:56:30 -0600
+Subject: [PATCH 53/70] PCI: designware: Make config accessor override
+ checking symmetric
+
+Drivers based on the DesignWare core can override the config read accessors
+by supplying rd_own_conf() and rd_other_conf() function pointers.
+dw_pcie_rd_conf() calls dw_pcie_rd_own_conf() (for accesses to the root
+bus) or dw_pcie_rd_other_conf():
+
+  dw_pcie_rd_conf
+    dw_pcie_rd_own_conf                # if on root bus
+    dw_pcie_rd_other_conf              # if not on root bus
+
+Previously we checked for rd_other_conf() directly in dw_pcie_rd_conf(),
+but we checked for rd_own_conf() in dw_pcie_rd_own_conf().
+
+Check for rd_other_conf() in dw_pcie_rd_other_conf() to make this symmetric
+with the rd_own_conf() checking, and similarly for the write path.
+
+No functional change intended.
+
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
+---
+ drivers/pci/host/pcie-designware.c |   12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
+@@ -571,6 +571,9 @@ static int dw_pcie_rd_other_conf(struct
+ 	u64 cpu_addr;
+ 	void __iomem *va_cfg_base;
+ 
+	if (pp->ops->rd_other_conf)
+		return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
+
+ 	busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
+ 		 PCIE_ATU_FUNC(PCI_FUNC(devfn));
+ 
+@@ -605,6 +608,9 @@ static int dw_pcie_wr_other_conf(struct
+ 	u64 cpu_addr;
+ 	void __iomem *va_cfg_base;
+ 
+	if (pp->ops->wr_other_conf)
+		return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
+
+ 	busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
+ 		 PCIE_ATU_FUNC(PCI_FUNC(devfn));
+ 
+@@ -667,9 +673,6 @@ static int dw_pcie_rd_conf(struct pci_bu
+ 	if (bus->number == pp->root_bus_nr)
+ 		return dw_pcie_rd_own_conf(pp, where, size, val);
+ 
+-	if (pp->ops->rd_other_conf)
+-		return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
+-
+ 	return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
+ }
+ 
+@@ -684,9 +687,6 @@ static int dw_pcie_wr_conf(struct pci_bu
+ 	if (bus->number == pp->root_bus_nr)
+ 		return dw_pcie_wr_own_conf(pp, where, size, val);
+ 
+-	if (pp->ops->wr_other_conf)
+-		return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
+-
+ 	return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
+ }
+ 
--- a/target/linux/layerscape/patches-4.4/0054-PCI-designware-Explain-why-we-don-t-program-ATU-for-.patch
+++ b/target/linux/layerscape/patches-4.4/0054-PCI-designware-Explain-why-we-don-t-program-ATU-for-.patch
@ -0,0 +1,34 @@
+From 481b1bc4ce0d58107887558342e50d6323a9601d Mon Sep 17 00:00:00 2001
+From: Jisheng Zhang <jszhang@marvell.com>
+Date: Thu, 7 Jan 2016 14:12:38 +0800
+Subject: [PATCH 54/70] PCI: designware: Explain why we don't program ATU for
+ some platforms
+
+Some platforms don't support ATU, e.g., pci-keystone.c.  These platforms
+use their own address translation component rather than ATU, and they
+provide the rd_other_conf and wr_other_conf methods to program the
+translation component and perform the access.
+
+Add a comment to explain why we don't program the ATU for these platforms.
+
+[bhelgaas: changelog]
+Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+---
+ drivers/pci/host/pcie-designware.c |    5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
+@@ -517,6 +517,11 @@ int dw_pcie_host_init(struct pcie_port *
+ 	if (pp->ops->host_init)
+ 		pp->ops->host_init(pp);
+ 
+	/*
+	 * If the platform provides ->rd_other_conf, it means the platform
+	 * uses its own address translation component rather than ATU, so
+	 * we should not program the ATU here.
+	 */
+ 	if (!pp->ops->rd_other_conf)
+ 		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
+ 					  PCIE_ATU_TYPE_MEM, pp->mem_base,
--- a/target/linux/layerscape/patches-4.4/0055-PCI-designware-Remove-PCI_PROBE_ONLY-handling.patch
+++ b/target/linux/layerscape/patches-4.4/0055-PCI-designware-Remove-PCI_PROBE_ONLY-handling.patch
@ -0,0 +1,41 @@
+From ee2a430c1691d0bac3098e8db3c29d8f023b04c2 Mon Sep 17 00:00:00 2001
+From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Date: Fri, 29 Jan 2016 11:29:32 +0000
+Subject: [PATCH 55/70] PCI: designware: Remove PCI_PROBE_ONLY handling
+
+The PCIe designware host driver is not used in system configurations
+requiring the PCI_PROBE_ONLY flag to be set to prevent resources
+assignment, therefore the driver code handling the flag can be removed
+from the kernel.
+
+Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
+Acked-by: Jingoo Han Jingoo Han <jingoohan1@gmail.com>
+Cc: Arnd Bergmann <arnd@arndb.de>
+Cc: Gabriele Paoloni <gabriele.paoloni@huawei.com>
+Cc: Zhou Wang <wangzhou1@hisilicon.com>
+---
+ drivers/pci/host/pcie-designware.c |   10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
+@@ -556,13 +556,11 @@ int dw_pcie_host_init(struct pcie_port *
+ 	pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
+ #endif
+ 
+-	if (!pci_has_flag(PCI_PROBE_ONLY)) {
+-		pci_bus_size_bridges(bus);
+-		pci_bus_assign_resources(bus);
+	pci_bus_size_bridges(bus);
+	pci_bus_assign_resources(bus);
+ 
+-		list_for_each_entry(child, &bus->children, node)
+-			pcie_bus_configure_settings(child);
+-	}
+	list_for_each_entry(child, &bus->children, node)
+		pcie_bus_configure_settings(child);
+ 
+ 	pci_bus_add_devices(bus);
+ 	return 0;
--- a/target/linux/layerscape/patches-4.4/0056-PCI-designware-Add-generic-dw_pcie_wait_for_link.patch
+++ b/target/linux/layerscape/patches-4.4/0056-PCI-designware-Add-generic-dw_pcie_wait_for_link.patch
@ -0,0 +1,249 @@
+From f0c3f31a8bd81b8e7354a187c49200f3ce52740d Mon Sep 17 00:00:00 2001
+From: Joao Pinto <Joao.Pinto@synopsys.com>
+Date: Thu, 10 Mar 2016 14:44:35 -0600
+Subject: [PATCH 56/70] PCI: designware: Add generic dw_pcie_wait_for_link()
+
+commit 886bc5ceb5cc3ad4b219502d72b277e3c3255a32 upstream
+[context adjustment]
+[remove drivers/pci/host/pcie-qcom.c related changes]
+
+Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and
+spear13xx) had similar loops waiting for the link to come up.
+
+Add a generic dw_pcie_wait_for_link() for use by all these drivers so the
+waiting is done consistently, e.g., always using usleep_range() rather than
+mdelay() and using similar timeouts and retry counts.
+
+Note that this changes the Keystone link training/wait for link strategy,
+so we initiate link training, then wait longer for the link to come up
+before re-initiating link training.
+
+[bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c]
+Signed-off-by: Joao Pinto <jpinto@synopsys.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ drivers/pci/host/pci-dra7xx.c      |   11 +----------
+ drivers/pci/host/pci-exynos.c      |   13 +++----------
+ drivers/pci/host/pci-imx6.c        |   13 ++++---------
+ drivers/pci/host/pci-keystone.c    |   10 ++++------
+ drivers/pci/host/pcie-designware.c |   19 +++++++++++++++++++
+ drivers/pci/host/pcie-designware.h |    6 ++++++
+ drivers/pci/host/pcie-spear13xx.c  |   14 +-------------
+ 7 files changed, 38 insertions(+), 48 deletions(-)
+
+--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
+@@ -10,7 +10,6 @@
+  * published by the Free Software Foundation.
+  */
+ 
+-#include <linux/delay.h>
+ #include <linux/err.h>
+ #include <linux/interrupt.h>
+ #include <linux/irq.h>
+@@ -108,7 +107,6 @@ static int dra7xx_pcie_establish_link(st
+ {
+ 	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
+ 	u32 reg;
+-	unsigned int retries;
+ 
+ 	if (dw_pcie_link_up(pp)) {
+ 		dev_err(pp->dev, "link is already up\n");
+@@ -119,14 +117,7 @@ static int dra7xx_pcie_establish_link(st
+ 	reg |= LTSSM_EN;
+ 	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
+ 
+-	for (retries = 0; retries < 1000; retries++) {
+-		if (dw_pcie_link_up(pp))
+-			return 0;
+-		usleep_range(10, 20);
+-	}
+-
+-	dev_err(pp->dev, "link is not up\n");
+-	return -EINVAL;
+	return dw_pcie_wait_for_link(pp);
+ }
+ 
+ static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp)
+--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
+@@ -318,7 +318,6 @@ static int exynos_pcie_establish_link(st
+ {
+ 	struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
+ 	u32 val;
+-	unsigned int retries;
+ 
+ 	if (dw_pcie_link_up(pp)) {
+ 		dev_err(pp->dev, "Link already up\n");
+@@ -357,13 +356,8 @@ static int exynos_pcie_establish_link(st
+ 			  PCIE_APP_LTSSM_ENABLE);
+ 
+ 	/* check if the link is up or not */
+-	for (retries = 0; retries < 10; retries++) {
+-		if (dw_pcie_link_up(pp)) {
+-			dev_info(pp->dev, "Link up\n");
+-			return 0;
+-		}
+-		mdelay(100);
+-	}
+	if (!dw_pcie_wait_for_link(pp))
+		return 0;
+ 
+ 	while (exynos_phy_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED) == 0) {
+ 		val = exynos_blk_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED);
+@@ -372,8 +366,7 @@ static int exynos_pcie_establish_link(st
+ 	/* power off phy */
+ 	exynos_pcie_power_off_phy(pp);
+ 
+-	dev_err(pp->dev, "PCIe Link Fail\n");
+-	return -EINVAL;
+	return -ETIMEDOUT;
+ }
+ 
+ static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp)
+--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
+@@ -330,19 +330,14 @@ static void imx6_pcie_init_phy(struct pc
+ 
+ static int imx6_pcie_wait_for_link(struct pcie_port *pp)
+ {
+-	unsigned int retries;
+	/* check if the link is up or not */
+	if (!dw_pcie_wait_for_link(pp))
+		return 0;
+ 
+-	for (retries = 0; retries < 200; retries++) {
+-		if (dw_pcie_link_up(pp))
+-			return 0;
+-		usleep_range(100, 1000);
+-	}
+-
+-	dev_err(pp->dev, "phy link never came up\n");
+ 	dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
+ 		readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
+ 		readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
+-	return -EINVAL;
+	return -ETIMEDOUT;
+ }
+ 
+ static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp)
+--- a/drivers/pci/host/pci-keystone.c
+++ b/drivers/pci/host/pci-keystone.c
+@@ -97,17 +97,15 @@ static int ks_pcie_establish_link(struct
+ 		return 0;
+ 	}
+ 
+-	ks_dw_pcie_initiate_link_train(ks_pcie);
+ 	/* check if the link is up or not */
+-	for (retries = 0; retries < 200; retries++) {
+-		if (dw_pcie_link_up(pp))
+-			return 0;
+-		usleep_range(100, 1000);
+	for (retries = 0; retries < 5; retries++) {
+ 		ks_dw_pcie_initiate_link_train(ks_pcie);
+		if (!dw_pcie_wait_for_link(pp))
+			return 0;
+ 	}
+ 
+ 	dev_err(pp->dev, "phy link never came up\n");
+-	return -EINVAL;
+	return -ETIMEDOUT;
+ }
+ 
+ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
+--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
+@@ -22,6 +22,7 @@
+ #include <linux/pci_regs.h>
+ #include <linux/platform_device.h>
+ #include <linux/types.h>
+#include <linux/delay.h>
+ 
+ #include "pcie-designware.h"
+ 
+@@ -380,6 +381,24 @@ static struct msi_controller dw_pcie_msi
+ 	.teardown_irq = dw_msi_teardown_irq,
+ };
+ 
+int dw_pcie_wait_for_link(struct pcie_port *pp)
+{
+	int retries;
+
+	/* check if the link is up or not */
+	for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
+		if (dw_pcie_link_up(pp)) {
+			dev_info(pp->dev, "link up\n");
+			return 0;
+		}
+		usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
+	}
+
+	dev_err(pp->dev, "phy link never came up\n");
+
+	return -ETIMEDOUT;
+}
+
+ int dw_pcie_link_up(struct pcie_port *pp)
+ {
+ 	if (pp->ops->link_up)
+--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
+@@ -22,6 +22,11 @@
+ #define MAX_MSI_IRQS			32
+ #define MAX_MSI_CTRLS			(MAX_MSI_IRQS / 32)
+ 
+/* Parameters for the waiting for link up routine */
+#define LINK_WAIT_MAX_RETRIES		10
+#define LINK_WAIT_USLEEP_MIN		90000
+#define LINK_WAIT_USLEEP_MAX		100000
+
+ struct pcie_port {
+ 	struct device		*dev;
+ 	u8			root_bus_nr;
+@@ -76,6 +81,7 @@ int dw_pcie_cfg_read(void __iomem *addr,
+ int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val);
+ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
+ void dw_pcie_msi_init(struct pcie_port *pp);
+int dw_pcie_wait_for_link(struct pcie_port *pp);
+ int dw_pcie_link_up(struct pcie_port *pp);
+ void dw_pcie_setup_rc(struct pcie_port *pp);
+ int dw_pcie_host_init(struct pcie_port *pp);
+--- a/drivers/pci/host/pcie-spear13xx.c
+++ b/drivers/pci/host/pcie-spear13xx.c
+@@ -13,7 +13,6 @@
+  */
+ 
+ #include <linux/clk.h>
+-#include <linux/delay.h>
+ #include <linux/interrupt.h>
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+@@ -149,7 +148,6 @@ static int spear13xx_pcie_establish_link
+ 	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+ 	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+ 	u32 exp_cap_off = EXP_CAP_ID_OFFSET;
+-	unsigned int retries;
+ 
+ 	if (dw_pcie_link_up(pp)) {
+ 		dev_err(pp->dev, "link already up\n");
+@@ -200,17 +198,7 @@ static int spear13xx_pcie_establish_link
+ 			| ((u32)1 << REG_TRANSLATION_ENABLE),
+ 			&app_reg->app_ctrl_0);
+ 
+-	/* check if the link is up or not */
+-	for (retries = 0; retries < 10; retries++) {
+-		if (dw_pcie_link_up(pp)) {
+-			dev_info(pp->dev, "link up\n");
+-			return 0;
+-		}
+-		mdelay(100);
+-	}
+-
+-	dev_err(pp->dev, "link Fail\n");
+-	return -EINVAL;
+	return dw_pcie_wait_for_link(pp);
+ }
+ 
+ static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
--- a/target/linux/layerscape/patches-4.4/0057-PCI-designware-Add-default-link-up-check-if-sub-driv.patch
+++ b/target/linux/layerscape/patches-4.4/0057-PCI-designware-Add-default-link-up-check-if-sub-driv.patch
@ -0,0 +1,46 @@
+From a0a4f406c7e90b2be66e88ea8b21699940c0823f Mon Sep 17 00:00:00 2001
+From: Joao Pinto <Joao.Pinto@synopsys.com>
+Date: Thu, 10 Mar 2016 14:44:44 -0600
+Subject: [PATCH 57/70] PCI: designware: Add default link up check if
+ sub-driver doesn't override
+
+Add a default DesignWare "link_up" test for use when a sub-driver doesn't
+supply its own pcie_host_ops.link_up() method.
+
+[bhelgaas: changelog, split into its own patch]
+Signed-off-by: Joao Pinto <jpinto@synopsys.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
+---
+ drivers/pci/host/pcie-designware.c |   10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
+@@ -70,6 +70,11 @@
+ #define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
+ #define PCIE_ATU_UPPER_TARGET		0x91C
+ 
+/* PCIe Port Logic registers */
+#define PLR_OFFSET			0x700
+#define PCIE_PHY_DEBUG_R1		(PLR_OFFSET + 0x2c)
+#define PCIE_PHY_DEBUG_R1_LINK_UP	0x00000010
+
+ static struct pci_ops dw_pcie_ops;
+ 
+ int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
+@@ -401,10 +406,13 @@ int dw_pcie_wait_for_link(struct pcie_po
+ 
+ int dw_pcie_link_up(struct pcie_port *pp)
+ {
+	u32 val;
+
+ 	if (pp->ops->link_up)
+ 		return pp->ops->link_up(pp);
+ 
+-	return 0;
+	val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
+	return val & PCIE_PHY_DEBUG_R1_LINK_UP;
+ }
+ 
+ static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
--- a/target/linux/layerscape/patches-4.4/0058-PCI-designware-Move-Root-Complex-setup-code-to-dw_pc.patch
+++ b/target/linux/layerscape/patches-4.4/0058-PCI-designware-Move-Root-Complex-setup-code-to-dw_pc.patch
@ -0,0 +1,109 @@
+From 892a427f8a2b25b561298941cf1fc0373a98b269 Mon Sep 17 00:00:00 2001
+From: Jisheng Zhang <jszhang@marvell.com>
+Date: Wed, 16 Mar 2016 19:40:33 +0800
+Subject: [PATCH 58/70] PCI: designware: Move Root Complex setup code to
+ dw_pcie_setup_rc()
+
+dw_pcie_host_init() looks up host bridge resources, ioremaps them, creates
+IRQ domains, and enumerates devices below the bridge.  dw_pcie_setup_rc()
+programs the Root Complex registers.  The Root Complex may lose power
+during suspend-to-RAM, and when we resume, we want to redo the latter but
+not the former.
+
+Move some Root Complex programming from dw_pcie_host_init() to
+dw_pcie_setup_rc() where it belongs.  DesignWare-based drivers can call
+dw_pcie_setup_rc() in their resume paths.
+
+[Niklas Cassel <niklas.cassel@axis.com>:  This change moves outbound ATU
+programming, which uses pp->mem_base, to dw_pcie_setup_rc().  Apply the
+dra7xx pp->mem_base update before calling dw_pcie_setup_rc().]
+
+[bhelgaas: changelog, fold in dra7xx fix from Niklas]
+Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
+---
+ drivers/pci/host/pci-dra7xx.c      |    4 ++--
+ drivers/pci/host/pcie-designware.c |   39 ++++++++++++++++++------------------
+ 2 files changed, 21 insertions(+), 22 deletions(-)
+
+--- a/drivers/pci/host/pci-dra7xx.c
+++ b/drivers/pci/host/pci-dra7xx.c
+@@ -142,13 +142,13 @@ static void dra7xx_pcie_enable_interrupt
+ 
+ static void dra7xx_pcie_host_init(struct pcie_port *pp)
+ {
+-	dw_pcie_setup_rc(pp);
+-
+ 	pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
+ 	pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
+ 	pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
+ 	pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR;
+ 
+	dw_pcie_setup_rc(pp);
+
+ 	dra7xx_pcie_establish_link(pp);
+ 	if (IS_ENABLED(CONFIG_PCI_MSI))
+ 		dw_pcie_msi_init(pp);
+--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
+@@ -434,7 +434,6 @@ int dw_pcie_host_init(struct pcie_port *
+ 	struct platform_device *pdev = to_platform_device(pp->dev);
+ 	struct pci_bus *bus, *child;
+ 	struct resource *cfg_res;
+-	u32 val;
+ 	int i, ret;
+ 	LIST_HEAD(res);
+ 	struct resource_entry *win;
+@@ -544,25 +543,6 @@ int dw_pcie_host_init(struct pcie_port *
+ 	if (pp->ops->host_init)
+ 		pp->ops->host_init(pp);
+ 
+-	/*
+-	 * If the platform provides ->rd_other_conf, it means the platform
+-	 * uses its own address translation component rather than ATU, so
+-	 * we should not program the ATU here.
+-	 */
+-	if (!pp->ops->rd_other_conf)
+-		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
+-					  PCIE_ATU_TYPE_MEM, pp->mem_base,
+-					  pp->mem_bus_addr, pp->mem_size);
+-
+-	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
+-
+-	/* program correct class for RC */
+-	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
+-
+-	dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
+-	val |= PORT_LOGIC_SPEED_CHANGE;
+-	dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
+-
+ 	pp->root_bus_nr = pp->busn->start;
+ 	if (IS_ENABLED(CONFIG_PCI_MSI)) {
+ 		bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr,
+@@ -800,6 +780,25 @@ void dw_pcie_setup_rc(struct pcie_port *
+ 	val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+ 		PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
+ 	dw_pcie_writel_rc(pp, val, PCI_COMMAND);
+
+	/*
+	 * If the platform provides ->rd_other_conf, it means the platform
+	 * uses its own address translation component rather than ATU, so
+	 * we should not program the ATU here.
+	 */
+	if (!pp->ops->rd_other_conf)
+		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
+					  PCIE_ATU_TYPE_MEM, pp->mem_base,
+					  pp->mem_bus_addr, pp->mem_size);
+
+	dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
+
+	/* program correct class for RC */
+	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
+
+	dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
+	val |= PORT_LOGIC_SPEED_CHANGE;
+	dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
+ }
+ 
+ MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
--- a/target/linux/layerscape/patches-4.4/0059-PCI-designware-Remove-incorrect-RC-memory-base-limit.patch
+++ b/target/linux/layerscape/patches-4.4/0059-PCI-designware-Remove-incorrect-RC-memory-base-limit.patch
@ -0,0 +1,45 @@
+From ae717a9744a3e18f2ed0a6aa44e279c89ad5052c Mon Sep 17 00:00:00 2001
+From: Gabriele Paoloni <gabriele.paoloni@huawei.com>
+Date: Sat, 16 Apr 2016 12:03:39 +0100
+Subject: [PATCH 59/70] PCI: designware: Remove incorrect RC memory base/limit
+ configuration
+
+Currently dw_pcie_setup_rc() configures memory base and memory limit in the
+type1 configuration header for the root complex.  In doing so it uses the
+CPU address (pp->mem_base) rather than the bus address (pp->mem_bus_addr).
+This is wrong and it is useless since the configuration is overwritten
+later on when pci_bus_assign_resources() is called.
+
+Remove this configuration from dw_pcie_setup_rc().
+
+Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
+---
+ drivers/pci/host/pcie-designware.c |    8 --------
+ 1 file changed, 8 deletions(-)
+
+--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
+@@ -708,8 +708,6 @@ static struct pci_ops dw_pcie_ops = {
+ void dw_pcie_setup_rc(struct pcie_port *pp)
+ {
+ 	u32 val;
+-	u32 membase;
+-	u32 memlimit;
+ 
+ 	/* set the number of lanes */
+ 	dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
+@@ -768,12 +766,6 @@ void dw_pcie_setup_rc(struct pcie_port *
+ 	val |= 0x00010100;
+ 	dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
+ 
+-	/* setup memory base, memory limit */
+-	membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
+-	memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000;
+-	val = memlimit | membase;
+-	dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
+-
+ 	/* setup command register */
+ 	dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
+ 	val &= 0xffff0000;
--- a/target/linux/layerscape/patches-4.4/2006-armv8-aarch32-Add-the-default-config-ls_aarch32_defc.patch
+++ b/target/linux/layerscape/patches-4.4/2006-armv8-aarch32-Add-the-default-config-ls_aarch32_defc.patch
@ -0,0 +1,209 @@
+From 4c4e5c275a0e37570d6267802e66a350b0b93dcd Mon Sep 17 00:00:00 2001
+From: Alison Wang <b18965@freescale.com>
+Date: Tue, 17 May 2016 17:30:19 +0800
+Subject: [PATCH 06/70] armv8: aarch32: Add the default config
+ ls_aarch32_defconfig
+
+ls_aarch32_defconfig is used as the default config for running 32-bit
+Linux.
+
+Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com>
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+---
+ arch/arm/configs/ls_aarch32_defconfig |  190 +++++++++++++++++++++++++++++++++
+ 1 file changed, 190 insertions(+)
+ create mode 100644 arch/arm/configs/ls_aarch32_defconfig
+
+--- /dev/null
+++ b/arch/arm/configs/ls_aarch32_defconfig
+@@ -0,0 +1,190 @@
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_CROSS_MEMORY_ATTACH is not set
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_JUMP_LABEL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_BLK_CMDLINE_PARSER=y
+CONFIG_ARCH_MXC=y
+CONFIG_ARCH_LAYERSCAPE=y
+CONFIG_ARM_LPAE=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_SMP=y
+CONFIG_VMSPLIT_2G=y
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_CLEANCACHE=y
+CONFIG_FRONTSWAP=y
+CONFIG_CMDLINE="console=ttyS0,115200"
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_KERNEL_MODE_NEON=y
+CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=y
+CONFIG_XFRM_USER=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_MROUTE=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_UDP_DIAG=y
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+CONFIG_CAN=y
+# CONFIG_CAN_BCM is not set
+# CONFIG_CAN_GW is not set
+CONFIG_CAN_FLEXCAN=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_BE_BYTE_SWAP=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_SST25L=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_SPI_FSL_QUADSPI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=8
+CONFIG_BLK_DEV_RAM_SIZE=262144
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_FREESCALE is not set
+CONFIG_E1000=y
+CONFIG_E1000E=y
+CONFIG_PHYLIB=y
+CONFIG_AT803X_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_MICREL_PHY=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+CONFIG_SERIO_SERPORT=m
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_IMX=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_FSL_DSPI=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_MPC8XXX=y
+CONFIG_SENSORS_LTC2945=y
+CONFIG_SENSORS_LM90=y
+CONFIG_SENSORS_INA2XX=y
+CONFIG_WATCHDOG=y
+CONFIG_IMX2_WDT=y
+CONFIG_MFD_SYSCON=y
+CONFIG_FB=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS3232=y
+CONFIG_DMADEVICES=y
+CONFIG_FSL_EDMA=y
+CONFIG_CLK_QORIQ=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_MEMORY=y
+CONFIG_PWM=y
+CONFIG_PWM_FSL_FTM=y
+# CONFIG_RESET_CONTROLLER is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS=y
+CONFIG_FANOTIFY=y
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=m
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_JFFS2_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_UTF8=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_SECTION_MISMATCH=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_PID_IN_CONTEXTIDR=y
+CONFIG_CRYPTO_LZO=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+CONFIG_CRC_CCITT=m
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m
--- a/target/linux/layerscape/patches-4.4/2027-armv8-aarch32-update-defconfig-for-LayerScape-SoC.patch
+++ b/target/linux/layerscape/patches-4.4/2027-armv8-aarch32-update-defconfig-for-LayerScape-SoC.patch
@ -0,0 +1,101 @@
+From 0cc4fd2e52f23f9b35dfdac80021da97ac6c2c52 Mon Sep 17 00:00:00 2001
+From: Pan Jiafei <Jiafei.Pan@nxp.com>
+Date: Tue, 24 May 2016 16:15:49 +0800
+Subject: [PATCH 27/70] armv8: aarch32: update defconfig for LayerScape SoC
+
+Enable QBMan, FMD, DPAA ethernet, kernel bridge, ATA,
+DMA_CMA, USB_STORAGE, PHY etc.
+
+Signed-off-by: Pan Jiafei <Jiafei.Pan@nxp.com>
+---
+ arch/arm/configs/ls_aarch32_defconfig |   20 +++++++++++++++++++-
+ 1 file changed, 19 insertions(+), 1 deletion(-)
+
+--- a/arch/arm/configs/ls_aarch32_defconfig
+++ b/arch/arm/configs/ls_aarch32_defconfig
+@@ -26,6 +26,7 @@ CONFIG_ARCH_MXC=y
+ CONFIG_ARCH_LAYERSCAPE=y
+ CONFIG_ARM_LPAE=y
+ # CONFIG_CACHE_L2X0 is not set
+CONFIG_HAS_FSL_QBMAN=y
+ CONFIG_PCI=y
+ CONFIG_PCI_MSI=y
+ CONFIG_PCI_HOST_GENERIC=y
+@@ -36,6 +37,7 @@ CONFIG_PREEMPT_VOLUNTARY=y
+ CONFIG_AEABI=y
+ CONFIG_HIGHMEM=y
+ CONFIG_CLEANCACHE=y
+CONFIG_CMA=y
+ CONFIG_FRONTSWAP=y
+ CONFIG_CMDLINE="console=ttyS0,115200"
+ CONFIG_CPU_FREQ=y
+@@ -62,6 +64,7 @@ CONFIG_INET_IPCOMP=y
+ CONFIG_INET_UDP_DIAG=y
+ # CONFIG_IPV6 is not set
+ CONFIG_NETFILTER=y
+CONFIG_BRIDGE=y
+ CONFIG_CAN=y
+ # CONFIG_CAN_BCM is not set
+ # CONFIG_CAN_GW is not set
+@@ -69,6 +72,7 @@ CONFIG_CAN_FLEXCAN=y
+ CONFIG_DEVTMPFS=y
+ CONFIG_DEVTMPFS_MOUNT=y
+ # CONFIG_FW_LOADER is not set
+CONFIG_DMA_CMA=y
+ CONFIG_MTD=y
+ CONFIG_MTD_CMDLINE_PARTS=y
+ CONFIG_MTD_BLOCK=y
+@@ -81,17 +85,26 @@ CONFIG_MTD_CFI_AMDSTD=y
+ CONFIG_MTD_CFI_STAA=y
+ CONFIG_MTD_PHYSMAP_OF=y
+ CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_M25P80=y
+ CONFIG_MTD_SST25L=y
+ CONFIG_MTD_NAND=y
+ CONFIG_MTD_NAND_FSL_IFC=y
+ CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+ CONFIG_SPI_FSL_QUADSPI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_ATA=y
+ CONFIG_BLK_DEV_LOOP=y
+ CONFIG_BLK_DEV_RAM=y
+ CONFIG_BLK_DEV_RAM_COUNT=8
+ CONFIG_BLK_DEV_RAM_SIZE=262144
+ CONFIG_NETDEVICES=y
+-# CONFIG_NET_VENDOR_FREESCALE is not set
+CONFIG_NET_VENDOR_FREESCALE is not set
+CONFIG_FSL_BMAN=y
+CONFIG_FSL_QMAN=y
+CONFIG_FSL_SDK_FMAN=y
+CONFIG_FMAN_ARM=y
+CONFIG_FSL_SDK_DPAA_ETH=y
+ CONFIG_E1000=y
+ CONFIG_E1000E=y
+ CONFIG_PHYLIB=y
+@@ -101,6 +114,8 @@ CONFIG_BROADCOM_PHY=y
+ CONFIG_REALTEK_PHY=y
+ CONFIG_NATIONAL_PHY=y
+ CONFIG_MICREL_PHY=y
+CONFIG_FIXED_PHY=y
+CONFIG_FSL_XGMAC_MDIO=y
+ CONFIG_MDIO_BUS_MUX_MMIOREG=y
+ CONFIG_INPUT_EVDEV=y
+ # CONFIG_MOUSE_PS2_TRACKPOINT is not set
+@@ -135,6 +150,8 @@ CONFIG_MFD_SYSCON=y
+ CONFIG_FB=y
+ CONFIG_USB=y
+ CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_STORAGE=y
+ CONFIG_MMC=y
+ CONFIG_MMC_SDHCI=y
+ CONFIG_MMC_SDHCI_PLTFM=y
+@@ -143,6 +160,7 @@ CONFIG_RTC_CLASS=y
+ CONFIG_RTC_DRV_DS3232=y
+ CONFIG_DMADEVICES=y
+ CONFIG_FSL_EDMA=y
+CONFIG_STAGING=y
+ CONFIG_CLK_QORIQ=y
+ # CONFIG_IOMMU_SUPPORT is not set
+ CONFIG_MEMORY=y
--- a/target/linux/layerscape/patches-4.4/3001-arm64-ls1043a-add-DTS-for-Freescale-LS1043A-SoC.patch
+++ b/target/linux/layerscape/patches-4.4/3001-arm64-ls1043a-add-DTS-for-Freescale-LS1043A-SoC.patch
@ -0,0 +1,552 @@
+From 3ce895cbe3469bfcaa84674ec4f1b2d60e8b370b Mon Sep 17 00:00:00 2001
+From: Mingkai Hu <Mingkai.Hu@freescale.com>
+Date: Mon, 21 Jul 2014 14:48:42 +0800
+Subject: [PATCH 01/70] arm64/ls1043a: add DTS for Freescale LS1043A SoC
+
+LS1043a is an SoC with 4 ARMv8 A53 cores and most other IP blocks
+similar to LS1021a which complies to Chassis 2.1 spec.
+
+Following levels of DTSI/DTS files have been created for the
+LS1043A SoC family:
+
+- fsl-ls1043a.dtsi:
+  DTS-Include file for FSL LS1043A SoC.
+
+Signed-off-by: Li Yang <leoli@freescale.com>
+Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
+Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
+Signed-off-by: Wenbin Song <Wenbin.Song@freescale.com>
+Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |  525 ++++++++++++++++++++++++
+ 1 file changed, 525 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+
+--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+@@ -0,0 +1,525 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright 2014-2015, Freescale Semiconductor
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/ {
+	compatible = "fsl,ls1043a";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		/*
+		 * We expect the enable-method for cpu's to be "psci", but this
+		 * is dependent on the SoC FW, which will fill this in.
+		 *
+		 * Currently supported enable-method is psci v0.2
+		 */
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x0>;
+			clocks = <&clockgen 1 0>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x1>;
+			clocks = <&clockgen 1 0>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x2>;
+			clocks = <&clockgen 1 0>;
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x3>;
+			clocks = <&clockgen 1 0>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0 0x80000000>;
+		      /* DRAM space 1, size: 2GiB DRAM */
+	};
+
+	sysclk: sysclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "sysclk";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <1 13 0x1>, /* Physical Secure PPI */
+			     <1 14 0x1>, /* Physical Non-Secure PPI */
+			     <1 11 0x1>, /* Virtual PPI */
+			     <1 10 0x1>; /* Hypervisor PPI */
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <0 106 0x4>,
+			     <0 107 0x4>,
+			     <0 95 0x4>,
+			     <0 97 0x4>;
+		interrupt-affinity = <&cpu0>,
+				     <&cpu1>,
+				     <&cpu2>,
+				     <&cpu3>;
+	};
+
+	gic: interrupt-controller@1400000 {
+		compatible = "arm,gic-400";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
+		      <0x0 0x1402000 0 0x2000>, /* GICC */
+		      <0x0 0x1404000 0 0x2000>, /* GICH */
+		      <0x0 0x1406000 0 0x2000>; /* GICV */
+		interrupts = <1 9 0xf08>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		clockgen: clocking@1ee1000 {
+			compatible = "fsl,ls1043a-clockgen";
+			reg = <0x0 0x1ee1000 0x0 0x1000>;
+			#clock-cells = <2>;
+			clocks = <&sysclk>;
+		};
+
+		scfg: scfg@1570000 {
+			compatible = "fsl,ls1043a-scfg", "syscon";
+			reg = <0x0 0x1570000 0x0 0x10000>;
+			big-endian;
+		};
+
+		dcfg: dcfg@1ee0000 {
+			compatible = "fsl,ls1043a-dcfg", "syscon";
+			reg = <0x0 0x1ee0000 0x0 0x10000>;
+		};
+
+		ifc: ifc@1530000 {
+			compatible = "fsl,ifc", "simple-bus";
+			reg = <0x0 0x1530000 0x0 0x10000>;
+			interrupts = <0 43 0x4>;
+		};
+
+		esdhc: esdhc@1560000 {
+			compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
+			reg = <0x0 0x1560000 0x0 0x10000>;
+			interrupts = <0 62 0x4>;
+			clock-frequency = <0>;
+			voltage-ranges = <1800 1800 3300 3300>;
+			sdhci,auto-cmd12;
+			big-endian;
+			bus-width = <4>;
+		};
+
+		dspi0: dspi@2100000 {
+			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2100000 0x0 0x10000>;
+			interrupts = <0 64 0x4>;
+			clock-names = "dspi";
+			clocks = <&clockgen 4 0>;
+			spi-num-chipselects = <5>;
+			big-endian;
+			status = "disabled";
+		};
+
+		dspi1: dspi@2110000 {
+			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2110000 0x0 0x10000>;
+			interrupts = <0 65 0x4>;
+			clock-names = "dspi";
+			clocks = <&clockgen 4 0>;
+			spi-num-chipselects = <5>;
+			big-endian;
+			status = "disabled";
+		};
+
+		i2c0: i2c@2180000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2180000 0x0 0x10000>;
+			interrupts = <0 56 0x4>;
+			clock-names = "i2c";
+			clocks = <&clockgen 4 0>;
+			dmas = <&edma0 1 39>,
+			       <&edma0 1 38>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		i2c1: i2c@2190000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2190000 0x0 0x10000>;
+			interrupts = <0 57 0x4>;
+			clock-names = "i2c";
+			clocks = <&clockgen 4 0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@21a0000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x21a0000 0x0 0x10000>;
+			interrupts = <0 58 0x4>;
+			clock-names = "i2c";
+			clocks = <&clockgen 4 0>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@21b0000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x21b0000 0x0 0x10000>;
+			interrupts = <0 59 0x4>;
+			clock-names = "i2c";
+			clocks = <&clockgen 4 0>;
+			status = "disabled";
+		};
+
+		duart0: serial@21c0500 {
+			compatible = "fsl,ns16550", "ns16550a";
+			reg = <0x00 0x21c0500 0x0 0x100>;
+			interrupts = <0 54 0x4>;
+			clocks = <&clockgen 4 0>;
+		};
+
+		duart1: serial@21c0600 {
+			compatible = "fsl,ns16550", "ns16550a";
+			reg = <0x00 0x21c0600 0x0 0x100>;
+			interrupts = <0 54 0x4>;
+			clocks = <&clockgen 4 0>;
+		};
+
+		duart2: serial@21d0500 {
+			compatible = "fsl,ns16550", "ns16550a";
+			reg = <0x0 0x21d0500 0x0 0x100>;
+			interrupts = <0 55 0x4>;
+			clocks = <&clockgen 4 0>;
+		};
+
+		duart3: serial@21d0600 {
+			compatible = "fsl,ns16550", "ns16550a";
+			reg = <0x0 0x21d0600 0x0 0x100>;
+			interrupts = <0 55 0x4>;
+			clocks = <&clockgen 4 0>;
+		};
+
+		gpio1: gpio@2300000 {
+			compatible = "fsl,ls1043a-gpio";
+			reg = <0x0 0x2300000 0x0 0x10000>;
+			interrupts = <0 66 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio2: gpio@2310000 {
+			compatible = "fsl,ls1043a-gpio";
+			reg = <0x0 0x2310000 0x0 0x10000>;
+			interrupts = <0 67 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio3: gpio@2320000 {
+			compatible = "fsl,ls1043a-gpio";
+			reg = <0x0 0x2320000 0x0 0x10000>;
+			interrupts = <0 68 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio4: gpio@2330000 {
+			compatible = "fsl,ls1043a-gpio";
+			reg = <0x0 0x2330000 0x0 0x10000>;
+			interrupts = <0 134 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		lpuart0: serial@2950000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x0 0x2950000 0x0 0x1000>;
+			interrupts = <0 48 0x4>;
+			clocks = <&clockgen 0 0>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		lpuart1: serial@2960000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x0 0x2960000 0x0 0x1000>;
+			interrupts = <0 49 0x4>;
+			clocks = <&clockgen 4 0>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		lpuart2: serial@2970000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x0 0x2970000 0x0 0x1000>;
+			interrupts = <0 50 0x4>;
+			clocks = <&clockgen 4 0>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		lpuart3: serial@2980000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x0 0x2980000 0x0 0x1000>;
+			interrupts = <0 51 0x4>;
+			clocks = <&clockgen 4 0>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		lpuart4: serial@2990000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x0 0x2990000 0x0 0x1000>;
+			interrupts = <0 52 0x4>;
+			clocks = <&clockgen 4 0>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		lpuart5: serial@29a0000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x0 0x29a0000 0x0 0x1000>;
+			interrupts = <0 53 0x4>;
+			clocks = <&clockgen 4 0>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		wdog0: wdog@2ad0000 {
+			compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
+			reg = <0x0 0x2ad0000 0x0 0x10000>;
+			interrupts = <0 83 0x4>;
+			clocks = <&clockgen 4 0>;
+			clock-names = "wdog";
+			big-endian;
+		};
+
+		edma0: edma@2c00000 {
+			#dma-cells = <2>;
+			compatible = "fsl,vf610-edma";
+			reg = <0x0 0x2c00000 0x0 0x10000>,
+			      <0x0 0x2c10000 0x0 0x10000>,
+			      <0x0 0x2c20000 0x0 0x10000>;
+			interrupts = <0 103 0x4>,
+				     <0 103 0x4>;
+			interrupt-names = "edma-tx", "edma-err";
+			dma-channels = <32>;
+			big-endian;
+			clock-names = "dmamux0", "dmamux1";
+			clocks = <&clockgen 4 0>,
+				 <&clockgen 4 0>;
+		};
+
+		usb0: usb3@2f00000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0x2f00000 0x0 0x10000>;
+			interrupts = <0 60 0x4>;
+			dr_mode = "host";
+		};
+
+		usb1: usb3@3000000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0x3000000 0x0 0x10000>;
+			interrupts = <0 61 0x4>;
+			dr_mode = "host";
+		};
+
+		usb2: usb3@3100000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0x3100000 0x0 0x10000>;
+			interrupts = <0 63 0x4>;
+			dr_mode = "host";
+		};
+
+		sata: sata@3200000 {
+			compatible = "fsl,ls1043a-ahci";
+			reg = <0x0 0x3200000 0x0 0x10000>;
+			interrupts = <0 69 0x4>;
+			clocks = <&clockgen 4 0>;
+		};
+
+		msi1: msi-controller1@1571000 {
+			compatible = "fsl,1s1043a-msi";
+			reg = <0x0 0x1571000 0x0 0x4>,
+			      <0x0 0x1571004 0x0 0x4>;
+			reg-names = "msiir", "msir";
+			msi-controller;
+			interrupts = <0 116 0x4>;
+		};
+
+		msi2: msi-controller2@1572000 {
+			compatible = "fsl,1s1043a-msi";
+			reg = <0x0 0x1572000 0x0 0x4>,
+			      <0x0 0x1572004 0x0 0x4>;
+			reg-names = "msiir", "msir";
+			msi-controller;
+			interrupts = <0 126 0x4>;
+		};
+
+		msi3: msi-controller3@1573000 {
+			compatible = "fsl,1s1043a-msi";
+			reg = <0x0 0x1573000 0x0 0x4>,
+			      <0x0 0x1573004 0x0 0x4>;
+			reg-names = "msiir", "msir";
+			msi-controller;
+			interrupts = <0 160 0x4>;
+		};
+
+		pcie@3400000 {
+			compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
+			       0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
+			interrupts = <0 118 0x4>, /* controller interrupt */
+				     <0 117 0x4>; /* PME interrupt */
+			interrupt-names = "intr", "pme";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			num-lanes = <4>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			msi-parent = <&msi1>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
+					<0000 0 0 2 &gic 0 111 0x4>,
+					<0000 0 0 3 &gic 0 112 0x4>,
+					<0000 0 0 4 &gic 0 113 0x4>;
+		};
+
+		pcie@3500000 {
+			compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
+			       0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
+			interrupts = <0 128 0x4>,
+				     <0 127 0x4>;
+			interrupt-names = "intr", "pme";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			num-lanes = <2>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			msi-parent = <&msi2>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
+					<0000 0 0 2 &gic 0 121 0x4>,
+					<0000 0 0 3 &gic 0 122 0x4>,
+					<0000 0 0 4 &gic 0 123 0x4>;
+		};
+
+		pcie@3600000 {
+			compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
+			       0x50 0x00000000 0x0 0x00002000>; /* configuration space */
+			reg-names = "regs", "config";
+			interrupts = <0 162 0x4>,
+				     <0 161 0x4>;
+			interrupt-names = "intr", "pme";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			num-lanes = <2>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+			msi-parent = <&msi3>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
+					<0000 0 0 2 &gic 0 155 0x4>,
+					<0000 0 0 3 &gic 0 156 0x4>,
+					<0000 0 0 4 &gic 0 157 0x4>;
+		};
+	};
+
+};
--- a/target/linux/layerscape/patches-4.4/3002-dts-ls1043a-add-LS1043ARDB-board-support.patch
+++ b/target/linux/layerscape/patches-4.4/3002-dts-ls1043a-add-LS1043ARDB-board-support.patch
@ -0,0 +1,150 @@
+From 57d949256241fb79b669bbca0426c2d74a3dfc6e Mon Sep 17 00:00:00 2001
+From: Shaohui Xie <Shaohui.Xie@freescale.com>
+Date: Fri, 8 Jul 2016 10:27:39 +0800
+Subject: [PATCH 02/70] dts/ls1043a: add LS1043ARDB board support
+
+commit 9a6fce16a82d3412c9350b9f08eacebaa81c0a3d
+[context adjustment]
+
+Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
+Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
+Signed-off-by: Wenbin Song <Wenbin.Song@freescale.com>
+Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
+Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
+Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
+---
+ arch/arm64/boot/dts/freescale/Makefile            |    1 +
+ arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts |  117 +++++++++++++++++++++
+ 2 files changed, 118 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+
+--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
+@@ -1,6 +1,7 @@
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
+  
+ always		:= $(dtb-y)
+ subdir-y	:= $(dts-dirs)
+--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+@@ -0,0 +1,117 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ *
+ * Copyright 2014-2015, Freescale Semiconductor
+ *
+ * Mingkai Hu <Mingkai.hu@freescale.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "fsl-ls1043a.dtsi"
+
+/ {
+	model = "LS1043A RDB Board";
+	compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
+};
+
+&i2c0 {
+	status = "okay";
+	ina220@40 {
+		compatible = "ti,ina220";
+		reg = <0x40>;
+		shunt-resistor = <1000>;
+	};
+	adt7461a@4c {
+		compatible = "adi,adt7461";
+		reg = <0x4c>;
+	};
+	eeprom@56 {
+		compatible = "at24,24c512";
+		reg = <0x52>;
+	};
+	eeprom@57 {
+		compatible = "at24,24c512";
+		reg = <0x53>;
+	};
+	rtc@68 {
+		compatible = "pericom,pt7c4338";
+		reg = <0x68>;
+	};
+};
+
+&ifc {
+	status = "okay";
+	#address-cells = <2>;
+	#size-cells = <1>;
+	/* NOR, NAND Flashes and FPGA on board */
+	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
+		  0x1 0x0 0x0 0x7e800000 0x00010000
+		  0x2 0x0 0x0 0x7fb00000 0x00000100>;
+
+		nor@0,0 {
+			compatible = "cfi-flash";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x0 0x0 0x8000000>;
+			bank-width = <2>;
+			device-width = <1>;
+		};
+
+		nand@1,0 {
+			compatible = "fsl,ifc-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x1 0x0 0x10000>;
+		};
+
+		cpld: board-control@2,0 {
+			compatible = "fsl,ls1043ardb-cpld";
+			reg = <0x2 0x0 0x0000100>;
+		};
+};
+
+&duart0 {
+	status = "okay";
+};
+
+&duart1 {
+	status = "okay";
+};
--- a/target/linux/layerscape/patches-4.4/3003-arm64-dts-Update-address-cells-and-reg-properties-of.patch
+++ b/target/linux/layerscape/patches-4.4/3003-arm64-dts-Update-address-cells-and-reg-properties-of.patch
@ -0,0 +1,141 @@
+From 3970a709eb4c25e298e11cfe0ea7412bb2139197 Mon Sep 17 00:00:00 2001
+From: Alison Wang <alison.wang@nxp.com>
+Date: Fri, 8 Jul 2016 10:50:46 +0800
+Subject: [PATCH 03/70] arm64: dts: Update address-cells and reg properties of
+ cpu nodes
+
+commit 67161e229a59faf81732892b45a9ab3bae62ea18
+[context adjustment]
+
+MPIDR_EL1[63:32] value is equal to 0 for the CPUs of the LS1043A and
+LS2080A SoCs. The ARM CPU binding allows #address-cells to be set to 1,
+since MPIDR_EL1[63:32] bits are not used for CPUs identification. Update
+the #address-cells and reg properties accordingly.
+
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |   10 +++++-----
+ arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi |   18 +++++++++---------
+ 2 files changed, 14 insertions(+), 14 deletions(-)
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+@@ -51,7 +51,7 @@
+ 	#size-cells = <2>;
+ 
+ 	cpus {
+-		#address-cells = <2>;
+		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 
+ 		/*
+@@ -63,28 +63,28 @@
+ 		cpu0: cpu@0 {
+ 			device_type = "cpu";
+ 			compatible = "arm,cortex-a53";
+-			reg = <0x0 0x0>;
+			reg = <0x0>;
+ 			clocks = <&clockgen 1 0>;
+ 		};
+ 
+ 		cpu1: cpu@1 {
+ 			device_type = "cpu";
+ 			compatible = "arm,cortex-a53";
+-			reg = <0x0 0x1>;
+			reg = <0x1>;
+ 			clocks = <&clockgen 1 0>;
+ 		};
+ 
+ 		cpu2: cpu@2 {
+ 			device_type = "cpu";
+ 			compatible = "arm,cortex-a53";
+-			reg = <0x0 0x2>;
+			reg = <0x2>;
+ 			clocks = <&clockgen 1 0>;
+ 		};
+ 
+ 		cpu3: cpu@3 {
+ 			device_type = "cpu";
+ 			compatible = "arm,cortex-a53";
+-			reg = <0x0 0x3>;
+			reg = <0x3>;
+ 			clocks = <&clockgen 1 0>;
+ 		};
+ 	};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+@@ -51,7 +51,7 @@
+ 	#size-cells = <2>;
+ 
+ 	cpus {
+-		#address-cells = <2>;
+		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 
+ 		/*
+@@ -65,56 +65,56 @@
+ 		cpu@0 {
+ 			device_type = "cpu";
+ 			compatible = "arm,cortex-a57";
+-			reg = <0x0 0x0>;
+			reg = <0x0>;
+ 			clocks = <&clockgen 1 0>;
+ 		};
+ 
+ 		cpu@1 {
+ 			device_type = "cpu";
+ 			compatible = "arm,cortex-a57";
+-			reg = <0x0 0x1>;
+			reg = <0x1>;
+ 			clocks = <&clockgen 1 0>;
+ 		};
+ 
+ 		cpu@100 {
+ 			device_type = "cpu";
+ 			compatible = "arm,cortex-a57";
+-			reg = <0x0 0x100>;
+			reg = <0x100>;
+ 			clocks = <&clockgen 1 1>;
+ 		};
+ 
+ 		cpu@101 {
+ 			device_type = "cpu";
+ 			compatible = "arm,cortex-a57";
+-			reg = <0x0 0x101>;
+			reg = <0x101>;
+ 			clocks = <&clockgen 1 1>;
+ 		};
+ 
+ 		cpu@200 {
+ 			device_type = "cpu";
+ 			compatible = "arm,cortex-a57";
+-			reg = <0x0 0x200>;
+			reg = <0x200>;
+ 			clocks = <&clockgen 1 2>;
+ 		};
+ 
+ 		cpu@201 {
+ 			device_type = "cpu";
+ 			compatible = "arm,cortex-a57";
+-			reg = <0x0 0x201>;
+			reg = <0x201>;
+ 			clocks = <&clockgen 1 2>;
+ 		};
+ 
+ 		cpu@300 {
+ 			device_type = "cpu";
+ 			compatible = "arm,cortex-a57";
+-			reg = <0x0 0x300>;
+			reg = <0x300>;
+ 			clocks = <&clockgen 1 3>;
+ 		};
+ 
+ 		cpu@301 {
+ 			device_type = "cpu";
+ 			compatible = "arm,cortex-a57";
+-			reg = <0x0 0x301>;
+			reg = <0x301>;
+ 			clocks = <&clockgen 1 3>;
+ 		};
+ 	};
--- a/target/linux/layerscape/patches-4.4/3004-armv8-aarch32-Add-ITS-file-for-AArch32-Linux-on-LS10.patch
+++ b/target/linux/layerscape/patches-4.4/3004-armv8-aarch32-Add-ITS-file-for-AArch32-Linux-on-LS10.patch
@ -0,0 +1,71 @@
+From 503f48a0a43ddf20098b2a5ec2c3d9d91775e441 Mon Sep 17 00:00:00 2001
+From: Alison Wang <b18965@freescale.com>
+Date: Wed, 9 Dec 2015 10:53:04 +0800
+Subject: [PATCH 04/70] armv8: aarch32: Add ITS file for AArch32 Linux on
+ LS1043ARDB
+
+kernel-ls1043a-rdb-aarch32.its is added to load kernel, DTB
+and root filesystrem together.
+
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+---
+ kernel-ls1043a-rdb-aarch32.its |   53 ++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 53 insertions(+)
+ create mode 100644 kernel-ls1043a-rdb-aarch32.its
+
+--- /dev/null
+++ b/kernel-ls1043a-rdb-aarch32.its
+@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/ {
+	description = "RDB Image file for the LS1043A Linux Kernel";
+	#address-cells = <1>;
+
+	images {
+		kernel@1 {
+			description = "ARM32 Linux kernel";
+			data = /incbin/("./arch/arm/boot/zImage");
+			type = "kernel";
+			arch = "arm";
+			os = "linux";
+			compression = "none";
+			load = <0x80008000>;
+			entry = <0x80008000>;
+		};
+		fdt@1 {
+			description = "Flattened Device Tree blob";
+			data = /incbin/("./fsl-ls1043a-rdb.dtb");
+			type = "flat_dt";
+			arch = "arm";
+			compression = "none";
+			load = <0x90000000>;
+		};
+		ramdisk@1 {
+			description = "LS1 Ramdisk";
+                        data = /incbin/("./fsl-image-core-ls1021atwr-wifi.rootfs.ext2.gz");
+			type = "ramdisk";
+			arch = "arm";
+			os = "linux";
+			compression = "none";
+		};
+	};
+
+	configurations {
+		default = "config@1";
+		config@1 {
+			description = "Boot Linux kernel";
+			kernel = "kernel@1";
+			fdt = "fdt@1";
+			ramdisk = "ramdisk@1";
+		};
+	};
+};
--- a/target/linux/layerscape/patches-4.4/3005-armv8-aarch32-change-FS-file-name-in-ITS.patch
+++ b/target/linux/layerscape/patches-4.4/3005-armv8-aarch32-change-FS-file-name-in-ITS.patch
@ -0,0 +1,21 @@
+From 8f9b9d829ea0e67760b2e67c9339f6c417084fdc Mon Sep 17 00:00:00 2001
+From: Pan Jiafei <Jiafei.Pan@nxp.com>
+Date: Thu, 28 Jan 2016 12:10:24 +0800
+Subject: [PATCH 05/70] armv8: aarch32: change FS file name in ITS
+
+Signed-off-by: Pan Jiafei <Jiafei.Pan@nxp.com>
+---
+ kernel-ls1043a-rdb-aarch32.its |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/kernel-ls1043a-rdb-aarch32.its
+++ b/kernel-ls1043a-rdb-aarch32.its
+@@ -33,7 +33,7 @@
+ 		};
+ 		ramdisk@1 {
+ 			description = "LS1 Ramdisk";
+-                        data = /incbin/("./fsl-image-core-ls1021atwr-wifi.rootfs.ext2.gz");
+                        data = /incbin/("./fsl-image-core-ls1043ardb-32b.ext2.gz");
+ 			type = "ramdisk";
+ 			arch = "arm";
+ 			os = "linux";
--- a/target/linux/layerscape/patches-4.4/3007-armv8-aarch32-Run-32-bit-Linux-in-AArch32-execution-.patch
+++ b/target/linux/layerscape/patches-4.4/3007-armv8-aarch32-Run-32-bit-Linux-in-AArch32-execution-.patch
@ -0,0 +1,79 @@
+From 3a827762e11670ca815bd4ee305f5faf5f02acb9 Mon Sep 17 00:00:00 2001
+From: Alison Wang <b18965@freescale.com>
+Date: Tue, 17 May 2016 17:23:51 +0800
+Subject: [PATCH 07/70] armv8: aarch32: Run 32-bit Linux in AArch32 execution
+ state
+
+This patch adds AArch32 execution state support for LS1043A. Verified
+32-bit Linux kernel can run on LS1043ARDB board.
+
+Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com>
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+---
+ arch/arm/mach-imx/Kconfig        |   10 ++++++++++
+ arch/arm/mach-imx/Makefile       |    4 +++-
+ arch/arm/mach-imx/mach-ls1043a.c |   21 +++++++++++++++++++++
+ 3 files changed, 34 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm/mach-imx/mach-ls1043a.c
+
+--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
+@@ -612,6 +612,16 @@ endchoice
+ 
+ endif
+ 
+config ARCH_LAYERSCAPE
+	bool "Freescale Layerscape SoC support"
+	select ARM_GIC
+	select HAVE_ARM_ARCH_TIMER
+	select PCI_LAYERSCAPE if PCI
+	select LS1_MSI if PCI_MSI
+
+	help
+	  This enables support for Freescale Layerscape SoC family.
+
+ source "arch/arm/mach-imx/devices/Kconfig"
+ 
+ endif
+--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
+@@ -75,7 +75,7 @@ obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.
+ obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
+ obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
+ obj-$(CONFIG_HAVE_IMX_SRC) += src.o
+-ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),)
+ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A)$(CONFIG_ARCH_LAYERSCAPE),)
+ AFLAGS_headsmp.o :=-Wa,-march=armv7-a
+ obj-$(CONFIG_SMP) += headsmp.o platsmp.o
+ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
+@@ -101,4 +101,6 @@ obj-$(CONFIG_SOC_VF610) += mach-vf610.o
+ 
+ obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
+ 
+obj-$(CONFIG_ARCH_LAYERSCAPE) += mach-ls1043a.o
+
+ obj-y += devices/
+--- /dev/null
+++ b/arch/arm/mach-imx/mach-ls1043a.c
+@@ -0,0 +1,21 @@
+/*
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <asm/mach/arch.h>
+
+#include "common.h"
+
+static const char * const ls1043a_dt_compat[] __initconst = {
+	"fsl,ls1043a",
+	NULL,
+};
+
+DT_MACHINE_START(LS1043A, "Freescale LS1043A")
+	.dt_compat	= ls1043a_dt_compat,
+MACHINE_END
--- a/target/linux/layerscape/patches-4.4/3008-armv8-aarch32-Add-SMP-support-for-32-bit-Linux.patch
+++ b/target/linux/layerscape/patches-4.4/3008-armv8-aarch32-Add-SMP-support-for-32-bit-Linux.patch
@ -0,0 +1,103 @@
+From 5d06e90bd0e3bdd104b7b25173e05617f02dc44d Mon Sep 17 00:00:00 2001
+From: Alison Wang <b18965@freescale.com>
+Date: Fri, 13 May 2016 15:09:47 +0800
+Subject: [PATCH 08/70] armv8: aarch32: Add SMP support for 32-bit Linux
+
+The patch adds SMP support for running 32-bit Linux kernel. Spin-table
+method is used for SMP support.
+
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
+---
+ arch/arm/mach-imx/common.h       |    1 +
+ arch/arm/mach-imx/mach-ls1043a.c |    1 +
+ arch/arm/mach-imx/platsmp.c      |   49 ++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 51 insertions(+)
+
+--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
+@@ -155,5 +155,6 @@ static inline void imx_init_l2cache(void
+ 
+ extern struct smp_operations imx_smp_ops;
+ extern struct smp_operations ls1021a_smp_ops;
+extern const struct smp_operations layerscape_smp_ops;
+ 
+ #endif
+--- a/arch/arm/mach-imx/mach-ls1043a.c
+++ b/arch/arm/mach-imx/mach-ls1043a.c
+@@ -17,5 +17,6 @@ static const char * const ls1043a_dt_com
+ };
+ 
+ DT_MACHINE_START(LS1043A, "Freescale LS1043A")
+	.smp		= smp_ops(layerscape_smp_ops),
+ 	.dt_compat	= ls1043a_dt_compat,
+ MACHINE_END
+--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
+@@ -14,6 +14,7 @@
+ #include <linux/of_address.h>
+ #include <linux/of.h>
+ #include <linux/smp.h>
+#include <linux/types.h>
+ 
+ #include <asm/cacheflush.h>
+ #include <asm/page.h>
+@@ -26,6 +27,8 @@
+ u32 g_diag_reg;
+ static void __iomem *scu_base;
+ 
+static u64 cpu_release_addr[NR_CPUS];
+
+ static struct map_desc scu_io_desc __initdata = {
+ 	/* .virtual and .pfn are run-time assigned */
+ 	.length		= SZ_4K,
+@@ -127,3 +130,49 @@ struct smp_operations  ls1021a_smp_ops _
+ 	.smp_prepare_cpus	= ls1021a_smp_prepare_cpus,
+ 	.smp_boot_secondary	= ls1021a_boot_secondary,
+ };
+
+static int layerscape_smp_boot_secondary(unsigned int cpu,
+					 struct task_struct *idle)
+{
+	u32 secondary_startup_phys;
+	__le32 __iomem *release_addr;
+
+	secondary_startup_phys = virt_to_phys(secondary_startup);
+
+	release_addr = ioremap_cache((u32)cpu_release_addr[cpu],
+				     sizeof(u64));
+	if (!release_addr)
+		return -ENOMEM;
+
+	writel_relaxed(secondary_startup_phys, release_addr);
+	writel_relaxed(0, release_addr + 1);
+	__cpuc_flush_dcache_area((__force void *)release_addr,
+				 sizeof(u64));
+
+	sev();
+
+	iounmap(release_addr);
+
+	return 0;
+}
+
+static void layerscape_smp_init_cpus(void)
+{
+	struct device_node *dnt = NULL;
+	unsigned int cpu = 0;
+
+	while ((dnt = of_find_node_by_type(dnt, "cpu"))) {
+		if (of_property_read_u64(dnt, "cpu-release-addr",
+		    &cpu_release_addr[cpu])) {
+			pr_err("CPU %d: missing or invalid cpu-release-addr property\n",
+			cpu);
+		}
+
+		cpu++;
+	}
+}
+
+const struct smp_operations layerscape_smp_ops __initconst = {
+	.smp_init_cpus		= layerscape_smp_init_cpus,
+	.smp_boot_secondary	= layerscape_smp_boot_secondary,
+};
--- a/target/linux/layerscape/patches-4.4/3009-armv8-aarch32-Allow-RAM-to-be-mapped-for-LayerScape-.patch
+++ b/target/linux/layerscape/patches-4.4/3009-armv8-aarch32-Allow-RAM-to-be-mapped-for-LayerScape-.patch
@ -0,0 +1,31 @@
+From ef25bf644b7de83849a2f804c84bb54cd2f1255f Mon Sep 17 00:00:00 2001
+From: Alison Wang <b18965@freescale.com>
+Date: Mon, 11 Apr 2016 17:25:40 +0800
+Subject: [PATCH 09/70] armv8: aarch32: Allow RAM to be mapped for LayerScape
+ SoC
+
+This patch is based on Kernel v4.1.8. As in v4.1.8, memremap() is not
+introduced and the WARN() check is not relaxed to allow MT_MEMORY_RW
+mappings of pfn_valid() pages, this patch is needed as a workaround for
+spin-table address which locates in RAM to be mapped.
+
+For the latest kernel in upstream, this patch is not needed anymore.
+
+Signed-off-by: Alison Wang <alison.wang@nxp.com>
+---
+ arch/arm/mm/ioremap.c |    2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
+@@ -298,8 +298,10 @@ static void __iomem * __arm_ioremap_pfn_
+ 	/*
+ 	 * Don't allow RAM to be mapped - this causes problems with ARMv6+
+ 	 */
+#ifndef CONFIG_ARCH_LAYERSCAPE
+ 	if (WARN_ON(pfn_valid(pfn)))
+ 		return NULL;
+#endif
+ 
+ 	area = get_vm_area_caller(size, VM_IOREMAP, caller);
+  	if (!area)
--- a/target/linux/layerscape/patches-4.4/3010-arm-add-pgprot_cached-and-pgprot_cached_ns-support.patch
+++ b/target/linux/layerscape/patches-4.4/3010-arm-add-pgprot_cached-and-pgprot_cached_ns-support.patch
@ -0,0 +1,26 @@
+From 31a5b5189bdd33bb87f88320964a47c0da983af2 Mon Sep 17 00:00:00 2001
+From: Jianhua Xie <jianhua.xie@nxp.com>
+Date: Fri, 29 Jan 2016 16:40:46 +0800
+Subject: [PATCH 10/70] arm: add pgprot_cached and pgprot_cached_ns support
+
+Signed-off-by: Jianhua Xie <jianhua.xie@nxp.com>
+---
+ arch/arm/include/asm/pgtable.h |    7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
+@@ -116,6 +116,13 @@ extern pgprot_t		pgprot_s2_device;
+ #define pgprot_noncached(prot) \
+ 	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
+ 
+#define pgprot_cached(prot) \
+	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED)
+
+#define pgprot_cached_ns(prot) \
+	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED | \
+			L_PTE_MT_DEV_NONSHARED)
+
+ #define pgprot_writecombine(prot) \
+ 	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
+ 
--- a/target/linux/layerscape/patches-4.4/3011-arm-add-new-non-shareable-ioremap.patch
+++ b/target/linux/layerscape/patches-4.4/3011-arm-add-new-non-shareable-ioremap.patch
@ -0,0 +1,99 @@
+From 707627a28924320a7a36bdb8b02c05651c0c384d Mon Sep 17 00:00:00 2001
+From: Pan Jiafei <Jiafei.Pan@nxp.com>
+Date: Fri, 8 Jul 2016 11:16:13 +0800
+Subject: [PATCH 11/70] arm: add new non-shareable ioremap
+
+commit 17d7448eef0fa57a0899e6a864d875e7a9082561
+[modify ioremap_cache_ns according to Linux v4.4.7]
+
+Signed-off-by: Pan Jiafei <Jiafei.Pan@nxp.com>
+Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
+---
+ arch/arm/include/asm/io.h       |    4 ++++
+ arch/arm/include/asm/mach/map.h |    4 ++--
+ arch/arm/mm/ioremap.c           |    7 +++++++
+ arch/arm/mm/mmu.c               |    9 +++++++++
+ 4 files changed, 22 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
+@@ -129,6 +129,7 @@ static inline u32 __raw_readl(const vola
+ #define MT_DEVICE_NONSHARED	1
+ #define MT_DEVICE_CACHED	2
+ #define MT_DEVICE_WC		3
+#define MT_MEMORY_RW_NS		4
+ /*
+  * types 4 onwards can be found in asm/mach/map.h and are undefined
+  * for ioremap
+@@ -399,6 +400,9 @@ void __iomem *ioremap_wc(resource_size_t
+ #define ioremap_wc ioremap_wc
+ #define ioremap_wt ioremap_wc
+ 
+void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size);
+#define ioremap_cache_ns ioremap_cache_ns
+
+ void iounmap(volatile void __iomem *iomem_cookie);
+ #define iounmap iounmap
+ 
+--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
+@@ -21,9 +21,9 @@ struct map_desc {
+ 	unsigned int type;
+ };
+ 
+-/* types 0-3 are defined in asm/io.h */
+/* types 0-4 are defined in asm/io.h */
+ enum {
+-	MT_UNCACHED = 4,
+	MT_UNCACHED = 5,
+ 	MT_CACHECLEAN,
+ 	MT_MINICLEAN,
+ 	MT_LOW_VECTORS,
+--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
+@@ -394,6 +394,13 @@ void __iomem *ioremap_wc(resource_size_t
+ }
+ EXPORT_SYMBOL(ioremap_wc);
+ 
+void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size)
+{
+	return arch_ioremap_caller(res_cookie, size, MT_MEMORY_RW_NS,
+				   __builtin_return_address(0));
+}
+EXPORT_SYMBOL(ioremap_cache_ns);
+
+ /*
+  * Remap an arbitrary physical address space into the kernel virtual
+  * address space as memory. Needed when the kernel wants to execute
+--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
+@@ -313,6 +313,13 @@ static struct mem_type mem_types[] = {
+ 		.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
+ 		.domain    = DOMAIN_KERNEL,
+ 	},
+	[MT_MEMORY_RW_NS] = {
+		.prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
+			     L_PTE_XN,
+		.prot_l1   = PMD_TYPE_TABLE,
+		.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_XN,
+		.domain    = DOMAIN_KERNEL,
+	},
+ 	[MT_ROM] = {
+ 		.prot_sect = PMD_TYPE_SECT,
+ 		.domain    = DOMAIN_KERNEL,
+@@ -644,6 +651,7 @@ static void __init build_mem_type_table(
+ 	}
+ 	kern_pgprot |= PTE_EXT_AF;
+ 	vecs_pgprot |= PTE_EXT_AF;
+	mem_types[MT_MEMORY_RW_NS].prot_pte |= PTE_EXT_AF | cp->pte;
+ 
+ 	/*
+ 	 * Set PXN for user mappings
+@@ -672,6 +680,7 @@ static void __init build_mem_type_table(
+ 	mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
+ 	mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
+ 	mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
+	mem_types[MT_MEMORY_RW_NS].prot_sect |= ecc_mask | cp->pmd;
+ 	mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
+ 	mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
+ 	mem_types[MT_ROM].prot_sect |= cp->pmd;
--- a/target/linux/layerscape/patches-4.4/3012-dts-ls1043a-add-fman-bman-qman-ethernet-nodes.patch
+++ b/target/linux/layerscape/patches-4.4/3012-dts-ls1043a-add-fman-bman-qman-ethernet-nodes.patch
@ -0,0 +1,747 @@
+From 10b0a19d62d932a6eb01ceb8749190aaf0ff063e Mon Sep 17 00:00:00 2001
+From: Shaohui Xie <Shaohui.Xie@freescale.com>
+Date: Mon, 11 Jul 2016 10:47:20 +0800
+Subject: [PATCH 12/70] dts: ls1043a: add fman/bman/qman/ethernet nodes
+
+commit ecb0901ba0a6558a05054d21ad9e70999a6f7ca1
+[context adjustment]
+
+Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
+Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi     |  461 ++++++++++++++++++++
+ .../boot/dts/freescale/qoriq-bman1-portals.dtsi    |  104 +++++
+ .../boot/dts/freescale/qoriq-qman1-portals.dtsi    |  136 ++++++
+ 3 files changed, 701 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+@@ -50,6 +50,16 @@
+ 	#address-cells = <2>;
+ 	#size-cells = <2>;
+ 
+	aliases {
+		ethernet0 = &fm1mac1;
+		ethernet1 = &fm1mac2;
+		ethernet2 = &fm1mac3;
+		ethernet3 = &fm1mac4;
+		ethernet4 = &fm1mac5;
+		ethernet5 = &fm1mac6;
+		ethernet6 = &fm1mac9;
+	};
+
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -174,6 +184,323 @@
+ 			bus-width = <4>;
+ 		};
+ 
+		qman: qman@1880000 {
+			compatible = "fsl,qman";
+			reg = <0x00 0x1880000 0x0 0x10000>;
+			interrupts = <0 45 0x4>;
+		};
+
+		bman: bman@1890000 {
+			compatible = "fsl,bman";
+			reg = <0x00 0x1890000 0x0 0x10000>;
+			interrupts = <0 45 0x4>;
+		};
+
+		fman0: fman@1a00000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			cell-index = <0>;
+			compatible = "fsl,fman", "simple-bus";
+			ranges = <0x0 0x00 0x1a00000 0x100000>;
+			reg = <0x00 0x1a00000 0x0 0x100000>;
+			clock-frequency = <0>;
+			interrupts = <0 44 0x4>,
+				     <0 45 0x4>;
+
+			cc {
+				compatible = "fsl,fman-cc";
+			};
+
+			muram@0 {
+				compatible = "fsl,fman-muram";
+				reg = <0x0 0x60000>;
+			};
+
+			bmi@80000 {
+				compatible = "fsl,fman-bmi";
+				reg = <0x80000 0x400>;
+			};
+
+			qmi@80400 {
+				compatible = "fsl,fman-qmi";
+				reg = <0x80400 0x400>;
+			};
+
+			fman0_oh1: port@82000 {
+				cell-index = <0>;
+				compatible = "fsl,fman-port-oh";
+				reg = <0x82000 0x1000>;
+			};
+
+			fman0_oh2: port@83000 {
+				cell-index = <1>;
+				compatible = "fsl,fman-port-oh";
+				reg = <0x83000 0x1000>;
+			};
+
+			fman0_oh3: port@84000 {
+				cell-index = <2>;
+				compatible = "fsl,fman-port-oh";
+				reg = <0x84000 0x1000>;
+			};
+
+			fman0_oh4: port@85000 {
+				cell-index = <3>;
+				compatible = "fsl,fman-port-oh";
+				reg = <0x85000 0x1000>;
+			};
+
+			fman0_oh5: port@86000 {
+				cell-index = <4>;
+				compatible = "fsl,fman-port-oh";
+				reg = <0x86000 0x1000>;
+			};
+
+			fman0_oh6: port@87000 {
+				cell-index = <5>;
+				compatible = "fsl,fman-port-oh";
+				reg = <0x87000 0x1000>;
+			};
+
+			policer@c0000 {
+				compatible = "fsl,fman-policer";
+				reg = <0xc0000 0x1000>;
+			};
+
+			keygen@c1000 {
+				compatible = "fsl,fman-keygen";
+				reg = <0xc1000 0x1000>;
+			};
+
+			dma@c2000 {
+				compatible = "fsl,fman-dma";
+				reg = <0xc2000 0x1000>;
+			};
+
+			fpm@c3000 {
+				compatible = "fsl,fman-fpm";
+				reg = <0xc3000 0x1000>;
+			};
+
+			parser@c7000 {
+				compatible = "fsl,fman-parser";
+				reg = <0xc7000 0x1000>;
+			};
+
+			vsps@dc000 {
+				compatible = "fsl,fman-vsps";
+				reg = <0xdc000 0x1000>;
+			};
+
+			mdio0: mdio@fc000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,fman-memac-mdio";
+				reg = <0xfc000 0x1000>;
+			};
+
+			xmdio0: mdio@fd000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,fman-memac-mdio";
+				reg = <0xfd000 0x1000>;
+			};
+
+			fman0_rx0: port@88000 {
+				cell-index = <0>;
+				compatible = "fsl,fman-port-1g-rx";
+				reg = <0x88000 0x1000>;
+			};
+
+			fman0_tx0: port@a8000 {
+				cell-index = <0>;
+				compatible = "fsl,fman-port-1g-tx";
+				reg = <0xa8000 0x1000>;
+			};
+
+			fm1mac1: ethernet@e0000 {
+				cell-index = <0>;
+				compatible = "fsl,fman-memac";
+				reg = <0xe0000 0x1000>;
+				fsl,port-handles = <&fman0_rx0 &fman0_tx0>;
+				ptimer-handle = <&ptp_timer0>;
+			};
+
+			mdio@e1000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,fman-memac-mdio";
+				reg = <0xe1000 0x1000>;
+			};
+
+			fman0_rx1: port@89000 {
+				cell-index = <1>;
+				compatible = "fsl,fman-port-1g-rx";
+				reg = <0x89000 0x1000>;
+			};
+
+			fman0_tx1: port@a9000 {
+				cell-index = <1>;
+				compatible = "fsl,fman-port-1g-tx";
+				reg = <0xa9000 0x1000>;
+			};
+
+			fm1mac2: ethernet@e2000 {
+				cell-index = <1>;
+				compatible = "fsl,fman-memac";
+				reg = <0xe2000 0x1000>;
+				fsl,port-handles = <&fman0_rx1 &fman0_tx1>;
+				ptimer-handle = <&ptp_timer0>;
+			};
+
+			mdio@e3000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,fman-memac-mdio";
+				reg = <0xe3000 0x1000>;
+			};
+
+			fman0_rx2: port@8a000 {
+				cell-index = <2>;
+				compatible = "fsl,fman-port-1g-rx";
+				reg = <0x8a000 0x1000>;
+			};
+
+			fman0_tx2: port@aa000 {
+				cell-index = <2>;
+				compatible = "fsl,fman-port-1g-tx";
+				reg = <0xaa000 0x1000>;
+			};
+
+			fm1mac3: ethernet@e4000 {
+				cell-index = <2>;
+				compatible = "fsl,fman-memac";
+				reg = <0xe4000 0x1000>;
+				fsl,port-handles = <&fman0_rx2 &fman0_tx2>;
+				ptimer-handle = <&ptp_timer0>;
+			};
+
+			mdio@e5000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,fman-memac-mdio";
+				reg = <0xe5000 0x1000>;
+			};
+
+			fman0_rx3: port@8b000 {
+				cell-index = <3>;
+				compatible = "fsl,fman-port-1g-rx";
+				reg = <0x8b000 0x1000>;
+			};
+
+			fman0_tx3: port@ab000 {
+				cell-index = <3>;
+				compatible = "fsl,fman-port-1g-tx";
+				reg = <0xab000 0x1000>;
+			};
+
+			fm1mac4: ethernet@e6000 {
+				cell-index = <3>;
+				compatible = "fsl,fman-memac";
+				reg = <0xe6000 0x1000>;
+				fsl,port-handles = <&fman0_rx3 &fman0_tx3>;
+				ptimer-handle = <&ptp_timer0>;
+			};
+
+			mdio@e7000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,fman-memac-mdio";
+				reg = <0xe7000 0x1000>;
+			};
+
+			fman0_rx4: port@8c000 {
+				cell-index = <4>;
+				compatible = "fsl,fman-port-1g-rx";
+				reg = <0x8c000 0x1000>;
+			};
+
+			fman0_tx4: port@ac000 {
+				cell-index = <4>;
+				compatible = "fsl,fman-port-1g-tx";
+				reg = <0xac000 0x1000>;
+			};
+
+			fm1mac5: ethernet@e8000 {
+				cell-index = <4>;
+				compatible = "fsl,fman-memac";
+				reg = <0xe8000 0x1000>;
+				fsl,port-handles = <&fman0_rx4 &fman0_tx4>;
+				ptimer-handle = <&ptp_timer0>;
+			};
+
+			mdio@e9000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,fman-memac-mdio";
+				reg = <0xe9000 0x1000>;
+			};
+
+			fman0_rx5: port@8d000 {
+				cell-index = <5>;
+				compatible = "fsl,fman-port-1g-rx";
+				reg = <0x8d000 0x1000>;
+			};
+
+			fman0_tx5: port@ad000 {
+				cell-index = <5>;
+				compatible = "fsl,fman-port-1g-tx";
+				reg = <0xad000 0x1000>;
+			};
+
+			fm1mac6: ethernet@ea000 {
+				cell-index = <5>;
+				compatible = "fsl,fman-memac";
+				reg = <0xea000 0x1000>;
+				fsl,port-handles = <&fman0_rx5 &fman0_tx5>;
+				ptimer-handle = <&ptp_timer0>;
+			};
+
+			mdio@eb000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,fman-memac-mdio";
+				reg = <0xeb000 0x1000>;
+			};
+
+			fman0_10g_rx0: port@90000 {
+				cell-index = <0>;
+				compatible = "fsl,fman-port-10g-rx";
+				reg = <0x90000 0x1000>;
+			};
+
+			fman0_10g_tx0: port@b0000 {
+				cell-index = <0>;
+				compatible = "fsl,fman-port-10g-tx";
+				reg = <0xb0000 0x1000>;
+				fsl,qman-channel-id = <0x800>;
+			};
+
+			fm1mac9: ethernet@f0000 {
+				cell-index = <0>;
+				compatible = "fsl,fman-memac";
+				reg = <0xf0000 0x1000>;
+				fsl,port-handles = <&fman0_10g_rx0 &fman0_10g_tx0>;
+			};
+
+			mdio@f1000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,fman-memac-mdio";
+				reg = <0xf1000 0x1000>;
+			};
+
+			ptp_timer0: rtc@fe000 {
+				compatible = "fsl,fman-rtc";
+				reg = <0xfe000 0x1000>;
+			};
+		};
+
+ 		dspi0: dspi@2100000 {
+ 			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
+ 			#address-cells = <1>;
+@@ -522,4 +849,138 @@
+ 		};
+ 	};
+ 
+	fsl,dpaa {
+		compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa";
+		ethernet@0 {
+			compatible = "fsl,dpa-ethernet";
+			fsl,fman-mac = <&fm1mac1>;
+		};
+		ethernet@1 {
+			compatible = "fsl,dpa-ethernet";
+			fsl,fman-mac = <&fm1mac2>;
+		};
+		ethernet@2 {
+			compatible = "fsl,dpa-ethernet";
+			fsl,fman-mac = <&fm1mac3>;
+		};
+		ethernet@3 {
+			compatible = "fsl,dpa-ethernet";
+			fsl,fman-mac = <&fm1mac4>;
+		};
+		ethernet@4 {
+			compatible = "fsl,dpa-ethernet";
+			fsl,fman-mac = <&fm1mac5>;
+		};
+		ethernet@5 {
+			compatible = "fsl,dpa-ethernet";
+			fsl,fman-mac = <&fm1mac6>;
+		};
+		ethernet@8 {
+			compatible = "fsl,dpa-ethernet";
+			fsl,fman-mac = <&fm1mac9>;
+		};
+	};
+
+	qportals: qman-portals@500000000 {
+		   ranges = <0x0 0x5 0x00000000 0x8000000>;
+        };
+	bportals: bman-portals@508000000 {
+		   ranges = <0x0 0x5 0x08000000 0x8000000>;
+        };
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		bman_fbpr: bman-fbpr {
+			size = <0 0x1000000>;
+			alignment = <0 0x1000000>;
+		};
+		qman_fqd: qman-fqd {
+			size = <0 0x400000>;
+			alignment = <0 0x400000>;
+		};
+		qman_pfdr: qman-pfdr {
+			size = <0 0x2000000>;
+			alignment = <0 0x2000000>;
+		};
+	};
+};
+
+&fman0 {
+	/* offline - 1 */
+	port@82000 {
+		fsl,qman-channel-id = <0x809>;
+	};
+
+	/* tx - 10g - 2 */
+	port@a8000 {
+		fsl,qman-channel-id = <0x802>;
+	};
+	/* tx - 10g - 3 */
+	port@a9000 {
+		fsl,qman-channel-id = <0x803>;
+	};
+	/* tx - 1g - 2 */
+	port@aa000 {
+		fsl,qman-channel-id = <0x804>;
+	};
+	/* tx - 1g - 3 */
+	port@ab000 {
+		fsl,qman-channel-id = <0x805>;
+	};
+	/* tx - 1g - 4 */
+	port@ac000 {
+		fsl,qman-channel-id = <0x806>;
+	};
+	/* tx - 1g - 5 */
+	port@ad000 {
+		fsl,qman-channel-id = <0x807>;
+	};
+	/* tx - 10g - 0 */
+	port@b0000 {
+		fsl,qman-channel-id = <0x800>;
+	};
+	/* tx - 10g - 1 */
+	port@b1000 {
+		fsl,qman-channel-id = <0x801>;
+	};
+	/* offline - 2 */
+	port@83000 {
+		fsl,qman-channel-id = <0x80a>;
+	};
+	/* offline - 3 */
+	port@84000 {
+		fsl,qman-channel-id = <0x80b>;
+	};
+	/* offline - 4 */
+	port@85000 {
+		fsl,qman-channel-id = <0x80c>;
+	};
+	/* offline - 5 */
+	port@86000 {
+		fsl,qman-channel-id = <0x80d>;
+	};
+	/* offline - 6 */
+	port@87000 {
+		fsl,qman-channel-id = <0x80e>;
+	};
+};
+
+&bman_fbpr {
+	compatible = "fsl,bman-fbpr";
+	alloc-ranges = <0 0 0x10000 0>;
+ };
+
+&qman_fqd {
+	compatible = "fsl,qman-fqd";
+	alloc-ranges = <0 0 0x10000 0>;
+};
+
+&qman_pfdr {
+	compatible = "fsl,qman-pfdr";
+	alloc-ranges = <0 0 0x10000 0>;
+};
+
+/include/ "qoriq-qman1-portals.dtsi"
+/include/ "qoriq-bman1-portals.dtsi"
+--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
+@@ -0,0 +1,104 @@
+/*
+ * QorIQ BMan Portal device tree stub for 10 portals
+ *
+ * Copyright 2011-2016 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *	 notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *	 notice, this list of conditions and the following disclaimer in the
+ *	 documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *	 names of its contributors may be used to endorse or promote products
+ *	 derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&bportals {
+	  #address-cells = <1>;
+	  #size-cells = <1>;
+	  compatible = "simple-bus";
+	  bportal0: bman-portal@0 {
+		cell-index = <0>;
+		compatible = "fsl,bman-portal";
+		reg = <0x0 0x4000 0x4000000 0x4000>;
+		interrupts = <0 173 0x4>;
+	};
+	bportal1: bman-portal@10000 {
+		cell-index = <1>;
+		compatible = "fsl,bman-portal";
+		reg = <0x10000 0x4000 0x4010000 0x4000>;
+		interrupts = <0 175 0x4>;
+	};
+	bportal2: bman-portal@20000 {
+		cell-index = <2>;
+		compatible = "fsl,bman-portal";
+		reg = <0x20000 0x4000 0x4020000 0x4000>;
+		interrupts = <0 177 0x4>;
+	};
+	bportal3: bman-portal@30000 {
+		cell-index = <3>;
+		compatible = "fsl,bman-portal";
+		reg = <0x30000 0x4000 0x4030000 0x4000>;
+		interrupts = <0 179 0x4>;
+	};
+	bportal4: bman-portal@40000 {
+		cell-index = <4>;
+		compatible = "fsl,bman-portal";
+		reg = <0x40000 0x4000 0x4040000 0x4000>;
+		interrupts = <0 181 0x4>;
+		};
+	bportal5: bman-portal@50000 {
+		cell-index = <5>;
+		compatible = "fsl,bman-portal";
+		reg = <0x50000 0x4000 0x4050000 0x4000>;
+		interrupts = <0 183 0x4>;
+	};
+	bportal6: bman-portal@60000 {
+		cell-index = <6>;
+		compatible = "fsl,bman-portal";
+		reg = <0x60000 0x4000 0x4060000 0x4000>;
+		interrupts = <0 185 0x4>;
+	};
+	bportal7: bman-portal@70000 {
+		cell-index = <7>;
+		compatible = "fsl,bman-portal";
+		reg = <0x70000 0x4000 0x4070000 0x4000>;
+		interrupts = <0 187 0x4>;
+	};
+	bportal8: bman-portal@80000 {
+		cell-index = <8>;
+		compatible = "fsl,bman-portal";
+		reg = <0x80000 0x4000 0x4080000 0x4000>;
+		interrupts = <0 189 0x4>;
+	};
+/*	bportal9: bman-portal@90000 {
+		cell-index = <9>;
+		compatible = "fsl,bman-portal";
+		reg = <0x90000 0x4000 0x4090000 0x4000>;
+		interrupts = <0 191 0x4>;
+	}; */
+	 bman-bpids@0 {
+                compatible = "fsl,bpid-range";
+                fsl,bpid-range = <32 32>;
+        };
+
+};
+--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
+@@ -0,0 +1,136 @@
+/*
+ * QorIQ QMan Portal device tree stub for 10 portals & 15 pool channels
+ *
+ * Copyright 2011-2016 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *	 notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *	 notice, this list of conditions and the following disclaimer in the
+ *	 documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *	 names of its contributors may be used to endorse or promote products
+ *	 derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+&qportals {
+
+	  #address-cells = <1>;
+	  #size-cells = <1>;
+	  compatible = "simple-bus";
+	  qportal0: qman-portal@0 {
+		cell-index = <0>;
+		compatible = "fsl,qman-portal";
+		reg = <0x0 0x4000 0x4000000 0x4000>;
+		interrupts = <0 172 0x4>;
+		fsl,qman-channel-id = <0x0>;
+	};
+
+	qportal1: qman-portal@10000 {
+		  cell-index = <1>;
+		  compatible = "fsl,qman-portal";
+		  reg = <0x10000 0x4000 0x4010000 0x4000>;
+		  interrupts = <0 174 0x4>;
+		  fsl,qman-channel-id = <1>;
+	};
+
+	qportal2: qman-portal@20000 {
+		  cell-index = <2>;
+		  compatible = "fsl,qman-portal";
+		  reg = <0x20000 0x4000 0x4020000 0x4000>;
+		  interrupts = <0 176 0x4>;
+		  fsl,qman-channel-id = <2>;
+	};
+
+	qportal3: qman-portal@30000 {
+		  cell-index = <3>;
+		  compatible = "fsl,qman-portal";
+		  reg = <0x30000 0x4000 0x4030000 0x4000>;
+		  interrupts = <0 178 0x4>;
+		  fsl,qman-channel-id = <3>;
+	};
+
+	qportal4: qman-portal@40000 {
+		  cell-index = <4>;
+		  compatible = "fsl,qman-portal";
+		  reg = <0x40000 0x4000 0x4040000 0x4000>;
+		  interrupts = <0 180 0x4>;
+		  fsl,qman-channel-id = <4>;
+	};
+
+	qportal5: qman-portal@50000 {
+		  cell-index = <5>;
+		  compatible = "fsl,qman-portal";
+		  reg = <0x50000 0x4000 0x4050000 0x4000>;
+		  interrupts = <0 182 0x4>;
+		  fsl,qman-channel-id = <5>;
+	};
+
+	qportal6: qman-portal@60000 {
+		  cell-index = <6>;
+		  compatible = "fsl,qman-portal";
+		  reg = <0x60000 0x4000 0x4060000 0x4000>;
+		  interrupts = <0 184 0x4>;
+		  fsl,qman-channel-id = <6>;
+	};
+
+	qportal7: qman-portal@70000 {
+		  cell-index = <7>;
+		  compatible = "fsl,qman-portal";
+		  reg = <0x70000 0x4000 0x4070000 0x4000>;
+		  interrupts = <0 186 0x4>;
+		  fsl,qman-channel-id = <7>;
+	};
+
+	qportal8: qman-portal@80000 {
+		cell-index = <8>;
+		compatible = "fsl,qman-portal";
+		reg = <0x80000 0x4000 0x4080000 0x4000>;
+		interrupts = <0 188 0x4>;
+		fsl,qman-channel-id = <8>;
+	};
+
+/*	qportal9: qman-portal@90000 {
+		cell-index = <9>;
+		compatible = "fsl,qman-portal";
+		reg = <0x90000 0x4000 0x4090000 0x4000>;
+		interrupts = <0 190 0x4>;
+		fsl,qman-channel-id = <9>;
+	}; */
+
+	qman-fqids@0 {
+                compatible = "fsl,fqid-range";
+                fsl,fqid-range = <256 256>;
+        };
+        qman-fqids@1 {
+                compatible = "fsl,fqid-range";
+                fsl,fqid-range = <32768 32768>;
+        };
+        qman-pools@0 {
+                compatible = "fsl,pool-channel-range";
+                fsl,pool-channel-range = <0x401 0xf>;
+        };
+        qman-cgrids@0 {
+                compatible = "fsl,cgrid-range";
+                fsl,cgrid-range = <0 256>;
+        };
+
+};
+\ No newline at end of file
--- a/target/linux/layerscape/patches-4.4/3013-dts-ls1043ardb-add-mdio-phy-nodes.patch
+++ b/target/linux/layerscape/patches-4.4/3013-dts-ls1043ardb-add-mdio-phy-nodes.patch
@ -0,0 +1,81 @@
+From e2b301610e6201df40deb62942b18c772365eb1c Mon Sep 17 00:00:00 2001
+From: Shaohui Xie <Shaohui.Xie@freescale.com>
+Date: Thu, 21 Jan 2016 11:29:22 +0800
+Subject: [PATCH 13/70] dts: ls1043ardb: add mdio & phy nodes
+
+Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts |   65 +++++++++++++++++++++
+ 1 file changed, 65 insertions(+)
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+@@ -115,3 +115,68 @@
+ &duart1 {
+ 	status = "okay";
+ };
+
+&fman0 {
+	ethernet@e0000 {
+		phy-handle = <&qsgmii_phy1>;
+		phy-connection-type = "qsgmii";
+	};
+
+	ethernet@e2000 {
+		phy-handle = <&qsgmii_phy2>;
+		phy-connection-type = "qsgmii";
+	};
+
+	ethernet@e4000 {
+		phy-handle = <&rgmii_phy1>;
+		phy-connection-type = "rgmii";
+	};
+
+	ethernet@e6000 {
+		phy-handle = <&rgmii_phy2>;
+		phy-connection-type = "rgmii";
+	};
+
+	ethernet@e8000 {
+		phy-handle = <&qsgmii_phy3>;
+		phy-connection-type = "qsgmii";
+	};
+
+	ethernet@ea000 {
+		phy-handle = <&qsgmii_phy4>;
+		phy-connection-type = "qsgmii";
+	};
+
+	ethernet@f0000 { /* 10GEC1 */
+		phy-handle = <&aqr105_phy>;
+		phy-connection-type = "xgmii";
+	};
+
+	mdio@fc000 {
+		rgmii_phy1: ethernet-phy@1 {
+			reg = <0x1>;
+		};
+		rgmii_phy2: ethernet-phy@2 {
+			reg = <0x2>;
+		};
+		qsgmii_phy1: ethernet-phy@3 {
+			reg = <0x4>;
+		};
+		qsgmii_phy2: ethernet-phy@4 {
+			reg = <0x5>;
+		};
+		qsgmii_phy3: ethernet-phy@5 {
+			reg = <0x6>;
+		};
+		qsgmii_phy4: ethernet-phy@6 {
+			reg = <0x7>;
+		};
+	};
+
+	mdio@fd000 {
+		aqr105_phy: ethernet-phy@c {
+			compatible = "ethernet-phy-ieee802.3-c45";
+			reg = <0x1>;
+		};
+	};
+};
--- a/target/linux/layerscape/patches-4.4/3022-dt-move-guts-devicetree-doc-out-of-powerpc-directory.patch
+++ b/target/linux/layerscape/patches-4.4/3022-dt-move-guts-devicetree-doc-out-of-powerpc-directory.patch
@ -0,0 +1,108 @@
+From 0e9d79db770196e94869650d7c4d13ea23937138 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Mon, 25 Jan 2016 14:27:27 +0800
+Subject: [PATCH 22/70] dt: move guts devicetree doc out of powerpc directory
+
+Move guts devicetree doc to Documentation/devicetree/bindings/soc/fsl/
+since it's used by not only PowerPC but also ARM. And add a specification
+for 'little-endian' property.
+
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ .../devicetree/bindings/powerpc/fsl/guts.txt       |   41 ------------------
+ Documentation/devicetree/bindings/soc/fsl/guts.txt |   44 ++++++++++++++++++++
+ 2 files changed, 44 insertions(+), 41 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/powerpc/fsl/guts.txt
+ create mode 100644 Documentation/devicetree/bindings/soc/fsl/guts.txt
+
+--- a/Documentation/devicetree/bindings/powerpc/fsl/guts.txt
+++ /dev/null
+@@ -1,41 +0,0 @@
+-* Global Utilities Block
+-
+-The global utilities block controls power management, I/O device
+-enabling, power-on-reset configuration monitoring, general-purpose
+-I/O signal configuration, alternate function selection for multiplexed
+-signals, and clock control.
+-
+-Required properties:
+-
+- - compatible : Should define the compatible device type for
+-   global-utilities.
+-   Possible compatibles:
+-	"fsl,qoriq-device-config-1.0"
+-	"fsl,qoriq-device-config-2.0"
+-	"fsl,<chip>-device-config"
+-	"fsl,<chip>-guts"
+- - reg : Offset and length of the register set for the device.
+-
+-Recommended properties:
+-
+- - fsl,has-rstcr : Indicates that the global utilities register set
+-   contains a functioning "reset control register" (i.e. the board
+-   is wired to reset upon setting the HRESET_REQ bit in this register).
+-
+- - fsl,liodn-bits : Indicates the number of defined bits in the LIODN
+-   registers, for those SOCs that have a PAMU device.
+-
+-Examples:
+-	global-utilities@e0000 {	/* global utilities block */
+-		compatible = "fsl,mpc8548-guts";
+-		reg = <e0000 1000>;
+-		fsl,has-rstcr;
+-	};
+-
+-	guts: global-utilities@e0000 {
+-		compatible = "fsl,qoriq-device-config-1.0";
+-		reg = <0xe0000 0xe00>;
+-		fsl,has-rstcr;
+-		#sleep-cells = <1>;
+-		fsl,liodn-bits = <12>;
+-	};
+--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/guts.txt
+@@ -0,0 +1,44 @@
+* Global Utilities Block
+
+The global utilities block controls power management, I/O device
+enabling, power-on-reset configuration monitoring, general-purpose
+I/O signal configuration, alternate function selection for multiplexed
+signals, and clock control.
+
+Required properties:
+
+ - compatible : Should define the compatible device type for
+   global-utilities.
+   Possible compatibles:
+	"fsl,qoriq-device-config-1.0"
+	"fsl,qoriq-device-config-2.0"
+	"fsl,<chip>-device-config"
+	"fsl,<chip>-guts"
+ - reg : Offset and length of the register set for the device.
+
+Recommended properties:
+
+ - fsl,has-rstcr : Indicates that the global utilities register set
+   contains a functioning "reset control register" (i.e. the board
+   is wired to reset upon setting the HRESET_REQ bit in this register).
+
+ - fsl,liodn-bits : Indicates the number of defined bits in the LIODN
+   registers, for those SOCs that have a PAMU device.
+
+ - little-endian : Indicates that the global utilities block is little
+   endian. The default is big endian.
+
+Examples:
+	global-utilities@e0000 {	/* global utilities block */
+		compatible = "fsl,mpc8548-guts";
+		reg = <e0000 1000>;
+		fsl,has-rstcr;
+	};
+
+	guts: global-utilities@e0000 {
+		compatible = "fsl,qoriq-device-config-1.0";
+		reg = <0xe0000 0xe00>;
+		fsl,has-rstcr;
+		#sleep-cells = <1>;
+		fsl,liodn-bits = <12>;
+	};
--- a/target/linux/layerscape/patches-4.4/3023-powerpc-fsl-move-mpc85xx.h-to-include-linux-fsl.patch
+++ b/target/linux/layerscape/patches-4.4/3023-powerpc-fsl-move-mpc85xx.h-to-include-linux-fsl.patch
@ -0,0 +1,283 @@
+From 2d8816af7c19882f62c4a25edb9fcc9040312f96 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Tue, 12 Apr 2016 14:21:19 +0800
+Subject: [PATCH 23/70] powerpc/fsl: move mpc85xx.h to include/linux/fsl
+
+commit 2a76fbe35c14717b4f4a145e0ab83517b1f4ab4a
+[context adjustment]
+[doesn't apply arch/powerpc/kernel/cpu_setup_fsl_booke.S]
+[doesn't apply arch/powerpc/sysdev/mpic_timer.c]
+
+Move mpc85xx.h to include/linux/fsl and rename it to svr.h as
+a common header file. It has been used for mpc85xx and it will
+be used for ARM-based SoC as well.
+
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
+---
+ arch/powerpc/include/asm/mpc85xx.h       |   95 ------------------------------
+ drivers/clk/clk-qoriq.c                  |    2 +-
+ drivers/i2c/busses/i2c-mpc.c             |    2 +-
+ drivers/iommu/fsl_pamu.c                 |    2 +-
+ drivers/net/ethernet/freescale/gianfar.c |    2 +-
+ include/linux/fsl/svr.h                  |   95 ++++++++++++++++++++++++++++++
+ 6 files changed, 99 insertions(+), 99 deletions(-)
+ delete mode 100644 arch/powerpc/include/asm/mpc85xx.h
+ create mode 100644 include/linux/fsl/svr.h
+
+--- a/arch/powerpc/include/asm/mpc85xx.h
+++ /dev/null
+@@ -1,95 +0,0 @@
+-/*
+- * MPC85xx cpu type detection
+- *
+- * Copyright 2011-2012 Freescale Semiconductor, Inc.
+- *
+- * This is free software; you can redistribute it and/or modify
+- * it under the terms of the GNU General Public License as published by
+- * the Free Software Foundation; either version 2 of the License, or
+- * (at your option) any later version.
+- */
+-
+-#ifndef __ASM_PPC_MPC85XX_H
+-#define __ASM_PPC_MPC85XX_H
+-
+-#define SVR_REV(svr)	((svr) & 0xFF)		/* SOC design resision */
+-#define SVR_MAJ(svr)	(((svr) >>  4) & 0xF)	/* Major revision field*/
+-#define SVR_MIN(svr)	(((svr) >>  0) & 0xF)	/* Minor revision field*/
+-
+-/* Some parts define SVR[0:23] as the SOC version */
+-#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF)	/* SOC Version fields */
+-
+-#define SVR_8533	0x803400
+-#define SVR_8535	0x803701
+-#define SVR_8536	0x803700
+-#define SVR_8540	0x803000
+-#define SVR_8541	0x807200
+-#define SVR_8543	0x803200
+-#define SVR_8544	0x803401
+-#define SVR_8545	0x803102
+-#define SVR_8547	0x803101
+-#define SVR_8548	0x803100
+-#define SVR_8555	0x807100
+-#define SVR_8560	0x807000
+-#define SVR_8567	0x807501
+-#define SVR_8568	0x807500
+-#define SVR_8569	0x808000
+-#define SVR_8572	0x80E000
+-#define SVR_P1010	0x80F100
+-#define SVR_P1011	0x80E500
+-#define SVR_P1012	0x80E501
+-#define SVR_P1013	0x80E700
+-#define SVR_P1014	0x80F101
+-#define SVR_P1017	0x80F700
+-#define SVR_P1020	0x80E400
+-#define SVR_P1021	0x80E401
+-#define SVR_P1022	0x80E600
+-#define SVR_P1023	0x80F600
+-#define SVR_P1024	0x80E402
+-#define SVR_P1025	0x80E403
+-#define SVR_P2010	0x80E300
+-#define SVR_P2020	0x80E200
+-#define SVR_P2040	0x821000
+-#define SVR_P2041	0x821001
+-#define SVR_P3041	0x821103
+-#define SVR_P4040	0x820100
+-#define SVR_P4080	0x820000
+-#define SVR_P5010	0x822100
+-#define SVR_P5020	0x822000
+-#define SVR_P5021	0X820500
+-#define SVR_P5040	0x820400
+-#define SVR_T4240	0x824000
+-#define SVR_T4120	0x824001
+-#define SVR_T4160	0x824100
+-#define SVR_T4080	0x824102
+-#define SVR_C291	0x850000
+-#define SVR_C292	0x850020
+-#define SVR_C293	0x850030
+-#define SVR_B4860	0X868000
+-#define SVR_G4860	0x868001
+-#define SVR_G4060	0x868003
+-#define SVR_B4440	0x868100
+-#define SVR_G4440	0x868101
+-#define SVR_B4420	0x868102
+-#define SVR_B4220	0x868103
+-#define SVR_T1040	0x852000
+-#define SVR_T1041	0x852001
+-#define SVR_T1042	0x852002
+-#define SVR_T1020	0x852100
+-#define SVR_T1021	0x852101
+-#define SVR_T1022	0x852102
+-#define SVR_T2080	0x853000
+-#define SVR_T2081	0x853100
+-
+-#define SVR_8610	0x80A000
+-#define SVR_8641	0x809000
+-#define SVR_8641D	0x809001
+-
+-#define SVR_9130	0x860001
+-#define SVR_9131	0x860000
+-#define SVR_9132	0x861000
+-#define SVR_9232	0x861400
+-
+-#define SVR_Unknown	0xFFFFFF
+-
+-#endif
+--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
+@@ -13,6 +13,7 @@
+ #include <linux/clk.h>
+ #include <linux/clk-provider.h>
+ #include <linux/fsl/guts.h>
+#include <linux/fsl/svr.h>
+ #include <linux/io.h>
+ #include <linux/kernel.h>
+ #include <linux/module.h>
+@@ -1148,7 +1149,6 @@ bad_args:
+ }
+ 
+ #ifdef CONFIG_PPC
+-#include <asm/mpc85xx.h>
+ 
+ static const u32 a4510_svrs[] __initconst = {
+ 	(SVR_P2040 << 8) | 0x10,	/* P2040 1.0 */
+--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
+@@ -27,9 +27,9 @@
+ #include <linux/i2c.h>
+ #include <linux/interrupt.h>
+ #include <linux/delay.h>
+#include <linux/fsl/svr.h>
+ 
+ #include <asm/mpc52xx.h>
+-#include <asm/mpc85xx.h>
+ #include <sysdev/fsl_soc.h>
+ 
+ #define DRV_NAME "mpc-i2c"
+--- a/drivers/iommu/fsl_pamu.c
+++ b/drivers/iommu/fsl_pamu.c
+@@ -21,10 +21,10 @@
+ #include "fsl_pamu.h"
+ 
+ #include <linux/fsl/guts.h>
+#include <linux/fsl/svr.h>
+ #include <linux/interrupt.h>
+ #include <linux/genalloc.h>
+ 
+-#include <asm/mpc85xx.h>
+ 
+ /* define indexes for each operation mapping scenario */
+ #define OMI_QMAN        0x00
+--- a/drivers/net/ethernet/freescale/gianfar.c
+++ b/drivers/net/ethernet/freescale/gianfar.c
+@@ -86,11 +86,11 @@
+ #include <linux/udp.h>
+ #include <linux/in.h>
+ #include <linux/net_tstamp.h>
+#include <linux/fsl/svr.h>
+ 
+ #include <asm/io.h>
+ #ifdef CONFIG_PPC
+ #include <asm/reg.h>
+-#include <asm/mpc85xx.h>
+ #endif
+ #include <asm/irq.h>
+ #include <asm/uaccess.h>
+--- /dev/null
+++ b/include/linux/fsl/svr.h
+@@ -0,0 +1,95 @@
+/*
+ * MPC85xx cpu type detection
+ *
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef FSL_SVR_H
+#define FSL_SVR_H
+
+#define SVR_REV(svr)	((svr) & 0xFF)		/* SOC design resision */
+#define SVR_MAJ(svr)	(((svr) >>  4) & 0xF)	/* Major revision field*/
+#define SVR_MIN(svr)	(((svr) >>  0) & 0xF)	/* Minor revision field*/
+
+/* Some parts define SVR[0:23] as the SOC version */
+#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF)	/* SOC Version fields */
+
+#define SVR_8533	0x803400
+#define SVR_8535	0x803701
+#define SVR_8536	0x803700
+#define SVR_8540	0x803000
+#define SVR_8541	0x807200
+#define SVR_8543	0x803200
+#define SVR_8544	0x803401
+#define SVR_8545	0x803102
+#define SVR_8547	0x803101
+#define SVR_8548	0x803100
+#define SVR_8555	0x807100
+#define SVR_8560	0x807000
+#define SVR_8567	0x807501
+#define SVR_8568	0x807500
+#define SVR_8569	0x808000
+#define SVR_8572	0x80E000
+#define SVR_P1010	0x80F100
+#define SVR_P1011	0x80E500
+#define SVR_P1012	0x80E501
+#define SVR_P1013	0x80E700
+#define SVR_P1014	0x80F101
+#define SVR_P1017	0x80F700
+#define SVR_P1020	0x80E400
+#define SVR_P1021	0x80E401
+#define SVR_P1022	0x80E600
+#define SVR_P1023	0x80F600
+#define SVR_P1024	0x80E402
+#define SVR_P1025	0x80E403
+#define SVR_P2010	0x80E300
+#define SVR_P2020	0x80E200
+#define SVR_P2040	0x821000
+#define SVR_P2041	0x821001
+#define SVR_P3041	0x821103
+#define SVR_P4040	0x820100
+#define SVR_P4080	0x820000
+#define SVR_P5010	0x822100
+#define SVR_P5020	0x822000
+#define SVR_P5021	0X820500
+#define SVR_P5040	0x820400
+#define SVR_T4240	0x824000
+#define SVR_T4120	0x824001
+#define SVR_T4160	0x824100
+#define SVR_T4080	0x824102
+#define SVR_C291	0x850000
+#define SVR_C292	0x850020
+#define SVR_C293	0x850030
+#define SVR_B4860	0X868000
+#define SVR_G4860	0x868001
+#define SVR_G4060	0x868003
+#define SVR_B4440	0x868100
+#define SVR_G4440	0x868101
+#define SVR_B4420	0x868102
+#define SVR_B4220	0x868103
+#define SVR_T1040	0x852000
+#define SVR_T1041	0x852001
+#define SVR_T1042	0x852002
+#define SVR_T1020	0x852100
+#define SVR_T1021	0x852101
+#define SVR_T1022	0x852102
+#define SVR_T2080	0x853000
+#define SVR_T2081	0x853100
+
+#define SVR_8610	0x80A000
+#define SVR_8641	0x809000
+#define SVR_8641D	0x809001
+
+#define SVR_9130	0x860001
+#define SVR_9131	0x860000
+#define SVR_9132	0x861000
+#define SVR_9232	0x861400
+
+#define SVR_Unknown	0xFFFFFF
+
+#endif
--- a/target/linux/layerscape/patches-4.4/3025-arm64-dts-align-to-the-new-clocking-model.patch
+++ b/target/linux/layerscape/patches-4.4/3025-arm64-dts-align-to-the-new-clocking-model.patch
@ -0,0 +1,25 @@
+From caddf479c2deacf3d681a84db56ff164d8a5c9f7 Mon Sep 17 00:00:00 2001
+From: Madalin Bucur <madalin.bucur@freescale.com>
+Date: Wed, 23 Mar 2016 21:25:30 +0200
+Subject: [PATCH 25/70] arm64/dts: align to the new clocking model
+
+Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |    6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+@@ -203,9 +203,9 @@
+ 			compatible = "fsl,fman", "simple-bus";
+ 			ranges = <0x0 0x00 0x1a00000 0x100000>;
+ 			reg = <0x00 0x1a00000 0x0 0x100000>;
+-			clock-frequency = <0>;
+-			interrupts = <0 44 0x4>,
+-				     <0 45 0x4>;
+			interrupts = <0 44 0x4>, <0 45 0x4>;
+			clocks = <&clockgen 3 0>;
+			clock-names = "fmanclk";
+ 
+ 			cc {
+ 				compatible = "fsl,fman-cc";
--- a/target/linux/layerscape/patches-4.4/3028-dts-ls1043-update-dts-for-ls1043.patch
+++ b/target/linux/layerscape/patches-4.4/3028-dts-ls1043-update-dts-for-ls1043.patch
@ -0,0 +1,523 @@
+From ad6176d72132d020317db1496be1485056ac88d7 Mon Sep 17 00:00:00 2001
+From: Liu Gang <Gang.Liu@nxp.com>
+Date: Mon, 6 Jun 2016 15:46:00 +0800
+Subject: [PATCH 28/70] dts/ls1043: update dts for ls1043
+
+Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts  |   59 +++++
+ arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi     |  264 +++++++++++++++++++-
+ .../boot/dts/freescale/qoriq-qman1-portals.dtsi    |   10 +-
+ 3 files changed, 321 insertions(+), 12 deletions(-)
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+@@ -50,6 +50,10 @@
+ / {
+ 	model = "LS1043A RDB Board";
+ 	compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
+
+	aliases {
+		crypto = &crypto;
+	};
+ };
+ 
+ &i2c0 {
+@@ -108,6 +112,35 @@
+ 		};
+ };
+ 
+&dspi0 {
+	bus-num = <0>;
+	status = "okay";
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "n25q128a13", "jedec,spi-nor";  /* 16MB */
+		reg = <0>;
+		spi-max-frequency = <1000000>; /* input clock */
+	};
+
+	slic@2 {
+		compatible = "maxim,ds26522";
+		reg = <2>;
+		spi-max-frequency = <2000000>;
+		fsl,spi-cs-sck-delay = <100>;
+		fsl,spi-sck-cs-delay = <50>;
+	};
+
+	slic@3 {
+		compatible = "maxim,ds26522";
+		reg = <3>;
+		spi-max-frequency = <2000000>;
+		fsl,spi-cs-sck-delay = <100>;
+		fsl,spi-sck-cs-delay = <50>;
+	};
+};
+
+ &duart0 {
+ 	status = "okay";
+ };
+@@ -176,7 +209,33 @@
+ 	mdio@fd000 {
+ 		aqr105_phy: ethernet-phy@c {
+ 			compatible = "ethernet-phy-ieee802.3-c45";
+			interrupts = <0 132 4>;
+ 			reg = <0x1>;
+ 		};
+ 	};
+ };
+
+&uqe {
+	ucc_hdlc: ucc@2000 {
+		compatible = "fsl,ucc_hdlc";
+		rx-clock-name = "clk8";
+		tx-clock-name = "clk9";
+		fsl,rx-sync-clock = "rsync_pin";
+		fsl,tx-sync-clock = "tsync_pin";
+		fsl,tx-timeslot = <0xfffffffe>;
+		fsl,rx-timeslot = <0xfffffffe>;
+		fsl,tdm-framer-type = "e1";
+		fsl,tdm-mode = "normal";
+		fsl,tdm-id = <0>;
+		fsl,siram-entry-id = <0>;
+		fsl,tdm-interface;
+	};
+
+	ucc_serial: ucc@2200 {
+		device_type = "serial";
+		compatible = "ucc_uart";
+		port-number = <0>;
+		rx-clock-name = "brg2";
+		tx-clock-name = "brg2";
+	};
+};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+@@ -44,6 +44,8 @@
+  *     OTHER DEALINGS IN THE SOFTWARE.
+  */
+ 
+#include <dt-bindings/thermal/thermal.h>
+
+ / {
+ 	compatible = "fsl,ls1043a";
+ 	interrupt-parent = <&gic>;
+@@ -75,6 +77,7 @@
+ 			compatible = "arm,cortex-a53";
+ 			reg = <0x0>;
+ 			clocks = <&clockgen 1 0>;
+			#cooling-cells = <2>;
+ 		};
+ 
+ 		cpu1: cpu@1 {
+@@ -118,6 +121,8 @@
+ 			     <1 14 0x1>, /* Physical Non-Secure PPI */
+ 			     <1 11 0x1>, /* Virtual PPI */
+ 			     <1 10 0x1>; /* Hypervisor PPI */
+		arm,reread-timer;
+		fsl,erratum-a008585;
+ 	};
+ 
+ 	pmu {
+@@ -162,11 +167,64 @@
+ 			big-endian;
+ 		};
+ 
+		crypto: crypto@1700000 {
+			compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+				     "fsl,sec-v4.0";
+			fsl,sec-era = <3>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x00 0x1700000 0x100000>;
+			reg = <0x00 0x1700000 0x0 0x100000>;
+			interrupts = <0 75 0x4>;
+
+			sec_jr0: jr@10000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x10000 0x10000>;
+				interrupts = <0 71 0x4>;
+			};
+
+			sec_jr1: jr@20000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x20000 0x10000>;
+				interrupts = <0 72 0x4>;
+			};
+
+			sec_jr2: jr@30000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				interrupts = <0 73 0x4>;
+			};
+
+			sec_jr3: jr@40000 {
+				compatible = "fsl,sec-v5.4-job-ring",
+					     "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg	   = <0x40000 0x10000>;
+				interrupts = <0 74 0x4>;
+			};
+		};
+
+ 		dcfg: dcfg@1ee0000 {
+ 			compatible = "fsl,ls1043a-dcfg", "syscon";
+ 			reg = <0x0 0x1ee0000 0x0 0x10000>;
+ 		};
+ 
+		reset: reset@1EE00B0 {
+			compatible = "fsl,ls-reset";
+			reg = <0x0 0x1EE00B0 0x0 0x4>;
+			big-endian;
+		};
+
+		rcpm: rcpm@1ee2000 {
+			compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1";
+			reg = <0x0 0x1ee2000 0x0 0x10000>;
+		};
+
+ 		ifc: ifc@1530000 {
+ 			compatible = "fsl,ifc", "simple-bus";
+ 			reg = <0x0 0x1530000 0x0 0x10000>;
+@@ -501,6 +559,82 @@
+ 			};
+ 		};
+ 
+		tmu: tmu@1f00000 {
+			compatible = "fsl,qoriq-tmu", "fsl,ls1043a-tmu";
+			reg = <0x0 0x1f00000 0x0 0x10000>;
+			interrupts = <0 33 0x4>;
+			fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
+			fsl,tmu-calibration = <0x00000000 0x00000026
+					       0x00000001 0x0000002d
+					       0x00000002 0x00000032
+					       0x00000003 0x00000039
+					       0x00000004 0x0000003f
+					       0x00000005 0x00000046
+					       0x00000006 0x0000004d
+					       0x00000007 0x00000054
+					       0x00000008 0x0000005a
+					       0x00000009 0x00000061
+					       0x0000000a 0x0000006a
+					       0x0000000b 0x00000071
+
+					       0x00010000 0x00000025
+					       0x00010001 0x0000002c
+					       0x00010002 0x00000035
+					       0x00010003 0x0000003d
+					       0x00010004 0x00000045
+					       0x00010005 0x0000004e
+					       0x00010006 0x00000057
+					       0x00010007 0x00000061
+					       0x00010008 0x0000006b
+					       0x00010009 0x00000076
+
+					       0x00020000 0x00000029
+					       0x00020001 0x00000033
+					       0x00020002 0x0000003d
+					       0x00020003 0x00000049
+					       0x00020004 0x00000056
+					       0x00020005 0x00000061
+					       0x00020006 0x0000006d
+
+					       0x00030000 0x00000021
+					       0x00030001 0x0000002a
+					       0x00030002 0x0000003c
+					       0x00030003 0x0000004e>;
+			big-endian;
+			#thermal-sensor-cells = <1>;
+		};
+
+		thermal-zones {
+			cpu_thermal: cpu-thermal {
+				polling-delay-passive = <1000>;
+				polling-delay = <5000>;
+
+				thermal-sensors = <&tmu 3>;
+
+				trips {
+					cpu_alert: cpu-alert {
+						temperature = <85000>;
+						hysteresis = <2000>;
+						type = "passive";
+					};
+					cpu_crit: cpu-crit {
+						temperature = <95000>;
+						hysteresis = <2000>;
+						type = "critical";
+					};
+				};
+
+				cooling-maps {
+					map0 {
+						trip = <&cpu_alert>;
+						cooling-device =
+							<&cpu0 THERMAL_NO_LIMIT
+							THERMAL_NO_LIMIT>;
+					};
+				};
+			};
+		};
+
+ 		dspi0: dspi@2100000 {
+ 			compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
+ 			#address-cells = <1>;
+@@ -527,6 +661,20 @@
+ 			status = "disabled";
+ 		};
+ 
+		qspi: quadspi@1550000 {
+			compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x1550000 0x0 0x10000>,
+				<0x0 0x40000000 0x0 0x4000000>;
+			reg-names = "QuadSPI", "QuadSPI-memory";
+			interrupts = <0 99 0x4>;
+			clock-names = "qspi_en", "qspi";
+			clocks = <&clockgen 4 0>, <&clockgen 4 0>;
+			big-endian;
+			status = "disabled";
+		};
+
+ 		i2c0: i2c@2180000 {
+ 			compatible = "fsl,vf610-i2c";
+ 			#address-cells = <1>;
+@@ -602,8 +750,8 @@
+ 			clocks = <&clockgen 4 0>;
+ 		};
+ 
+-		gpio1: gpio@2300000 {
+-			compatible = "fsl,ls1043a-gpio";
+		gpio0: gpio@2300000 {
+			compatible = "fsl,qoriq-gpio";
+ 			reg = <0x0 0x2300000 0x0 0x10000>;
+ 			interrupts = <0 66 0x4>;
+ 			gpio-controller;
+@@ -612,8 +760,8 @@
+ 			#interrupt-cells = <2>;
+ 		};
+ 
+-		gpio2: gpio@2310000 {
+-			compatible = "fsl,ls1043a-gpio";
+		gpio1: gpio@2310000 {
+			compatible = "fsl,qoriq-gpio";
+ 			reg = <0x0 0x2310000 0x0 0x10000>;
+ 			interrupts = <0 67 0x4>;
+ 			gpio-controller;
+@@ -622,8 +770,8 @@
+ 			#interrupt-cells = <2>;
+ 		};
+ 
+-		gpio3: gpio@2320000 {
+-			compatible = "fsl,ls1043a-gpio";
+		gpio2: gpio@2320000 {
+			compatible = "fsl,qoriq-gpio";
+ 			reg = <0x0 0x2320000 0x0 0x10000>;
+ 			interrupts = <0 68 0x4>;
+ 			gpio-controller;
+@@ -632,8 +780,8 @@
+ 			#interrupt-cells = <2>;
+ 		};
+ 
+-		gpio4: gpio@2330000 {
+-			compatible = "fsl,ls1043a-gpio";
+		gpio3: gpio@2330000 {
+			compatible = "fsl,qoriq-gpio";
+ 			reg = <0x0 0x2330000 0x0 0x10000>;
+ 			interrupts = <0 134 0x4>;
+ 			gpio-controller;
+@@ -642,6 +790,70 @@
+ 			#interrupt-cells = <2>;
+ 		};
+ 
+		uqe: uqe@2400000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			device_type = "qe";
+			compatible = "fsl,qe", "simple-bus";
+			ranges = <0x0 0x0 0x2400000 0x40000>;
+			reg = <0x0 0x2400000 0x0 0x480>;
+			brg-frequency = <100000000>;
+			bus-frequency = <200000000>;
+
+			fsl,qe-num-riscs = <1>;
+			fsl,qe-num-snums = <28>;
+
+			qeic: qeic@80 {
+				compatible = "fsl,qe-ic";
+				reg = <0x80 0x80>;
+				#address-cells = <0>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupts = <0 77 0x04 0 77 0x04>;
+			};
+
+			si1: si@700 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,qe-si";
+				reg = <0x700 0x80>;
+			};
+
+			siram1: siram@1000 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "fsl,qe-siram";
+				reg = <0x1000 0x800>;
+			};
+
+			ucc@2000 {
+				cell-index = <1>;
+				reg = <0x2000 0x200>;
+				interrupts = <32>;
+				interrupt-parent = <&qeic>;
+			};
+
+			ucc@2200 {
+				cell-index = <3>;
+				reg = <0x2200 0x200>;
+				interrupts = <34>;
+				interrupt-parent = <&qeic>;
+			};
+
+			muram@10000 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "fsl,qe-muram", "fsl,cpm-muram";
+				ranges = <0x0 0x10000 0x6000>;
+
+				data-only@0 {
+					compatible = "fsl,qe-muram-data",
+					"fsl,cpm-muram-data";
+					reg = <0x0 0x6000>;
+				};
+			};
+		};
+
+ 		lpuart0: serial@2950000 {
+ 			compatible = "fsl,ls1021a-lpuart";
+ 			reg = <0x0 0x2950000 0x0 0x1000>;
+@@ -696,6 +908,15 @@
+ 			status = "disabled";
+ 		};
+ 
+		ftm0: ftm0@29d0000 {
+			compatible = "fsl,ftm-alarm";
+			reg = <0x0 0x29d0000 0x0 0x10000>;
+			interrupts = <0 86 0x4>;
+			big-endian;
+			rcpm-wakeup = <&rcpm 0x0 0x20000000>;
+			status = "okay";
+		};
+
+ 		wdog0: wdog@2ad0000 {
+ 			compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
+ 			reg = <0x0 0x2ad0000 0x0 0x10000>;
+@@ -726,6 +947,8 @@
+ 			reg = <0x0 0x2f00000 0x0 0x10000>;
+ 			interrupts = <0 60 0x4>;
+ 			dr_mode = "host";
+			configure-gfladj;
+			snps,dis_rxdet_inp3_quirk;
+ 		};
+ 
+ 		usb1: usb3@3000000 {
+@@ -733,6 +956,8 @@
+ 			reg = <0x0 0x3000000 0x0 0x10000>;
+ 			interrupts = <0 61 0x4>;
+ 			dr_mode = "host";
+			configure-gfladj;
+			snps,dis_rxdet_inp3_quirk;
+ 		};
+ 
+ 		usb2: usb3@3100000 {
+@@ -740,6 +965,8 @@
+ 			reg = <0x0 0x3100000 0x0 0x10000>;
+ 			interrupts = <0 63 0x4>;
+ 			dr_mode = "host";
+			configure-gfladj;
+			snps,dis_rxdet_inp3_quirk;
+ 		};
+ 
+ 		sata: sata@3200000 {
+@@ -749,6 +976,20 @@
+ 			clocks = <&clockgen 4 0>;
+ 		};
+ 
+		qdma: qdma@8380000 {
+			compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
+			reg = <0x0 0x838f000 0x0 0x11000 /* Controller regs */
+			       0x0 0x83a0000 0x0 0x40000>; /* Block regs */
+			interrupts = <0 152 0x4>,
+				     <0 39 0x4>;
+			interrupt-names = "qdma-error", "qdma-queue";
+			channels = <8>;
+			queues = <2>;
+			status-sizes = <64>;
+			queue-sizes = <64 64>;
+			big-endian;
+		};
+
+ 		msi1: msi-controller1@1571000 {
+ 			compatible = "fsl,1s1043a-msi";
+ 			reg = <0x0 0x1571000 0x0 0x4>,
+@@ -787,6 +1028,7 @@
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 			device_type = "pci";
+			dma-coherent;
+ 			num-lanes = <4>;
+ 			bus-range = <0x0 0xff>;
+ 			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
+@@ -811,6 +1053,7 @@
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 			device_type = "pci";
+			dma-coherent;
+ 			num-lanes = <2>;
+ 			bus-range = <0x0 0xff>;
+ 			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
+@@ -835,6 +1078,7 @@
+ 			#address-cells = <3>;
+ 			#size-cells = <2>;
+ 			device_type = "pci";
+			dma-coherent;
+ 			num-lanes = <2>;
+ 			bus-range = <0x0 0xff>;
+ 			ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
+@@ -897,8 +1141,8 @@
+ 			alignment = <0 0x1000000>;
+ 		};
+ 		qman_fqd: qman-fqd {
+-			size = <0 0x400000>;
+-			alignment = <0 0x400000>;
+			size = <0 0x800000>;
+			alignment = <0 0x800000>;
+ 		};
+ 		qman_pfdr: qman-pfdr {
+ 			size = <0 0x2000000>;
+--- a/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
+++ b/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
+@@ -132,5 +132,11 @@
+                 compatible = "fsl,cgrid-range";
+                 fsl,cgrid-range = <0 256>;
+         };
+-
+-};
+\ No newline at end of file
+	qman-ceetm@0 {
+		compatible = "fsl,qman-ceetm";
+		fsl,ceetm-lfqid-range = <0xf00000 0x1000>;
+		fsl,ceetm-sp-range = <0 12>;
+		fsl,ceetm-lni-range = <0 8>;
+		fsl,ceetm-channel-range = <0 32>;
+	};
+};
--- a/target/linux/layerscape/patches-4.4/3032-arm64-Add-pdev_archdata-for-dmamask.patch
+++ b/target/linux/layerscape/patches-4.4/3032-arm64-Add-pdev_archdata-for-dmamask.patch
@ -0,0 +1,51 @@
+From f7e48669bb75f3b52e9f3ce1a5d885c49b7c4712 Mon Sep 17 00:00:00 2001
+From: Cristian Sovaiala <cristian.sovaiala@freescale.com>
+Date: Thu, 4 Jun 2015 18:27:20 +0300
+Subject: [PATCH 32/70] arm64: Add pdev_archdata for dmamask
+
+The dma_mask for a device structure is a pointer. This pointer
+needs to be set up before the dma mask can actually be set. Most
+frameworks in the kernel take care of setting this up properly but
+platform devices that don't follow a regular bus structure may not
+ever have this set. As a result, checks such as dma_capable will
+always return false on a raw platform device and dma_set_mask will
+always return -EIO. Fix this by adding a dma_mask in the
+platform_device archdata and setting it to be the dma_mask. Devices
+used in other frameworks can change this as needed.
+
+Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
+---
+ arch/arm64/include/asm/device.h |    1 +
+ arch/arm64/kernel/setup.c       |    7 +++++++
+ 2 files changed, 8 insertions(+)
+
+--- a/arch/arm64/include/asm/device.h
+++ b/arch/arm64/include/asm/device.h
+@@ -25,6 +25,7 @@ struct dev_archdata {
+ };
+ 
+ struct pdev_archdata {
+	u64 dma_mask;
+ };
+ 
+ #endif
+--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
+@@ -44,6 +44,7 @@
+ #include <linux/of_platform.h>
+ #include <linux/efi.h>
+ #include <linux/psci.h>
+#include <linux/dma-mapping.h>
+ 
+ #include <asm/acpi.h>
+ #include <asm/fixmap.h>
+@@ -381,3 +382,9 @@ static int __init topology_init(void)
+ 	return 0;
+ }
+ subsys_initcall(topology_init);
+
+void arch_setup_pdev_archdata(struct platform_device *pdev)
+{
+	pdev->archdata.dma_mask = DMA_BIT_MASK(32);
+	pdev->dev.dma_mask = &pdev->archdata.dma_mask;
+}
--- a/target/linux/layerscape/patches-4.4/3033-arm64-add-ioremap-for-normal-cacheable-non-shareable.patch
+++ b/target/linux/layerscape/patches-4.4/3033-arm64-add-ioremap-for-normal-cacheable-non-shareable.patch
@ -0,0 +1,42 @@
+From 6ef5cf7b8f6b86fb3856f3449f1ad431118e5c9d Mon Sep 17 00:00:00 2001
+From: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Wed, 22 Apr 2015 13:07:25 -0400
+Subject: [PATCH 33/70] arm64: add ioremap for normal cacheable non-shareable
+ memory
+
+[context adjustment]
+
+Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+Change-Id: Iab7413f182a64bd6ad4707dd1d6254d04f51a3b1
+Reviewed-on: http://git.am.freescale.net:8181/35486
+Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
+Reviewed-by: Roy Pledge <roy.pledge@freescale.com>
+Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ arch/arm64/include/asm/io.h      |    2 ++
+ arch/arm64/include/asm/pgtable.h |    2 ++
+ 2 files changed, 4 insertions(+)
+
+--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
+@@ -171,6 +171,8 @@ extern void __iomem *ioremap_cache(phys_
+ #define ioremap_nocache(addr, size)	__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
+ #define ioremap_wc(addr, size)		__ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
+ #define ioremap_wt(addr, size)		__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
+#define ioremap_cache_ns(addr, size)	__ioremap((addr), (size), \
+						 __pgprot(PROT_NORMAL_NS))
+ #define iounmap				__iounmap
+ 
+ /*
+--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
+@@ -74,6 +74,8 @@ extern void __pgd_error(const char *file
+ #define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
+ #define PROT_NORMAL_WT		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
+ #define PROT_NORMAL		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
+#define PROT_NORMAL_NS		(PTE_TYPE_PAGE | PTE_AF | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | \
+				 PTE_ATTRINDX(MT_NORMAL))
+ 
+ #define PROT_SECT_DEVICE_nGnRE	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
+ #define PROT_SECT_NORMAL	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
--- a/target/linux/layerscape/patches-4.4/3034-arm64-add-support-to-remap-kernel-cacheable-memory-t.patch
+++ b/target/linux/layerscape/patches-4.4/3034-arm64-add-support-to-remap-kernel-cacheable-memory-t.patch
@ -0,0 +1,28 @@
+From 52bffb91d40a3090ecf9138fadca97f77c99afa4 Mon Sep 17 00:00:00 2001
+From: Haiying Wang <Haiying.Wang@freescale.com>
+Date: Wed, 22 Apr 2015 13:09:47 -0400
+Subject: [PATCH 34/70] arm64: add support to remap kernel cacheable memory to
+ userspace
+
+Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
+Change-Id: I50ee4798a2929932fa9ff7c9cdb42cd1a215f77a
+Reviewed-on: http://git.am.freescale.net:8181/35488
+Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
+Reviewed-by: Roy Pledge <roy.pledge@freescale.com>
+Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com>
+---
+ arch/arm64/include/asm/pgtable.h |    3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
+@@ -389,6 +389,9 @@ static inline int has_transparent_hugepa
+ 	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
+ #define pgprot_writecombine(prot) \
+ 	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
+#define pgprot_cached(prot) \
+	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL) | \
+			PTE_PXN | PTE_UXN)
+ #define pgprot_device(prot) \
+ 	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
+ #define __HAVE_PHYS_MEM_ACCESS_PROT
--- a/target/linux/layerscape/patches-4.4/3035-arm64-pgtable-add-support-to-map-cacheable-and-non-s.patch
+++ b/target/linux/layerscape/patches-4.4/3035-arm64-pgtable-add-support-to-map-cacheable-and-non-s.patch
@ -0,0 +1,22 @@
+From 1d6d5b6d2363cf5a0d175f086209fb208692ec00 Mon Sep 17 00:00:00 2001
+From: Haiying Wang <Haiying.wang@freescale.com>
+Date: Sat, 8 Aug 2015 07:25:02 -0400
+Subject: [PATCH 35/70] arm64/pgtable: add support to map cacheable and non
+ shareable memory
+
+Signed-off-by: Haiying Wang <Haiying.wang@freescale.com>
+---
+ arch/arm64/include/asm/pgtable.h |    2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
+@@ -392,6 +392,8 @@ static inline int has_transparent_hugepa
+ #define pgprot_cached(prot) \
+ 	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL) | \
+ 			PTE_PXN | PTE_UXN)
+#define pgprot_cached_ns(prot) \
+	__pgprot(pgprot_val(pgprot_cached(prot)) ^ PTE_SHARED)
+ #define pgprot_device(prot) \
+ 	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
+ #define __HAVE_PHYS_MEM_ACCESS_PROT
--- a/target/linux/layerscape/patches-4.4/3039-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch
+++ b/target/linux/layerscape/patches-4.4/3039-arch-arm-add-ARM-specific-fucntions-required-for-ehc.patch
@ -0,0 +1,79 @@
+From 03eea243622d85d59653ee076ce43ac0653dc51d Mon Sep 17 00:00:00 2001
+From: Zhao Qiang <B45475@freescale.com>
+Date: Fri, 10 Oct 2014 10:38:48 +0800
+Subject: [PATCH 39/70] arch: arm: add ARM specific fucntions required for
+ ehci fsl driver
+
+Add below functions for ARM platform which are used by ehci fsl driver:
+1. spin_event_timeout function
+2. set/clear bits functions
+
+Signed-off-by: Zhao Qiang <B45475@freescale.com>
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
+---
+ arch/arm/include/asm/delay.h |   16 ++++++++++++++++
+ arch/arm/include/asm/io.h    |   28 ++++++++++++++++++++++++++++
+ 2 files changed, 44 insertions(+)
+
+--- a/arch/arm/include/asm/delay.h
+++ b/arch/arm/include/asm/delay.h
+@@ -57,6 +57,22 @@ extern void __bad_udelay(void);
+ 			__const_udelay((n) * UDELAY_MULT)) :		\
+ 	  __udelay(n))
+ 
+#define spin_event_timeout(condition, timeout, delay)                          \
+({                                                                             \
+	typeof(condition) __ret;                                               \
+	int i = 0;							       \
+	while (!(__ret = (condition)) && (i++ < timeout)) {		       \
+		if (delay)                                                     \
+			udelay(delay);                                         \
+		else                                                           \
+			cpu_relax();					       \
+		udelay(1);						       \
+	}								       \
+	if (!__ret)                                                            \
+		__ret = (condition);                                           \
+	__ret;		                                                       \
+})
+
+ /* Loop-based definitions for assembly code. */
+ extern void __loop_delay(unsigned long loops);
+ extern void __loop_udelay(unsigned long usecs);
+--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
+@@ -221,6 +221,34 @@ extern int pci_ioremap_io(unsigned int o
+ #endif
+ #endif
+ 
+/* access ports */
+#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) |  (_v), (_addr))
+#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
+
+#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) |  (_v), (_addr))
+#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
+
+#define setbits8(_addr, _v) iowrite8(ioread8(_addr) |  (_v), (_addr))
+#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
+
+/* Clear and set bits in one shot.  These macros can be used to clear and
+ * set multiple bits in a register using a single read-modify-write.  These
+ * macros can also be used to set a multiple-bit bit pattern using a mask,
+ * by specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrsetbits_be32(addr, clear, set) \
+	iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
+#define clrsetbits_le32(addr, clear, set) \
+	iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr))
+#define clrsetbits_be16(addr, clear, set) \
+	iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
+#define clrsetbits_le16(addr, clear, set) \
+	iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr))
+#define clrsetbits_8(addr, clear, set) \
+	iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
+
+ /*
+  *  IO port access primitives
+  *  -------------------------
--- a/target/linux/layerscape/patches-4.4/3063-arm64-add-NO_IRQ-macro.patch
+++ b/target/linux/layerscape/patches-4.4/3063-arm64-add-NO_IRQ-macro.patch
@ -0,0 +1,27 @@
+From 9417a4b5978a7c38ae1dee217c3b22cda8e94731 Mon Sep 17 00:00:00 2001
+From: Mingkai Hu <Mingkai.Hu@freescale.com>
+Date: Thu, 19 Nov 2015 15:25:37 +0800
+Subject: [PATCH 63/70] arm64: add NO_IRQ macro
+
+Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
+---
+ arch/arm64/include/asm/irq.h |    8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/include/asm/irq.h
+++ b/arch/arm64/include/asm/irq.h
+@@ -3,6 +3,14 @@
+ 
+ #include <asm-generic/irq.h>
+ 
+/*
+ * Use this value to indicate lack of interrupt
+ * capability
+ */
+#ifndef NO_IRQ
+#define NO_IRQ	((unsigned int)(-1))
+#endif
+
+ struct pt_regs;
+ 
+ extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
--- a/target/linux/layerscape/patches-4.4/4043-driver-memory-Removal-of-deprecated-NO_IRQ.patch
+++ b/target/linux/layerscape/patches-4.4/4043-driver-memory-Removal-of-deprecated-NO_IRQ.patch
@ -0,0 +1,24 @@
+From ae1f7ae8bbacbdbf9df3977449f97d1432ff1957 Mon Sep 17 00:00:00 2001
+From: Raghav Dogra <raghav@freescale.com>
+Date: Wed, 16 Dec 2015 16:11:31 +0530
+Subject: [PATCH 43/70] driver/memory: Removal of deprecated NO_IRQ
+
+Replacing the NO_IRQ macro with 0. If there is no interrupt,
+returned value will be 0 regardless of what NO_IRQ is defined.
+
+Signed-off-by: Raghav Dogra <raghav@freescale.com>
+---
+ drivers/memory/fsl_ifc.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/memory/fsl_ifc.c
+++ b/drivers/memory/fsl_ifc.c
+@@ -260,7 +260,7 @@ static int fsl_ifc_ctrl_probe(struct pla
+ 
+ 	/* get the Controller level irq */
+ 	fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
+-	if (fsl_ifc_ctrl_dev->irq == NO_IRQ) {
+	if (fsl_ifc_ctrl_dev->irq == 0) {
+ 		dev_err(&dev->dev, "failed to get irq resource "
+ 							"for IFC\n");
+ 		ret = -ENODEV;
--- a/target/linux/layerscape/patches-4.4/4044-drivers-memory-Add-deep-sleep-support-for-IFC.patch
+++ b/target/linux/layerscape/patches-4.4/4044-drivers-memory-Add-deep-sleep-support-for-IFC.patch
@ -0,0 +1,233 @@
+From bb35d670afd2f3501de36c158e9842817ce013b8 Mon Sep 17 00:00:00 2001
+From: Raghav Dogra <raghav@freescale.com>
+Date: Fri, 15 Jan 2016 17:10:09 +0530
+Subject: [PATCH 44/70] drivers/memory: Add deep sleep support for IFC
+
+Add support of suspend, resume function to support deep sleep.
+Also make sure of SRAM initialization  during resume.
+
+Signed-off-by: Raghav Dogra <raghav@freescale.com>
+---
+ drivers/memory/fsl_ifc.c |  163 ++++++++++++++++++++++++++++++++++++++++++++++
+ include/linux/fsl_ifc.h  |    6 ++
+ 2 files changed, 169 insertions(+)
+
+--- a/drivers/memory/fsl_ifc.c
+++ b/drivers/memory/fsl_ifc.c
+@@ -24,6 +24,7 @@
+ #include <linux/compiler.h>
+ #include <linux/sched.h>
+ #include <linux/spinlock.h>
+#include <linux/delay.h>
+ #include <linux/types.h>
+ #include <linux/slab.h>
+ #include <linux/io.h>
+@@ -35,6 +36,8 @@
+ 
+ struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
+ EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
+#define FSL_IFC_V1_3_0	0x01030000
+#define IFC_TIMEOUT_MSECS	100000 /* 100ms */
+ 
+ /*
+  * convert_ifc_address - convert the base address
+@@ -309,6 +312,161 @@ err:
+ 	return ret;
+ }
+ 
+#ifdef CONFIG_PM_SLEEP
+/* save ifc registers */
+static int fsl_ifc_suspend(struct device *dev)
+{
+	struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
+	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+	__be32 nand_evter_intr_en, cm_evter_intr_en, nor_evter_intr_en,
+							 gpcm_evter_intr_en;
+
+	ctrl->saved_regs = kzalloc(sizeof(struct fsl_ifc_regs), GFP_KERNEL);
+	if (!ctrl->saved_regs)
+		return -ENOMEM;
+
+	cm_evter_intr_en = ifc_in32(&ifc->cm_evter_intr_en);
+	nand_evter_intr_en = ifc_in32(&ifc->ifc_nand.nand_evter_intr_en);
+	nor_evter_intr_en = ifc_in32(&ifc->ifc_nor.nor_evter_intr_en);
+	gpcm_evter_intr_en = ifc_in32(&ifc->ifc_gpcm.gpcm_evter_intr_en);
+
+/* IFC interrupts disabled */
+
+	ifc_out32(0x0, &ifc->cm_evter_intr_en);
+	ifc_out32(0x0, &ifc->ifc_nand.nand_evter_intr_en);
+	ifc_out32(0x0, &ifc->ifc_nor.nor_evter_intr_en);
+	ifc_out32(0x0, &ifc->ifc_gpcm.gpcm_evter_intr_en);
+
+	memcpy_fromio(ctrl->saved_regs, ifc, sizeof(struct fsl_ifc_regs));
+
+/* save the interrupt values */
+	ctrl->saved_regs->cm_evter_intr_en = cm_evter_intr_en;
+	ctrl->saved_regs->ifc_nand.nand_evter_intr_en = nand_evter_intr_en;
+	ctrl->saved_regs->ifc_nor.nor_evter_intr_en = nor_evter_intr_en;
+	ctrl->saved_regs->ifc_gpcm.gpcm_evter_intr_en = gpcm_evter_intr_en;
+
+	return 0;
+}
+
+/* restore ifc registers */
+static int fsl_ifc_resume(struct device *dev)
+{
+	struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
+	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+	struct fsl_ifc_regs *savd_regs = ctrl->saved_regs;
+	uint32_t ver = 0, ncfgr, status, ifc_bank, i;
+
+/*
+ * IFC interrupts disabled
+ */
+	ifc_out32(0x0, &ifc->cm_evter_intr_en);
+	ifc_out32(0x0, &ifc->ifc_nand.nand_evter_intr_en);
+	ifc_out32(0x0, &ifc->ifc_nor.nor_evter_intr_en);
+	ifc_out32(0x0, &ifc->ifc_gpcm.gpcm_evter_intr_en);
+
+
+	if (ctrl->saved_regs) {
+		for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) {
+			ifc_out32(savd_regs->cspr_cs[ifc_bank].cspr_ext,
+					&ifc->cspr_cs[ifc_bank].cspr_ext);
+			ifc_out32(savd_regs->cspr_cs[ifc_bank].cspr,
+					&ifc->cspr_cs[ifc_bank].cspr);
+			ifc_out32(savd_regs->amask_cs[ifc_bank].amask,
+					&ifc->amask_cs[ifc_bank].amask);
+			ifc_out32(savd_regs->csor_cs[ifc_bank].csor_ext,
+					&ifc->csor_cs[ifc_bank].csor_ext);
+			ifc_out32(savd_regs->csor_cs[ifc_bank].csor,
+					&ifc->csor_cs[ifc_bank].csor);
+			for (i = 0; i < 4; i++) {
+				ifc_out32(savd_regs->ftim_cs[ifc_bank].ftim[i],
+					&ifc->ftim_cs[ifc_bank].ftim[i]);
+			}
+		}
+		ifc_out32(savd_regs->ifc_gcr, &ifc->ifc_gcr);
+		ifc_out32(savd_regs->cm_evter_en, &ifc->cm_evter_en);
+
+/*
+* IFC controller NAND machine registers
+*/
+		ifc_out32(savd_regs->ifc_nand.ncfgr, &ifc->ifc_nand.ncfgr);
+		ifc_out32(savd_regs->ifc_nand.nand_fcr0,
+						&ifc->ifc_nand.nand_fcr0);
+		ifc_out32(savd_regs->ifc_nand.nand_fcr1,
+						&ifc->ifc_nand.nand_fcr1);
+		ifc_out32(savd_regs->ifc_nand.row0, &ifc->ifc_nand.row0);
+		ifc_out32(savd_regs->ifc_nand.row1, &ifc->ifc_nand.row1);
+		ifc_out32(savd_regs->ifc_nand.col0, &ifc->ifc_nand.col0);
+		ifc_out32(savd_regs->ifc_nand.col1, &ifc->ifc_nand.col1);
+		ifc_out32(savd_regs->ifc_nand.row2, &ifc->ifc_nand.row2);
+		ifc_out32(savd_regs->ifc_nand.col2, &ifc->ifc_nand.col2);
+		ifc_out32(savd_regs->ifc_nand.row3, &ifc->ifc_nand.row3);
+		ifc_out32(savd_regs->ifc_nand.col3, &ifc->ifc_nand.col3);
+		ifc_out32(savd_regs->ifc_nand.nand_fbcr,
+						&ifc->ifc_nand.nand_fbcr);
+		ifc_out32(savd_regs->ifc_nand.nand_fir0,
+						&ifc->ifc_nand.nand_fir0);
+		ifc_out32(savd_regs->ifc_nand.nand_fir1,
+						&ifc->ifc_nand.nand_fir1);
+		ifc_out32(savd_regs->ifc_nand.nand_fir2,
+						&ifc->ifc_nand.nand_fir2);
+		ifc_out32(savd_regs->ifc_nand.nand_csel,
+						&ifc->ifc_nand.nand_csel);
+		ifc_out32(savd_regs->ifc_nand.nandseq_strt,
+						&ifc->ifc_nand.nandseq_strt);
+		ifc_out32(savd_regs->ifc_nand.nand_evter_en,
+						&ifc->ifc_nand.nand_evter_en);
+		ifc_out32(savd_regs->ifc_nand.nanndcr, &ifc->ifc_nand.nanndcr);
+
+/*
+* IFC controller NOR machine registers
+*/
+		ifc_out32(savd_regs->ifc_nor.nor_evter_en,
+					&ifc->ifc_nor.nor_evter_en);
+		ifc_out32(savd_regs->ifc_nor.norcr, &ifc->ifc_nor.norcr);
+
+/*
+ * IFC controller GPCM Machine registers
+ */
+		ifc_out32(savd_regs->ifc_gpcm.gpcm_evter_en,
+					&ifc->ifc_gpcm.gpcm_evter_en);
+
+
+
+/*
+ * IFC interrupts enabled
+ */
+	ifc_out32(ctrl->saved_regs->cm_evter_intr_en, &ifc->cm_evter_intr_en);
+	ifc_out32(ctrl->saved_regs->ifc_nand.nand_evter_intr_en,
+					&ifc->ifc_nand.nand_evter_intr_en);
+	ifc_out32(ctrl->saved_regs->ifc_nor.nor_evter_intr_en,
+					&ifc->ifc_nor.nor_evter_intr_en);
+	ifc_out32(ctrl->saved_regs->ifc_gpcm.gpcm_evter_intr_en,
+					&ifc->ifc_gpcm.gpcm_evter_intr_en);
+
+		kfree(ctrl->saved_regs);
+		ctrl->saved_regs = NULL;
+	}
+
+	ver = ifc_in32(&ctrl->regs->ifc_rev);
+	ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
+	if (ver >= FSL_IFC_V1_3_0) {
+
+		ifc_out32(ncfgr | IFC_NAND_SRAM_INIT_EN,
+					&ifc->ifc_nand.ncfgr);
+		/* wait for  SRAM_INIT bit to be clear or timeout */
+		status = spin_event_timeout(
+					!(ifc_in32(&ifc->ifc_nand.ncfgr)
+					& IFC_NAND_SRAM_INIT_EN),
+					IFC_TIMEOUT_MSECS, 0);
+
+		if (!status)
+			dev_err(ctrl->dev, "Timeout waiting for IFC SRAM INIT");
+	}
+
+	return 0;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+ static const struct of_device_id fsl_ifc_match[] = {
+ 	{
+ 		.compatible = "fsl,ifc",
+@@ -316,10 +474,15 @@ static const struct of_device_id fsl_ifc
+ 	{},
+ };
+ 
+static const struct dev_pm_ops ifc_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(fsl_ifc_suspend, fsl_ifc_resume)
+};
+
+ static struct platform_driver fsl_ifc_ctrl_driver = {
+ 	.driver = {
+ 		.name	= "fsl-ifc",
+ 		.of_match_table = fsl_ifc_match,
+		.pm = &ifc_pm_ops,
+ 	},
+ 	.probe       = fsl_ifc_ctrl_probe,
+ 	.remove      = fsl_ifc_ctrl_remove,
+--- a/include/linux/fsl_ifc.h
+++ b/include/linux/fsl_ifc.h
+@@ -270,6 +270,8 @@
+  */
+ /* Auto Boot Mode */
+ #define IFC_NAND_NCFGR_BOOT		0x80000000
+/* SRAM INIT EN */
+#define IFC_NAND_SRAM_INIT_EN		0x20000000
+ /* Addressing Mode-ROW0+n/COL0 */
+ #define IFC_NAND_NCFGR_ADDR_MODE_RC0	0x00000000
+ /* Addressing Mode-ROW0+n/COL0+n */
+@@ -842,6 +844,10 @@ struct fsl_ifc_ctrl {
+ 	u32 nand_stat;
+ 	wait_queue_head_t nand_wait;
+ 	bool little_endian;
+#ifdef CONFIG_PM_SLEEP
+	/*save regs when system goes to deep sleep*/
+	struct fsl_ifc_regs		*saved_regs;
+#endif
+ };
+ 
+ extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
--- a/target/linux/layerscape/patches-4.4/4045-driver-memory-Update-dependency-of-IFC-for-Layerscap.patch
+++ b/target/linux/layerscape/patches-4.4/4045-driver-memory-Update-dependency-of-IFC-for-Layerscap.patch
@ -0,0 +1,51 @@
+From bf489e54ef3de7de2d9caf896141fd08490a89c9 Mon Sep 17 00:00:00 2001
+From: Raghav Dogra <raghav@freescale.com>
+Date: Wed, 16 Dec 2015 16:11:50 +0530
+Subject: [PATCH 45/70] driver/memory: Update dependency of IFC for Layerscape
+
+IFC NAND is not working on ARM layescape platform due to
+undefined macro FSL_SOC.
+This patch fixes the dependency to enable NAND.
+
+Signed-off-by: Raghav Dogra <raghav@freescale.com>
+---
+ drivers/memory/Kconfig   |    2 +-
+ drivers/memory/fsl_ifc.c |    4 +++-
+ drivers/mtd/nand/Kconfig |    2 +-
+ 3 files changed, 5 insertions(+), 3 deletions(-)
+
+--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
+@@ -103,7 +103,7 @@ config FSL_CORENET_CF
+ 
+ config FSL_IFC
+ 	bool
+-	depends on FSL_SOC
+	depends on FSL_SOC || ARCH_LAYERSCAPE
+ 
+ config JZ4780_NEMC
+ 	bool "Ingenic JZ4780 SoC NEMC driver"
+--- a/drivers/memory/fsl_ifc.c
+++ b/drivers/memory/fsl_ifc.c
+@@ -32,7 +32,9 @@
+ #include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/fsl_ifc.h>
+-#include <asm/prom.h>
+#include <linux/irqdomain.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+ 
+ struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
+ EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
+--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
+@@ -436,7 +436,7 @@ config MTD_NAND_FSL_ELBC
+ 
+ config MTD_NAND_FSL_IFC
+ 	tristate "NAND support for Freescale IFC controller"
+-	depends on MTD_NAND && FSL_SOC
+	depends on MTD_NAND && (FSL_SOC || ARCH_LAYERSCAPE)
+ 	select FSL_IFC
+ 	select MEMORY
+ 	help
--- a/target/linux/layerscape/patches-4.4/4046-mtd-ifc-Segregate-IFC-fcm-and-runtime-registers.patch
+++ b/target/linux/layerscape/patches-4.4/4046-mtd-ifc-Segregate-IFC-fcm-and-runtime-registers.patch
@ -0,0 +1,705 @@
+From 1c62b9982b7f6cb560d1237d2658945c070c91d4 Mon Sep 17 00:00:00 2001
+From: Raghav Dogra <raghav@freescale.com>
+Date: Wed, 20 Jan 2016 13:06:32 +0530
+Subject: [PATCH 46/70] mtd/ifc: Segregate IFC fcm and runtime registers
+
+IFC has two set of registers viz FCM (Flash control machine)
+aka global and run time registers. These set are defined in two
+memory map PAGES. Upto IFC 1.4 PAGE size is 4 KB and from IFC2.0
+PAGE size is 64KB
+
+Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
+Signed-off-by: Raghav Dogra <raghav@freescale.com>
+---
+ drivers/memory/fsl_ifc.c        |  251 ++++++++++++++++++++-------------------
+ drivers/mtd/nand/fsl_ifc_nand.c |   72 ++++++-----
+ include/linux/fsl_ifc.h         |   48 +++++---
+ 3 files changed, 203 insertions(+), 168 deletions(-)
+
+--- a/drivers/memory/fsl_ifc.c
+++ b/drivers/memory/fsl_ifc.c
+@@ -64,11 +64,11 @@ int fsl_ifc_find(phys_addr_t addr_base)
+ {
+ 	int i = 0;
+ 
+-	if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
+	if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->gregs)
+ 		return -ENODEV;
+ 
+ 	for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
+-		u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->regs->cspr_cs[i].cspr);
+		u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->gregs->cspr_cs[i].cspr);
+ 		if (cspr & CSPR_V && (cspr & CSPR_BA) ==
+ 				convert_ifc_address(addr_base))
+ 			return i;
+@@ -80,7 +80,7 @@ EXPORT_SYMBOL(fsl_ifc_find);
+ 
+ static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
+ {
+-	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+	struct fsl_ifc_fcm __iomem *ifc = ctrl->gregs;
+ 
+ 	/*
+ 	 * Clear all the common status and event registers
+@@ -109,7 +109,7 @@ static int fsl_ifc_ctrl_remove(struct pl
+ 	irq_dispose_mapping(ctrl->nand_irq);
+ 	irq_dispose_mapping(ctrl->irq);
+ 
+-	iounmap(ctrl->regs);
+	iounmap(ctrl->gregs);
+ 
+ 	dev_set_drvdata(&dev->dev, NULL);
+ 	kfree(ctrl);
+@@ -127,7 +127,7 @@ static DEFINE_SPINLOCK(nand_irq_lock);
+ 
+ static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
+ {
+-	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+	struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
+ 	unsigned long flags;
+ 	u32 stat;
+ 
+@@ -162,7 +162,7 @@ static irqreturn_t fsl_ifc_nand_irq(int
+ static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
+ {
+ 	struct fsl_ifc_ctrl *ctrl = data;
+-	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+	struct fsl_ifc_fcm __iomem *ifc = ctrl->gregs;
+ 	u32 err_axiid, err_srcid, status, cs_err, err_addr;
+ 	irqreturn_t ret = IRQ_NONE;
+ 
+@@ -220,6 +220,7 @@ static int fsl_ifc_ctrl_probe(struct pla
+ {
+ 	int ret = 0;
+ 	int version, banks;
+	void __iomem *addr;
+ 
+ 	dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");
+ 
+@@ -230,22 +231,13 @@ static int fsl_ifc_ctrl_probe(struct pla
+ 	dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev);
+ 
+ 	/* IOMAP the entire IFC region */
+-	fsl_ifc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
+-	if (!fsl_ifc_ctrl_dev->regs) {
+	fsl_ifc_ctrl_dev->gregs = of_iomap(dev->dev.of_node, 0);
+	if (!fsl_ifc_ctrl_dev->gregs) {
+ 		dev_err(&dev->dev, "failed to get memory region\n");
+ 		ret = -ENODEV;
+ 		goto err;
+ 	}
+ 
+-	version = ifc_in32(&fsl_ifc_ctrl_dev->regs->ifc_rev) &
+-			FSL_IFC_VERSION_MASK;
+-	banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
+-	dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
+-		version >> 24, (version >> 16) & 0xf, banks);
+-
+-	fsl_ifc_ctrl_dev->version = version;
+-	fsl_ifc_ctrl_dev->banks = banks;
+-
+ 	if (of_property_read_bool(dev->dev.of_node, "little-endian")) {
+ 		fsl_ifc_ctrl_dev->little_endian = true;
+ 		dev_dbg(&dev->dev, "IFC REGISTERS are LITTLE endian\n");
+@@ -254,8 +246,9 @@ static int fsl_ifc_ctrl_probe(struct pla
+ 		dev_dbg(&dev->dev, "IFC REGISTERS are BIG endian\n");
+ 	}
+ 
+-	version = ioread32be(&fsl_ifc_ctrl_dev->regs->ifc_rev) &
+	version = ifc_in32(&fsl_ifc_ctrl_dev->gregs->ifc_rev) &
+ 			FSL_IFC_VERSION_MASK;
+
+ 	banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
+ 	dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
+ 		version >> 24, (version >> 16) & 0xf, banks);
+@@ -263,6 +256,14 @@ static int fsl_ifc_ctrl_probe(struct pla
+ 	fsl_ifc_ctrl_dev->version = version;
+ 	fsl_ifc_ctrl_dev->banks = banks;
+ 
+	addr = fsl_ifc_ctrl_dev->gregs;
+	if (version >= FSL_IFC_VERSION_2_0_0)
+		fsl_ifc_ctrl_dev->rregs =
+			(struct fsl_ifc_runtime *)(addr + PGOFFSET_64K);
+	else
+		fsl_ifc_ctrl_dev->rregs =
+			(struct fsl_ifc_runtime *)(addr + PGOFFSET_4K);
+
+ 	/* get the Controller level irq */
+ 	fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
+ 	if (fsl_ifc_ctrl_dev->irq == 0) {
+@@ -319,33 +320,39 @@ err:
+ static int fsl_ifc_suspend(struct device *dev)
+ {
+ 	struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
+-	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+	struct fsl_ifc_fcm __iomem *fcm = ctrl->gregs;
+	struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
+ 	__be32 nand_evter_intr_en, cm_evter_intr_en, nor_evter_intr_en,
+ 							 gpcm_evter_intr_en;
+ 
+-	ctrl->saved_regs = kzalloc(sizeof(struct fsl_ifc_regs), GFP_KERNEL);
+-	if (!ctrl->saved_regs)
+	ctrl->saved_gregs = kzalloc(sizeof(struct fsl_ifc_fcm), GFP_KERNEL);
+	if (!ctrl->saved_gregs)
+		return -ENOMEM;
+	ctrl->saved_rregs = kzalloc(sizeof(struct fsl_ifc_runtime), GFP_KERNEL);
+	if (!ctrl->saved_rregs)
+ 		return -ENOMEM;
+ 
+-	cm_evter_intr_en = ifc_in32(&ifc->cm_evter_intr_en);
+-	nand_evter_intr_en = ifc_in32(&ifc->ifc_nand.nand_evter_intr_en);
+-	nor_evter_intr_en = ifc_in32(&ifc->ifc_nor.nor_evter_intr_en);
+-	gpcm_evter_intr_en = ifc_in32(&ifc->ifc_gpcm.gpcm_evter_intr_en);
+	cm_evter_intr_en = ifc_in32(&fcm->cm_evter_intr_en);
+	nand_evter_intr_en = ifc_in32(&runtime->ifc_nand.nand_evter_intr_en);
+	nor_evter_intr_en = ifc_in32(&runtime->ifc_nor.nor_evter_intr_en);
+	gpcm_evter_intr_en = ifc_in32(&runtime->ifc_gpcm.gpcm_evter_intr_en);
+ 
+ /* IFC interrupts disabled */
+ 
+-	ifc_out32(0x0, &ifc->cm_evter_intr_en);
+-	ifc_out32(0x0, &ifc->ifc_nand.nand_evter_intr_en);
+-	ifc_out32(0x0, &ifc->ifc_nor.nor_evter_intr_en);
+-	ifc_out32(0x0, &ifc->ifc_gpcm.gpcm_evter_intr_en);
+-
+-	memcpy_fromio(ctrl->saved_regs, ifc, sizeof(struct fsl_ifc_regs));
+	ifc_out32(0x0, &fcm->cm_evter_intr_en);
+	ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en);
+	ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en);
+	ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en);
+
+	memcpy_fromio(ctrl->saved_gregs, fcm, sizeof(struct fsl_ifc_fcm));
+	memcpy_fromio(ctrl->saved_rregs, runtime,
+					sizeof(struct fsl_ifc_runtime));
+ 
+ /* save the interrupt values */
+-	ctrl->saved_regs->cm_evter_intr_en = cm_evter_intr_en;
+-	ctrl->saved_regs->ifc_nand.nand_evter_intr_en = nand_evter_intr_en;
+-	ctrl->saved_regs->ifc_nor.nor_evter_intr_en = nor_evter_intr_en;
+-	ctrl->saved_regs->ifc_gpcm.gpcm_evter_intr_en = gpcm_evter_intr_en;
+	ctrl->saved_gregs->cm_evter_intr_en = cm_evter_intr_en;
+	ctrl->saved_rregs->ifc_nand.nand_evter_intr_en = nand_evter_intr_en;
+	ctrl->saved_rregs->ifc_nor.nor_evter_intr_en = nor_evter_intr_en;
+	ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en = gpcm_evter_intr_en;
+ 
+ 	return 0;
+ }
+@@ -354,110 +361,116 @@ static int fsl_ifc_suspend(struct device
+ static int fsl_ifc_resume(struct device *dev)
+ {
+ 	struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
+-	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+-	struct fsl_ifc_regs *savd_regs = ctrl->saved_regs;
+	struct fsl_ifc_fcm __iomem *fcm = ctrl->gregs;
+	struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
+	struct fsl_ifc_fcm *savd_gregs = ctrl->saved_gregs;
+	struct fsl_ifc_runtime *savd_rregs = ctrl->saved_rregs;
+ 	uint32_t ver = 0, ncfgr, status, ifc_bank, i;
+ 
+ /*
+  * IFC interrupts disabled
+  */
+-	ifc_out32(0x0, &ifc->cm_evter_intr_en);
+-	ifc_out32(0x0, &ifc->ifc_nand.nand_evter_intr_en);
+-	ifc_out32(0x0, &ifc->ifc_nor.nor_evter_intr_en);
+-	ifc_out32(0x0, &ifc->ifc_gpcm.gpcm_evter_intr_en);
+	ifc_out32(0x0, &fcm->cm_evter_intr_en);
+	ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en);
+	ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en);
+	ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en);
+ 
+ 
+-	if (ctrl->saved_regs) {
+	if (ctrl->saved_gregs) {
+ 		for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) {
+-			ifc_out32(savd_regs->cspr_cs[ifc_bank].cspr_ext,
+-					&ifc->cspr_cs[ifc_bank].cspr_ext);
+-			ifc_out32(savd_regs->cspr_cs[ifc_bank].cspr,
+-					&ifc->cspr_cs[ifc_bank].cspr);
+-			ifc_out32(savd_regs->amask_cs[ifc_bank].amask,
+-					&ifc->amask_cs[ifc_bank].amask);
+-			ifc_out32(savd_regs->csor_cs[ifc_bank].csor_ext,
+-					&ifc->csor_cs[ifc_bank].csor_ext);
+-			ifc_out32(savd_regs->csor_cs[ifc_bank].csor,
+-					&ifc->csor_cs[ifc_bank].csor);
+			ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr_ext,
+					&fcm->cspr_cs[ifc_bank].cspr_ext);
+			ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr,
+					&fcm->cspr_cs[ifc_bank].cspr);
+			ifc_out32(savd_gregs->amask_cs[ifc_bank].amask,
+					&fcm->amask_cs[ifc_bank].amask);
+			ifc_out32(savd_gregs->csor_cs[ifc_bank].csor_ext,
+					&fcm->csor_cs[ifc_bank].csor_ext);
+			ifc_out32(savd_gregs->csor_cs[ifc_bank].csor,
+					&fcm->csor_cs[ifc_bank].csor);
+ 			for (i = 0; i < 4; i++) {
+-				ifc_out32(savd_regs->ftim_cs[ifc_bank].ftim[i],
+-					&ifc->ftim_cs[ifc_bank].ftim[i]);
+				ifc_out32(savd_gregs->ftim_cs[ifc_bank].ftim[i],
+					&fcm->ftim_cs[ifc_bank].ftim[i]);
+ 			}
+ 		}
+-		ifc_out32(savd_regs->ifc_gcr, &ifc->ifc_gcr);
+-		ifc_out32(savd_regs->cm_evter_en, &ifc->cm_evter_en);
+-
+-/*
+-* IFC controller NAND machine registers
+-*/
+-		ifc_out32(savd_regs->ifc_nand.ncfgr, &ifc->ifc_nand.ncfgr);
+-		ifc_out32(savd_regs->ifc_nand.nand_fcr0,
+-						&ifc->ifc_nand.nand_fcr0);
+-		ifc_out32(savd_regs->ifc_nand.nand_fcr1,
+-						&ifc->ifc_nand.nand_fcr1);
+-		ifc_out32(savd_regs->ifc_nand.row0, &ifc->ifc_nand.row0);
+-		ifc_out32(savd_regs->ifc_nand.row1, &ifc->ifc_nand.row1);
+-		ifc_out32(savd_regs->ifc_nand.col0, &ifc->ifc_nand.col0);
+-		ifc_out32(savd_regs->ifc_nand.col1, &ifc->ifc_nand.col1);
+-		ifc_out32(savd_regs->ifc_nand.row2, &ifc->ifc_nand.row2);
+-		ifc_out32(savd_regs->ifc_nand.col2, &ifc->ifc_nand.col2);
+-		ifc_out32(savd_regs->ifc_nand.row3, &ifc->ifc_nand.row3);
+-		ifc_out32(savd_regs->ifc_nand.col3, &ifc->ifc_nand.col3);
+-		ifc_out32(savd_regs->ifc_nand.nand_fbcr,
+-						&ifc->ifc_nand.nand_fbcr);
+-		ifc_out32(savd_regs->ifc_nand.nand_fir0,
+-						&ifc->ifc_nand.nand_fir0);
+-		ifc_out32(savd_regs->ifc_nand.nand_fir1,
+-						&ifc->ifc_nand.nand_fir1);
+-		ifc_out32(savd_regs->ifc_nand.nand_fir2,
+-						&ifc->ifc_nand.nand_fir2);
+-		ifc_out32(savd_regs->ifc_nand.nand_csel,
+-						&ifc->ifc_nand.nand_csel);
+-		ifc_out32(savd_regs->ifc_nand.nandseq_strt,
+-						&ifc->ifc_nand.nandseq_strt);
+-		ifc_out32(savd_regs->ifc_nand.nand_evter_en,
+-						&ifc->ifc_nand.nand_evter_en);
+-		ifc_out32(savd_regs->ifc_nand.nanndcr, &ifc->ifc_nand.nanndcr);
+-
+-/*
+-* IFC controller NOR machine registers
+-*/
+-		ifc_out32(savd_regs->ifc_nor.nor_evter_en,
+-					&ifc->ifc_nor.nor_evter_en);
+-		ifc_out32(savd_regs->ifc_nor.norcr, &ifc->ifc_nor.norcr);
+-
+-/*
+- * IFC controller GPCM Machine registers
+- */
+-		ifc_out32(savd_regs->ifc_gpcm.gpcm_evter_en,
+-					&ifc->ifc_gpcm.gpcm_evter_en);
+-
+-
+-
+-/*
+- * IFC interrupts enabled
+- */
+-	ifc_out32(ctrl->saved_regs->cm_evter_intr_en, &ifc->cm_evter_intr_en);
+-	ifc_out32(ctrl->saved_regs->ifc_nand.nand_evter_intr_en,
+-					&ifc->ifc_nand.nand_evter_intr_en);
+-	ifc_out32(ctrl->saved_regs->ifc_nor.nor_evter_intr_en,
+-					&ifc->ifc_nor.nor_evter_intr_en);
+-	ifc_out32(ctrl->saved_regs->ifc_gpcm.gpcm_evter_intr_en,
+-					&ifc->ifc_gpcm.gpcm_evter_intr_en);
+		ifc_out32(savd_gregs->rb_map, &fcm->rb_map);
+		ifc_out32(savd_gregs->wb_map, &fcm->wb_map);
+		ifc_out32(savd_gregs->ifc_gcr, &fcm->ifc_gcr);
+		ifc_out32(savd_gregs->ddr_ccr_low, &fcm->ddr_ccr_low);
+		ifc_out32(savd_gregs->cm_evter_en, &fcm->cm_evter_en);
+	}
+ 
+-		kfree(ctrl->saved_regs);
+-		ctrl->saved_regs = NULL;
+	if (ctrl->saved_rregs) {
+		/* IFC controller NAND machine registers */
+		ifc_out32(savd_rregs->ifc_nand.ncfgr,
+						&runtime->ifc_nand.ncfgr);
+		ifc_out32(savd_rregs->ifc_nand.nand_fcr0,
+						&runtime->ifc_nand.nand_fcr0);
+		ifc_out32(savd_rregs->ifc_nand.nand_fcr1,
+						&runtime->ifc_nand.nand_fcr1);
+		ifc_out32(savd_rregs->ifc_nand.row0, &runtime->ifc_nand.row0);
+		ifc_out32(savd_rregs->ifc_nand.row1, &runtime->ifc_nand.row1);
+		ifc_out32(savd_rregs->ifc_nand.col0, &runtime->ifc_nand.col0);
+		ifc_out32(savd_rregs->ifc_nand.col1, &runtime->ifc_nand.col1);
+		ifc_out32(savd_rregs->ifc_nand.row2, &runtime->ifc_nand.row2);
+		ifc_out32(savd_rregs->ifc_nand.col2, &runtime->ifc_nand.col2);
+		ifc_out32(savd_rregs->ifc_nand.row3, &runtime->ifc_nand.row3);
+		ifc_out32(savd_rregs->ifc_nand.col3, &runtime->ifc_nand.col3);
+		ifc_out32(savd_rregs->ifc_nand.nand_fbcr,
+						&runtime->ifc_nand.nand_fbcr);
+		ifc_out32(savd_rregs->ifc_nand.nand_fir0,
+						&runtime->ifc_nand.nand_fir0);
+		ifc_out32(savd_rregs->ifc_nand.nand_fir1,
+						&runtime->ifc_nand.nand_fir1);
+		ifc_out32(savd_rregs->ifc_nand.nand_fir2,
+						&runtime->ifc_nand.nand_fir2);
+		ifc_out32(savd_rregs->ifc_nand.nand_csel,
+						&runtime->ifc_nand.nand_csel);
+		ifc_out32(savd_rregs->ifc_nand.nandseq_strt,
+					&runtime->ifc_nand.nandseq_strt);
+		ifc_out32(savd_rregs->ifc_nand.nand_evter_en,
+					&runtime->ifc_nand.nand_evter_en);
+		ifc_out32(savd_rregs->ifc_nand.nanndcr,
+					&runtime->ifc_nand.nanndcr);
+		ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg0,
+					&runtime->ifc_nand.nand_dll_lowcfg0);
+		ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg1,
+					&runtime->ifc_nand.nand_dll_lowcfg1);
+
+		/* IFC controller NOR machine registers */
+		ifc_out32(savd_rregs->ifc_nor.nor_evter_en,
+					&runtime->ifc_nor.nor_evter_en);
+		ifc_out32(savd_rregs->ifc_nor.norcr, &runtime->ifc_nor.norcr);
+
+		/* IFC controller GPCM Machine registers */
+		ifc_out32(savd_rregs->ifc_gpcm.gpcm_evter_en,
+					&runtime->ifc_gpcm.gpcm_evter_en);
+
+		/* IFC interrupts enabled */
+		ifc_out32(ctrl->saved_gregs->cm_evter_intr_en,
+					&fcm->cm_evter_intr_en);
+		ifc_out32(ctrl->saved_rregs->ifc_nand.nand_evter_intr_en,
+					&runtime->ifc_nand.nand_evter_intr_en);
+		ifc_out32(ctrl->saved_rregs->ifc_nor.nor_evter_intr_en,
+					&runtime->ifc_nor.nor_evter_intr_en);
+		ifc_out32(ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en,
+					&runtime->ifc_gpcm.gpcm_evter_intr_en);
+
+		kfree(ctrl->saved_gregs);
+		kfree(ctrl->saved_rregs);
+		ctrl->saved_gregs = NULL;
+		ctrl->saved_rregs = NULL;
+ 	}
+ 
+-	ver = ifc_in32(&ctrl->regs->ifc_rev);
+-	ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
+	ver = ifc_in32(&fcm->ifc_rev);
+	ncfgr = ifc_in32(&runtime->ifc_nand.ncfgr);
+ 	if (ver >= FSL_IFC_V1_3_0) {
+ 
+ 		ifc_out32(ncfgr | IFC_NAND_SRAM_INIT_EN,
+-					&ifc->ifc_nand.ncfgr);
+					&runtime->ifc_nand.ncfgr);
+ 		/* wait for  SRAM_INIT bit to be clear or timeout */
+ 		status = spin_event_timeout(
+-					!(ifc_in32(&ifc->ifc_nand.ncfgr)
+					!(ifc_in32(&runtime->ifc_nand.ncfgr)
+ 					& IFC_NAND_SRAM_INIT_EN),
+ 					IFC_TIMEOUT_MSECS, 0);
+ 
+--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
+@@ -233,7 +233,7 @@ static void set_addr(struct mtd_info *mt
+ 	struct nand_chip *chip = mtd->priv;
+ 	struct fsl_ifc_mtd *priv = chip->priv;
+ 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
+-	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+	struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
+ 	int buf_num;
+ 
+ 	ifc_nand_ctrl->page = page_addr;
+@@ -296,7 +296,7 @@ static void fsl_ifc_run_command(struct m
+ 	struct fsl_ifc_mtd *priv = chip->priv;
+ 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
+ 	struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
+-	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+	struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
+ 	u32 eccstat[4];
+ 	int i;
+ 
+@@ -372,7 +372,7 @@ static void fsl_ifc_do_read(struct nand_
+ {
+ 	struct fsl_ifc_mtd *priv = chip->priv;
+ 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
+-	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+	struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
+ 
+ 	/* Program FIR/IFC_NAND_FCR0 for Small/Large page */
+ 	if (mtd->writesize > 512) {
+@@ -412,7 +412,7 @@ static void fsl_ifc_cmdfunc(struct mtd_i
+ 	struct nand_chip *chip = mtd->priv;
+ 	struct fsl_ifc_mtd *priv = chip->priv;
+ 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
+-	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+	struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
+ 
+ 	/* clear the read buffer */
+ 	ifc_nand_ctrl->read_bytes = 0;
+@@ -724,7 +724,7 @@ static int fsl_ifc_wait(struct mtd_info
+ {
+ 	struct fsl_ifc_mtd *priv = chip->priv;
+ 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
+-	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+	struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
+ 	u32 nand_fsr;
+ 
+ 	/* Use READ_STATUS command, but wait for the device to be ready */
+@@ -826,39 +826,42 @@ static int fsl_ifc_chip_init_tail(struct
+ static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
+ {
+ 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
+-	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+	struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
+	struct fsl_ifc_fcm __iomem *ifc_global = ctrl->gregs;
+ 	uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
+ 	uint32_t cs = priv->bank;
+ 
+ 	/* Save CSOR and CSOR_ext */
+-	csor = ifc_in32(&ifc->csor_cs[cs].csor);
+-	csor_ext = ifc_in32(&ifc->csor_cs[cs].csor_ext);
+	csor = ifc_in32(&ifc_global->csor_cs[cs].csor);
+	csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext);
+ 
+ 	/* chage PageSize 8K and SpareSize 1K*/
+ 	csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
+-	ifc_out32(csor_8k, &ifc->csor_cs[cs].csor);
+-	ifc_out32(0x0000400, &ifc->csor_cs[cs].csor_ext);
+	ifc_out32(csor_8k, &ifc_global->csor_cs[cs].csor);
+	ifc_out32(0x0000400, &ifc_global->csor_cs[cs].csor_ext);
+ 
+ 	/* READID */
+ 	ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
+-		  (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
+-		  (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
+-		  &ifc->ifc_nand.nand_fir0);
+		    (IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
+		    (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
+		    &ifc_runtime->ifc_nand.nand_fir0);
+ 	ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
+-		  &ifc->ifc_nand.nand_fcr0);
+-	ifc_out32(0x0, &ifc->ifc_nand.row3);
+		    &ifc_runtime->ifc_nand.nand_fcr0);
+	ifc_out32(0x0, &ifc_runtime->ifc_nand.row3);
+ 
+-	ifc_out32(0x0, &ifc->ifc_nand.nand_fbcr);
+	ifc_out32(0x0, &ifc_runtime->ifc_nand.nand_fbcr);
+ 
+ 	/* Program ROW0/COL0 */
+-	ifc_out32(0x0, &ifc->ifc_nand.row0);
+-	ifc_out32(0x0, &ifc->ifc_nand.col0);
+	ifc_out32(0x0, &ifc_runtime->ifc_nand.row0);
+	ifc_out32(0x0, &ifc_runtime->ifc_nand.col0);
+ 
+ 	/* set the chip select for NAND Transaction */
+-	ifc_out32(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel);
+	ifc_out32(cs << IFC_NAND_CSEL_SHIFT,
+		&ifc_runtime->ifc_nand.nand_csel);
+ 
+ 	/* start read seq */
+-	ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
+	ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT,
+		&ifc_runtime->ifc_nand.nandseq_strt);
+ 
+ 	/* wait for command complete flag or timeout */
+ 	wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
+@@ -868,14 +871,15 @@ static void fsl_ifc_sram_init(struct fsl
+ 		printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
+ 
+ 	/* Restore CSOR and CSOR_ext */
+-	ifc_out32(csor, &ifc->csor_cs[cs].csor);
+-	ifc_out32(csor_ext, &ifc->csor_cs[cs].csor_ext);
+	ifc_out32(csor, &ifc_global->csor_cs[cs].csor);
+	ifc_out32(csor_ext, &ifc_global->csor_cs[cs].csor_ext);
+ }
+ 
+ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
+ {
+ 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
+-	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+	struct fsl_ifc_fcm __iomem *ifc_global = ctrl->gregs;
+	struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
+ 	struct nand_chip *chip = &priv->chip;
+ 	struct nand_ecclayout *layout;
+ 	u32 csor;
+@@ -886,7 +890,8 @@ static int fsl_ifc_chip_init(struct fsl_
+ 
+ 	/* fill in nand_chip structure */
+ 	/* set up function call table */
+-	if ((ifc_in32(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
+	if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr))
+		& CSPR_PORT_SIZE_16)
+ 		chip->read_byte = fsl_ifc_read_byte16;
+ 	else
+ 		chip->read_byte = fsl_ifc_read_byte;
+@@ -900,13 +905,14 @@ static int fsl_ifc_chip_init(struct fsl_
+ 	chip->bbt_td = &bbt_main_descr;
+ 	chip->bbt_md = &bbt_mirror_descr;
+ 
+-	ifc_out32(0x0, &ifc->ifc_nand.ncfgr);
+	ifc_out32(0x0, &ifc_runtime->ifc_nand.ncfgr);
+ 
+ 	/* set up nand options */
+ 	chip->bbt_options = NAND_BBT_USE_FLASH;
+ 	chip->options = NAND_NO_SUBPAGE_WRITE;
+ 
+-	if (ifc_in32(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
+	if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)
+		& CSPR_PORT_SIZE_16) {
+ 		chip->read_byte = fsl_ifc_read_byte16;
+ 		chip->options |= NAND_BUSWIDTH_16;
+ 	} else {
+@@ -919,7 +925,7 @@ static int fsl_ifc_chip_init(struct fsl_
+ 	chip->ecc.read_page = fsl_ifc_read_page;
+ 	chip->ecc.write_page = fsl_ifc_write_page;
+ 
+-	csor = ifc_in32(&ifc->csor_cs[priv->bank].csor);
+	csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
+ 
+ 	/* Hardware generates ECC per 512 Bytes */
+ 	chip->ecc.size = 512;
+@@ -1005,10 +1011,10 @@ static int fsl_ifc_chip_remove(struct fs
+ 	return 0;
+ }
+ 
+-static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank,
+static int match_bank(struct fsl_ifc_fcm __iomem *ifc_global, int bank,
+ 		      phys_addr_t addr)
+ {
+-	u32 cspr = ifc_in32(&ifc->cspr_cs[bank].cspr);
+	u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr);
+ 
+ 	if (!(cspr & CSPR_V))
+ 		return 0;
+@@ -1022,7 +1028,7 @@ static DEFINE_MUTEX(fsl_ifc_nand_mutex);
+ 
+ static int fsl_ifc_nand_probe(struct platform_device *dev)
+ {
+-	struct fsl_ifc_regs __iomem *ifc;
+	struct fsl_ifc_runtime __iomem *ifc;
+ 	struct fsl_ifc_mtd *priv;
+ 	struct resource res;
+ 	static const char *part_probe_types[]
+@@ -1033,9 +1039,9 @@ static int fsl_ifc_nand_probe(struct pla
+ 	struct mtd_part_parser_data ppdata;
+ 
+ 	ppdata.of_node = dev->dev.of_node;
+-	if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
+	if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->rregs)
+ 		return -ENODEV;
+-	ifc = fsl_ifc_ctrl_dev->regs;
+	ifc = fsl_ifc_ctrl_dev->rregs;
+ 
+ 	/* get, allocate and map the memory resource */
+ 	ret = of_address_to_resource(node, 0, &res);
+@@ -1046,7 +1052,7 @@ static int fsl_ifc_nand_probe(struct pla
+ 
+ 	/* find which chip select it is connected to */
+ 	for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) {
+-		if (match_bank(ifc, bank, res.start))
+		if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start))
+ 			break;
+ 	}
+ 
+--- a/include/linux/fsl_ifc.h
+++ b/include/linux/fsl_ifc.h
+@@ -39,6 +39,10 @@
+ #define FSL_IFC_VERSION_MASK	0x0F0F0000
+ #define FSL_IFC_VERSION_1_0_0	0x01000000
+ #define FSL_IFC_VERSION_1_1_0	0x01010000
+#define FSL_IFC_VERSION_2_0_0	0x02000000
+
+#define PGOFFSET_64K	(64*1024)
+#define PGOFFSET_4K	(4*1024)
+ 
+ /*
+  * CSPR - Chip Select Property Register
+@@ -725,20 +729,26 @@ struct fsl_ifc_nand {
+ 	__be32 nand_evter_en;
+ 	u32 res17[0x2];
+ 	__be32 nand_evter_intr_en;
+-	u32 res18[0x2];
+	__be32 nand_vol_addr_stat;
+	u32 res18;
+ 	__be32 nand_erattr0;
+ 	__be32 nand_erattr1;
+ 	u32 res19[0x10];
+ 	__be32 nand_fsr;
+-	u32 res20;
+-	__be32 nand_eccstat[4];
+-	u32 res21[0x20];
+	u32 res20[0x3];
+	__be32 nand_eccstat[6];
+	u32 res21[0x1c];
+ 	__be32 nanndcr;
+ 	u32 res22[0x2];
+ 	__be32 nand_autoboot_trgr;
+ 	u32 res23;
+ 	__be32 nand_mdr;
+-	u32 res24[0x5C];
+	u32 res24[0x1C];
+	__be32 nand_dll_lowcfg0;
+	__be32 nand_dll_lowcfg1;
+	u32 res25;
+	__be32 nand_dll_lowstat;
+	u32 res26[0x3c];
+ };
+ 
+ /*
+@@ -773,13 +783,12 @@ struct fsl_ifc_gpcm {
+ 	__be32 gpcm_erattr1;
+ 	__be32 gpcm_erattr2;
+ 	__be32 gpcm_stat;
+-	u32 res4[0x1F3];
+ };
+ 
+ /*
+  * IFC Controller Registers
+  */
+-struct fsl_ifc_regs {
+struct fsl_ifc_fcm {
+ 	__be32 ifc_rev;
+ 	u32 res1[0x2];
+ 	struct {
+@@ -805,21 +814,26 @@ struct fsl_ifc_regs {
+ 	} ftim_cs[FSL_IFC_BANK_COUNT];
+ 	u32 res9[0x30];
+ 	__be32 rb_stat;
+-	u32 res10[0x2];
+	__be32 rb_map;
+	__be32 wb_map;
+ 	__be32 ifc_gcr;
+-	u32 res11[0x2];
+	u32 res10[0x2];
+ 	__be32 cm_evter_stat;
+-	u32 res12[0x2];
+	u32 res11[0x2];
+ 	__be32 cm_evter_en;
+-	u32 res13[0x2];
+	u32 res12[0x2];
+ 	__be32 cm_evter_intr_en;
+-	u32 res14[0x2];
+	u32 res13[0x2];
+ 	__be32 cm_erattr0;
+ 	__be32 cm_erattr1;
+-	u32 res15[0x2];
+	u32 res14[0x2];
+ 	__be32 ifc_ccr;
+ 	__be32 ifc_csr;
+-	u32 res16[0x2EB];
+	__be32 ddr_ccr_low;
+};
+
+
+struct fsl_ifc_runtime {
+ 	struct fsl_ifc_nand ifc_nand;
+ 	struct fsl_ifc_nor ifc_nor;
+ 	struct fsl_ifc_gpcm ifc_gpcm;
+@@ -833,7 +847,8 @@ extern int fsl_ifc_find(phys_addr_t addr
+ struct fsl_ifc_ctrl {
+ 	/* device info */
+ 	struct device			*dev;
+-	struct fsl_ifc_regs __iomem	*regs;
+	struct fsl_ifc_fcm __iomem	*gregs;
+	struct fsl_ifc_runtime __iomem	*rregs;
+ 	int				irq;
+ 	int				nand_irq;
+ 	spinlock_t			lock;
+@@ -846,7 +861,8 @@ struct fsl_ifc_ctrl {
+ 	bool little_endian;
+ #ifdef CONFIG_PM_SLEEP
+ 	/*save regs when system goes to deep sleep*/
+-	struct fsl_ifc_regs		*saved_regs;
+	struct fsl_ifc_fcm		*saved_gregs;
+	struct fsl_ifc_runtime		*saved_rregs;
+ #endif
+ };
+ 
--- a/target/linux/layerscape/patches-4.4/4047-drivers-memory-Fix-build-error-for-arm64.patch
+++ b/target/linux/layerscape/patches-4.4/4047-drivers-memory-Fix-build-error-for-arm64.patch
@ -0,0 +1,53 @@
+From 0ce5d6bd62a9f1dbaa2d39c3535a8bdb31cf7951 Mon Sep 17 00:00:00 2001
+From: Raghav Dogra <raghav.dogra@nxp.com>
+Date: Wed, 24 Feb 2016 23:12:58 +0530
+Subject: [PATCH 47/70] drivers/memory: Fix build error for arm64
+
+Replace spin_event_timeout() with arch independent macro
+
+Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+---
+ drivers/memory/fsl_ifc.c |   16 +++++++++-------
+ 1 file changed, 9 insertions(+), 7 deletions(-)
+
+--- a/drivers/memory/fsl_ifc.c
+++ b/drivers/memory/fsl_ifc.c
+@@ -39,7 +39,7 @@
+ struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
+ EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
+ #define FSL_IFC_V1_3_0	0x01030000
+-#define IFC_TIMEOUT_MSECS	100000 /* 100ms */
+#define IFC_TIMEOUT_MSECS	1000 /* 1000ms */
+ 
+ /*
+  * convert_ifc_address - convert the base address
+@@ -365,7 +365,7 @@ static int fsl_ifc_resume(struct device
+ 	struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
+ 	struct fsl_ifc_fcm *savd_gregs = ctrl->saved_gregs;
+ 	struct fsl_ifc_runtime *savd_rregs = ctrl->saved_rregs;
+-	uint32_t ver = 0, ncfgr, status, ifc_bank, i;
+	uint32_t ver = 0, ncfgr, timeout, ifc_bank, i;
+ 
+ /*
+  * IFC interrupts disabled
+@@ -469,12 +469,14 @@ static int fsl_ifc_resume(struct device
+ 		ifc_out32(ncfgr | IFC_NAND_SRAM_INIT_EN,
+ 					&runtime->ifc_nand.ncfgr);
+ 		/* wait for  SRAM_INIT bit to be clear or timeout */
+-		status = spin_event_timeout(
+-					!(ifc_in32(&runtime->ifc_nand.ncfgr)
+-					& IFC_NAND_SRAM_INIT_EN),
+-					IFC_TIMEOUT_MSECS, 0);
+		timeout = 10;
+		while ((ifc_in32(&runtime->ifc_nand.ncfgr) &
+			IFC_NAND_SRAM_INIT_EN) && timeout) {
+			mdelay(IFC_TIMEOUT_MSECS);
+			timeout--;
+		}
+ 
+-		if (!status)
+		if (!timeout)
+ 			dev_err(ctrl->dev, "Timeout waiting for IFC SRAM INIT");
+ 	}
+ 
--- a/target/linux/layerscape/patches-4.4/7014-temp-QE-headers-are-needed-by-FMD.patch
+++ b/target/linux/layerscape/patches-4.4/7014-temp-QE-headers-are-needed-by-FMD.patch
--- a/target/linux/layerscape/patches-4.4/7015-fmd-add-fman-driver.patch
+++ b/target/linux/layerscape/patches-4.4/7015-fmd-add-fman-driver.patch
--- a/target/linux/layerscape/patches-4.4/7016-dpa-add-dpaa_eth-driver.patch
+++ b/target/linux/layerscape/patches-4.4/7016-dpa-add-dpaa_eth-driver.patch
--- a/target/linux/layerscape/patches-4.4/7017-fsl_qbman-add-qbman-driver.patch
+++ b/target/linux/layerscape/patches-4.4/7017-fsl_qbman-add-qbman-driver.patch
--- a/target/linux/layerscape/patches-4.4/7018-devres-add-devm_alloc_percpu.patch
+++ b/target/linux/layerscape/patches-4.4/7018-devres-add-devm_alloc_percpu.patch
@ -0,0 +1,138 @@
+From f7792176d939e79b4f525114a95d0fd8266bef8e Mon Sep 17 00:00:00 2001
+From: Madalin Bucur <madalin.bucur@freescale.com>
+Date: Wed, 19 Nov 2014 13:06:54 +0200
+Subject: [PATCH 18/70] devres: add devm_alloc_percpu()
+
+Introduce managed counterparts for alloc_percpu() and free_percpu().
+Add devm_alloc_percpu() and devm_free_percpu() into the managed
+interfaces list.
+
+Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com>
+
+Change-Id: I93546348e7b0e1974fda8b6c7a3b3710ce45b724
+Reviewed-on: http://git.am.freescale.net:8181/24140
+Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
+Tested-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
+
+Conflicts:
+	Documentation/driver-model/devres.txt
+	drivers/base/devres.c
+
+Conflicts:
+	drivers/base/devres.c
+---
+ Documentation/driver-model/devres.txt |    4 +++
+ drivers/base/devres.c                 |   63 +++++++++++++++++++++++++++++++++
+ include/linux/device.h                |   19 ++++++++++
+ 3 files changed, 86 insertions(+)
+
+--- a/Documentation/driver-model/devres.txt
+++ b/Documentation/driver-model/devres.txt
+@@ -321,6 +321,10 @@ PHY
+   devm_usb_get_phy()
+   devm_usb_put_phy()
+ 
+PER-CPU MEM
+  devm_alloc_percpu()
+  devm_free_percpu()
+
+ PINCTRL
+   devm_pinctrl_get()
+   devm_pinctrl_put()
+--- a/drivers/base/devres.c
+++ b/drivers/base/devres.c
+@@ -985,3 +985,66 @@ void devm_free_pages(struct device *dev,
+ 			       &devres));
+ }
+ EXPORT_SYMBOL_GPL(devm_free_pages);
+
+static void devm_percpu_release(struct device *dev, void *pdata)
+{
+	void __percpu *p;
+
+	p = *(void __percpu **)pdata;
+	free_percpu(p);
+}
+
+static int devm_percpu_match(struct device *dev, void *data, void *p)
+{
+	struct devres *devr = container_of(data, struct devres, data);
+
+	return *(void **)devr->data == p;
+}
+
+/**
+ * __devm_alloc_percpu - Resource-managed alloc_percpu
+ * @dev: Device to allocate per-cpu memory for
+ * @size: Size of per-cpu memory to allocate
+ * @align: Alignement of per-cpu memory to allocate
+ *
+ * Managed alloc_percpu. Per-cpu memory allocated with this function is
+ * automatically freed on driver detach.
+ *
+ * RETURNS:
+ * Pointer to allocated memory on success, NULL on failure.
+ */
+void __percpu *__devm_alloc_percpu(struct device *dev, size_t size,
+		size_t align)
+{
+	void *p;
+	void __percpu *pcpu;
+
+	pcpu = __alloc_percpu(size, align);
+	if (!pcpu)
+		return NULL;
+
+	p = devres_alloc(devm_percpu_release, sizeof(void *), GFP_KERNEL);
+	if (!p)
+		return NULL;
+
+	*(void __percpu **)p = pcpu;
+
+	devres_add(dev, p);
+
+	return pcpu;
+}
+EXPORT_SYMBOL_GPL(__devm_alloc_percpu);
+
+/**
+ * devm_free_percpu - Resource-managed free_percpu
+ * @dev: Device this memory belongs to
+ * @pdata: Per-cpu memory to free
+ *
+ * Free memory allocated with devm_alloc_percpu().
+ */
+void devm_free_percpu(struct device *dev, void __percpu *pdata)
+{
+	WARN_ON(devres_destroy(dev, devm_percpu_release, devm_percpu_match,
+			       (void *)pdata));
+}
+EXPORT_SYMBOL_GPL(devm_free_percpu);
+--- a/include/linux/device.h
+++ b/include/linux/device.h
+@@ -681,6 +681,25 @@ void __iomem *devm_ioremap_resource(stru
+ int devm_add_action(struct device *dev, void (*action)(void *), void *data);
+ void devm_remove_action(struct device *dev, void (*action)(void *), void *data);
+ 
+/**
+ * devm_alloc_percpu - Resource-managed alloc_percpu
+ * @dev: Device to allocate per-cpu memory for
+ * @type: Type to allocate per-cpu memory for
+ *
+ * Managed alloc_percpu. Per-cpu memory allocated with this function is
+ * automatically freed on driver detach.
+ *
+ * RETURNS:
+ * Pointer to allocated memory on success, NULL on failure.
+ */
+#define devm_alloc_percpu(dev, type)      \
+	(typeof(type) __percpu *)__devm_alloc_percpu(dev, sizeof(type), \
+						     __alignof__(type))
+
+void __percpu *__devm_alloc_percpu(struct device *dev, size_t size,
+				   size_t align);
+void devm_free_percpu(struct device *dev, void __percpu *pdata);
+
+ struct device_dma_parameters {
+ 	/*
+ 	 * a low level driver may set these to teach IOMMU code about
--- a/target/linux/layerscape/patches-4.4/7019-net-readd-skb_recycle.patch
+++ b/target/linux/layerscape/patches-4.4/7019-net-readd-skb_recycle.patch
@ -0,0 +1,59 @@
+From abc24ef7a69f54c3317beea98078831ba9bfa2cd Mon Sep 17 00:00:00 2001
+From: Madalin Bucur <madalin.bucur@freescale.com>
+Date: Tue, 5 Jan 2016 12:12:07 +0200
+Subject: [PATCH 19/70] net: readd skb_recycle()
+
+Adding back skb_recycle() as it's used by the DPAA Ethernet driver.
+This was removed from the upstream kernel because it was lacking users.
+
+Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com>
+---
+ include/linux/skbuff.h |    1 +
+ net/core/skbuff.c      |   26 ++++++++++++++++++++++++++
+ 2 files changed, 27 insertions(+)
+
+--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
+@@ -799,6 +799,7 @@ void kfree_skb(struct sk_buff *skb);
+ void kfree_skb_list(struct sk_buff *segs);
+ void skb_tx_error(struct sk_buff *skb);
+ void consume_skb(struct sk_buff *skb);
+void skb_recycle(struct sk_buff *skb);
+ void  __kfree_skb(struct sk_buff *skb);
+ extern struct kmem_cache *skbuff_head_cache;
+ 
+--- a/net/core/skbuff.c
+++ b/net/core/skbuff.c
+@@ -766,6 +766,32 @@ void consume_skb(struct sk_buff *skb)
+ }
+ EXPORT_SYMBOL(consume_skb);
+ 
+/**
+ * 	skb_recycle - clean up an skb for reuse
+ * 	@skb: buffer
+ *
+ * 	Recycles the skb to be reused as a receive buffer. This
+ * 	function does any necessary reference count dropping, and
+ * 	cleans up the skbuff as if it just came from __alloc_skb().
+ */
+void skb_recycle(struct sk_buff *skb)
+{
+	struct skb_shared_info *shinfo;
+	u8 head_frag = skb->head_frag;
+
+	skb_release_head_state(skb);
+
+	shinfo = skb_shinfo(skb);
+	memset(shinfo, 0, offsetof(struct skb_shared_info, dataref));
+	atomic_set(&shinfo->dataref, 1);
+
+	memset(skb, 0, offsetof(struct sk_buff, tail));
+	skb->data = skb->head + NET_SKB_PAD;
+	skb->head_frag = head_frag;
+	skb_reset_tail_pointer(skb);
+}
+EXPORT_SYMBOL(skb_recycle);
+
+ /* Make sure a field is enclosed inside headers_start/headers_end section */
+ #define CHECK_SKB_FIELD(field) \
+ 	BUILD_BUG_ON(offsetof(struct sk_buff, field) <		\
--- a/target/linux/layerscape/patches-4.4/7020-net-add-custom-NETIF-flags.patch
+++ b/target/linux/layerscape/patches-4.4/7020-net-add-custom-NETIF-flags.patch
@ -0,0 +1,40 @@
+From 608986fc6b41633753701d5df9c1ab6a13856608 Mon Sep 17 00:00:00 2001
+From: Madalin Bucur <madalin.bucur@freescale.com>
+Date: Mon, 11 Jul 2016 14:14:15 +0800
+Subject: [PATCH 20/70] net: add custom NETIF flags
+
+commit 6a53650c0c4513429d91e6ad7253340f3d3b9da5
+[context adjustment]
+
+These flags are used by DPAA Ethernet to impose different behaviors
+in the networking stack.
+
+Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
+Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com>
+Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
+---
+ include/linux/netdev_features.h |    6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/include/linux/netdev_features.h
+++ b/include/linux/netdev_features.h
+@@ -66,6 +66,9 @@ enum {
+ 	NETIF_F_HW_VLAN_STAG_FILTER_BIT,/* Receive filtering on VLAN STAGs */
+ 	NETIF_F_HW_L2FW_DOFFLOAD_BIT,	/* Allow L2 Forwarding in Hardware */
+ 	NETIF_F_BUSY_POLL_BIT,		/* Busy poll */
+	/* Freescale DPA support */
+	NETIF_F_HW_QDISC_BIT,           /* Supports hardware Qdisc */
+	NETIF_F_HW_ACCEL_MQ_BIT,        /* Hardware-accelerated multiqueue */
+ 
+ 	/*
+ 	 * Add your fresh new feature above and remember to update
+@@ -124,6 +127,9 @@ enum {
+ #define NETIF_F_HW_VLAN_STAG_TX	__NETIF_F(HW_VLAN_STAG_TX)
+ #define NETIF_F_HW_L2FW_DOFFLOAD	__NETIF_F(HW_L2FW_DOFFLOAD)
+ #define NETIF_F_BUSY_POLL	__NETIF_F(BUSY_POLL)
+/* Freescale DPA support */
+#define NETIF_F_HW_QDISC       __NETIF_F(HW_QDISC)
+#define NETIF_F_HW_ACCEL_MQ    __NETIF_F(HW_ACCEL_MQ)
+ 
+ #define for_each_netdev_feature(mask_addr, bit)	\
+ 	for_each_set_bit(bit, (unsigned long *)mask_addr, NETDEV_FEATURE_COUNT)
--- a/target/linux/layerscape/patches-4.4/7021-net-Make-the-netdev-watchdog-aware-of-hardware-multi.patch
+++ b/target/linux/layerscape/patches-4.4/7021-net-Make-the-netdev-watchdog-aware-of-hardware-multi.patch
@ -0,0 +1,48 @@
+From 6aa1eca98ca44f515e10d8058d0ff6db3c8a3c11 Mon Sep 17 00:00:00 2001
+From: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
+Date: Fri, 28 Sep 2012 17:04:33 +0300
+Subject: [PATCH 21/70] net: Make the netdev watchdog aware of hardware
+ multiqueue devices
+
+If the netdev declares the NETIF_F_HW_ACCEL_MQ (accelerated multiqueue)
+capability, tell the watchdog to consider the per-netdev trans_start
+field rather than any individual multiqueue's timestamp. That is
+justified by the fact that queues only go in and out of congestion
+in groups, not individually, as far as the net device is concerned.
+
+Change-Id: I07a6693bf1f0bb1e9396c5e232452223a511ecc1
+Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com>
+Reviewed-on: http://git.am.freescale.net:8181/1033
+Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
+Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
+---
+ net/sched/sch_generic.c |   17 ++++++++++++++++-
+ 1 file changed, 16 insertions(+), 1 deletion(-)
+
+--- a/net/sched/sch_generic.c
+++ b/net/sched/sch_generic.c
+@@ -290,8 +290,23 @@ static void dev_watchdog(unsigned long a
+ 				txq = netdev_get_tx_queue(dev, i);
+ 				/*
+ 				 * old device drivers set dev->trans_start
+				 *
+				 * (Actually, not only "old" devices, but also
+				 * those which perform queue management in a
+				 * separate hw accelerator. So even though the
+				 * net device itself is single-queued, it makes
+				 * sense (and is safe, too) to use kernel's
+				 * multiqueue interface, specifically to avoid
+				 * unnecessary device locking in SMP systems.
+				 * In this case, we ought to consider not an
+				 * individual txq's timestamp as a congestion
+				 * indicator, but the "old" per-netdev field.)
+ 				 */
+-				trans_start = txq->trans_start ? : dev->trans_start;
+				if (dev->features & NETIF_F_HW_ACCEL_MQ)
+					trans_start = dev->trans_start;
+				else
+					trans_start = txq->trans_start ? :
+						dev->trans_start;
+ 				if (netif_xmit_stopped(txq) &&
+ 				    time_after(jiffies, (trans_start +
+ 							 dev->watchdog_timeo))) {
--- a/target/linux/layerscape/patches-4.4/7024-Add-APIs-to-setup-HugeTLB-mappings-for-USDPAA.patch
+++ b/target/linux/layerscape/patches-4.4/7024-Add-APIs-to-setup-HugeTLB-mappings-for-USDPAA.patch
@ -0,0 +1,59 @@
+From 2dcd28f7b4f5b92686da45f4ec46802026fb8573 Mon Sep 17 00:00:00 2001
+From: Roy Pledge <Roy.Pledge@freescale.com>
+Date: Mon, 11 Jul 2016 14:34:59 +0800
+Subject: [PATCH 24/70] Add APIs to setup HugeTLB mappings for USDPAA
+
+commit 189653d40d5dc41b8bd4cfb61f766bd8a89b1e34
+[context adjustment]
+
+Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
+---
+ arch/powerpc/mm/fsl_booke_mmu.c |   14 +++++++++++++-
+ arch/powerpc/mm/mmu_decl.h      |    6 ++++++
+ 2 files changed, 19 insertions(+), 1 deletion(-)
+
+--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
+@@ -105,7 +105,7 @@ unsigned long p_mapped_by_tlbcam(phys_ad
+  * an unsigned long (for example, 32-bit implementations cannot support a 4GB
+  * size).
+  */
+-static void settlbcam(int index, unsigned long virt, phys_addr_t phys,
+void settlbcam(int index, unsigned long virt, phys_addr_t phys,
+ 		unsigned long size, unsigned long flags, unsigned int pid)
+ {
+ 	unsigned int tsize;
+@@ -143,6 +143,18 @@ static void settlbcam(int index, unsigne
+ 	tlbcam_addrs[index].phys = phys;
+ }
+ 
+void cleartlbcam(unsigned long virt, unsigned int pid)
+{
+        int i = 0;
+        for (i = 0; i < NUM_TLBCAMS; i++) {
+                if (tlbcam_addrs[i].start == virt) {
+                        TLBCAM[i].MAS1 = 0;
+                        loadcam_entry(i);
+                        return;
+                }
+        }
+}
+
+ unsigned long calc_cam_sz(unsigned long ram, unsigned long virt,
+ 			  phys_addr_t phys)
+ {
+--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
+@@ -91,6 +91,12 @@ extern void _tlbia(void);
+ 
+ #endif /* CONFIG_PPC_MMU_NOHASH */
+ 
+void settlbcam(int index, unsigned long virt, phys_addr_t phys,
+               unsigned long size, unsigned long flags, unsigned int pid);
+
+void cleartlbcam(unsigned long virt, unsigned int pid);
+
+
+ #ifdef CONFIG_PPC32
+ 
+ extern void mapin_ram(void);
--- a/target/linux/layerscape/patches-4.4/7029-fmd-SGMII-PCS-needs-to-be-reprogrammed-after-sleep.patch
+++ b/target/linux/layerscape/patches-4.4/7029-fmd-SGMII-PCS-needs-to-be-reprogrammed-after-sleep.patch
@ -0,0 +1,228 @@
+From afcfdda960da9d9ad4c4d21c7dd0cc7791cf36c7 Mon Sep 17 00:00:00 2001
+From: Madalin Bucur <madalin.bucur@freescale.com>
+Date: Wed, 4 May 2016 19:24:53 +0300
+Subject: [PATCH 29/70] fmd: SGMII PCS needs to be reprogrammed after sleep
+
+Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com>
+---
+ drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth.c |    6 ++
+ .../freescale/sdk_fman/Peripherals/FM/MAC/dtsec.c  |    1 +
+ .../freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.c |   12 ++++
+ .../freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.h |    1 +
+ .../freescale/sdk_fman/Peripherals/FM/MAC/memac.c  |   58 +++++++++++---------
+ .../freescale/sdk_fman/Peripherals/FM/MAC/tgec.c   |    1 +
+ .../sdk_fman/inc/Peripherals/fm_mac_ext.h          |   13 +++++
+ .../sdk_fman/src/inc/wrapper/lnxwrp_fsl_fman.h     |    2 +
+ .../freescale/sdk_fman/src/wrapper/lnxwrp_fm.c     |   14 +++++
+ 9 files changed, 83 insertions(+), 25 deletions(-)
+
+--- a/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth.c
+++ b/drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth.c
+@@ -175,6 +175,12 @@ static int dpaa_resume(struct device *de
+ 		priv = netdev_priv(net_dev);
+ 		mac_dev = priv->mac_dev;
+ 
+		err = fm_mac_resume(mac_dev->get_mac_handle(mac_dev));
+		if (err) {
+			netdev_err(net_dev, "fm_mac_resume = %d\n", err);
+			goto resume_failed;
+		}
+
+ 		err = fm_port_resume(mac_dev->port_dev[TX]);
+ 		if (err) {
+ 			netdev_err(net_dev, "fm_port_resume(TX) = %d\n", err);
+--- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec.c
+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/dtsec.c
+@@ -1371,6 +1371,7 @@ static void InitFmMacControllerDriver(t_
+ 
+     p_FmMacControllerDriver->f_FM_MAC_Enable                    = DtsecEnable;
+     p_FmMacControllerDriver->f_FM_MAC_Disable                   = DtsecDisable;
+    p_FmMacControllerDriver->f_FM_MAC_Resume                    = NULL;
+ 
+     p_FmMacControllerDriver->f_FM_MAC_SetException              = DtsecSetException;
+ 
+--- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.c
+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.c
+@@ -299,6 +299,18 @@ t_Error FM_MAC_Disable (t_Handle h_FmMac
+     RETURN_ERROR(MINOR, E_NOT_SUPPORTED, NO_MSG);
+ }
+ 
+t_Error FM_MAC_Resume (t_Handle h_FmMac)
+{
+    t_FmMacControllerDriver *p_FmMacControllerDriver = (t_FmMacControllerDriver *)h_FmMac;
+
+    SANITY_CHECK_RETURN_ERROR(p_FmMacControllerDriver, E_INVALID_HANDLE);
+
+    if (p_FmMacControllerDriver->f_FM_MAC_Resume)
+        return p_FmMacControllerDriver->f_FM_MAC_Resume(h_FmMac);
+
+    return E_OK;
+}
+
+ /* ......................................................................... */
+ 
+ t_Error FM_MAC_Enable1588TimeStamp (t_Handle h_FmMac)
+--- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.h
+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/fm_mac.h
+@@ -91,6 +91,7 @@ typedef struct {
+ 
+     t_Error (*f_FM_MAC_Enable)  (t_Handle h_FmMac,  e_CommMode mode);
+     t_Error (*f_FM_MAC_Disable) (t_Handle h_FmMac, e_CommMode mode);
+    t_Error (*f_FM_MAC_Resume)  (t_Handle h_FmMac);
+     t_Error (*f_FM_MAC_Enable1588TimeStamp) (t_Handle h_FmMac);
+     t_Error (*f_FM_MAC_Disable1588TimeStamp) (t_Handle h_FmMac);
+     t_Error (*f_FM_MAC_Reset)   (t_Handle h_FmMac, bool wait);
+--- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.c
+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/memac.c
+@@ -812,6 +812,37 @@ static uint16_t MemacGetMaxFrameLength(t
+     return fman_memac_get_max_frame_len(p_Memac->p_MemMap);
+ }
+ 
+static t_Error MemacInitInternalPhy(t_Handle h_Memac)
+{
+    t_Memac *p_Memac = (t_Memac *)h_Memac;
+    uint8_t i, phyAddr;
+
+    if (ENET_INTERFACE_FROM_MODE(p_Memac->enetMode) == e_ENET_IF_SGMII)
+    {
+        /* Configure internal SGMII PHY */
+        if (p_Memac->enetMode & ENET_IF_SGMII_BASEX)
+            SetupSgmiiInternalPhyBaseX(p_Memac, PHY_MDIO_ADDR);
+        else
+            SetupSgmiiInternalPhy(p_Memac, PHY_MDIO_ADDR);
+    }
+    else if (ENET_INTERFACE_FROM_MODE(p_Memac->enetMode) == e_ENET_IF_QSGMII)
+    {
+        /* Configure 4 internal SGMII PHYs */
+        for (i = 0; i < 4; i++)
+        {
+            /* QSGMII PHY address occupies 3 upper bits of 5-bit
+               phyAddress; the lower 2 bits are used to extend
+               register address space and access each one of 4
+               ports inside QSGMII. */
+            phyAddr = (uint8_t)((PHY_MDIO_ADDR << 2) | i);
+            if (p_Memac->enetMode & ENET_IF_SGMII_BASEX)
+                SetupSgmiiInternalPhyBaseX(p_Memac, phyAddr);
+            else
+                SetupSgmiiInternalPhy(p_Memac, phyAddr);
+        }
+    }
+    return E_OK;
+}
+ 
+ /*****************************************************************************/
+ /*                      mEMAC Init & Free API                                   */
+@@ -825,7 +856,6 @@ static t_Error MemacInit(t_Handle h_Mema
+     struct memac_cfg        *p_MemacDriverParam;
+     enum enet_interface     enet_interface;
+     enum enet_speed         enet_speed;
+-    uint8_t                 i, phyAddr;
+     t_EnetAddr              ethAddr;
+     e_FmMacType             portType;
+     t_Error                 err;
+@@ -887,30 +917,7 @@ static t_Error MemacInit(t_Handle h_Mema
+     }
+ #endif /* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 */
+ 
+-    if (ENET_INTERFACE_FROM_MODE(p_Memac->enetMode) == e_ENET_IF_SGMII)
+-    {
+-        /* Configure internal SGMII PHY */
+-        if (p_Memac->enetMode & ENET_IF_SGMII_BASEX)
+-            SetupSgmiiInternalPhyBaseX(p_Memac, PHY_MDIO_ADDR);
+-        else
+-            SetupSgmiiInternalPhy(p_Memac, PHY_MDIO_ADDR);
+-    }
+-    else if (ENET_INTERFACE_FROM_MODE(p_Memac->enetMode) == e_ENET_IF_QSGMII)
+-    {
+-        /* Configure 4 internal SGMII PHYs */
+-        for (i = 0; i < 4; i++)
+-        {
+-            /* QSGMII PHY address occupies 3 upper bits of 5-bit
+-               phyAddress; the lower 2 bits are used to extend
+-               register address space and access each one of 4
+-               ports inside QSGMII. */
+-            phyAddr = (uint8_t)((PHY_MDIO_ADDR << 2) | i);
+-            if (p_Memac->enetMode & ENET_IF_SGMII_BASEX)
+-                SetupSgmiiInternalPhyBaseX(p_Memac, phyAddr);
+-            else
+-                SetupSgmiiInternalPhy(p_Memac, phyAddr);
+-        }
+-    }
+    MemacInitInternalPhy(h_Memac);
+ 
+     /* Max Frame Length */
+     err = FmSetMacMaxFrame(p_Memac->fmMacControllerDriver.h_Fm,
+@@ -1008,6 +1015,7 @@ static void InitFmMacControllerDriver(t_
+ 
+     p_FmMacControllerDriver->f_FM_MAC_Enable                    = MemacEnable;
+     p_FmMacControllerDriver->f_FM_MAC_Disable                   = MemacDisable;
+    p_FmMacControllerDriver->f_FM_MAC_Resume                    = MemacInitInternalPhy;
+ 
+     p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames      = MemacSetTxAutoPauseFrames;
+     p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames          = MemacSetTxPauseFrames;
+--- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec.c
+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/MAC/tgec.c
+@@ -897,6 +897,7 @@ static void InitFmMacControllerDriver(t_
+ 
+     p_FmMacControllerDriver->f_FM_MAC_Enable                    = TgecEnable;
+     p_FmMacControllerDriver->f_FM_MAC_Disable                   = TgecDisable;
+    p_FmMacControllerDriver->f_FM_MAC_Resume                    = NULL;
+ 
+     p_FmMacControllerDriver->f_FM_MAC_SetTxAutoPauseFrames      = TgecTxMacPause;
+     p_FmMacControllerDriver->f_FM_MAC_SetTxPauseFrames          = TgecSetTxPauseFrames;
+--- a/drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_mac_ext.h
+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/Peripherals/fm_mac_ext.h
+@@ -467,6 +467,19 @@ t_Error FM_MAC_Enable(t_Handle h_FmMac,
+ t_Error FM_MAC_Disable(t_Handle h_FmMac, e_CommMode mode);
+ 
+ /**************************************************************************//**
+ @Function      FM_MAC_Resume
+
+ @Description   Re-init the MAC after suspend
+
+ @Param[in]     h_FmMac    A handle to a FM MAC Module.
+
+ @Return        E_OK on success; Error code otherwise.
+
+ @Cautions      Allowed only following FM_MAC_Init().
+*//***************************************************************************/
+t_Error FM_MAC_Resume(t_Handle h_FmMac);
+
+/**************************************************************************//**
+  @Function      FM_MAC_Enable1588TimeStamp
+ 
+  @Description   Enables the TSU operation.
+--- a/drivers/net/ethernet/freescale/sdk_fman/src/inc/wrapper/lnxwrp_fsl_fman.h
+++ b/drivers/net/ethernet/freescale/sdk_fman/src/inc/wrapper/lnxwrp_fsl_fman.h
+@@ -765,6 +765,8 @@ int fm_mac_enable(struct fm_mac_dev *fm_
+ 
+ int fm_mac_disable(struct fm_mac_dev *fm_mac_dev);
+ 
+int fm_mac_resume(struct fm_mac_dev *fm_mac_dev);
+
+ int fm_mac_set_promiscuous(struct fm_mac_dev *fm_mac_dev,
+ 		bool enable);
+ 
+--- a/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_fm.c
+++ b/drivers/net/ethernet/freescale/sdk_fman/src/wrapper/lnxwrp_fm.c
+@@ -1733,6 +1733,20 @@ int fm_mac_disable(struct fm_mac_dev *fm
+ }
+ EXPORT_SYMBOL(fm_mac_disable);
+ 
+int fm_mac_resume(struct fm_mac_dev *fm_mac_dev)
+{
+        int      _errno;
+        t_Error  err;
+
+        err = FM_MAC_Resume(fm_mac_dev);
+        _errno = -GET_ERROR_TYPE(err);
+        if (unlikely(_errno < 0))
+                pr_err("FM_MAC_Resume() = 0x%08x\n", err);
+
+        return _errno;
+}
+EXPORT_SYMBOL(fm_mac_resume);
+
+ int fm_mac_set_promiscuous(struct fm_mac_dev *fm_mac_dev,
+ 		bool enable)
+ {
--- a/target/linux/layerscape/patches-4.4/7030-fmd-use-kernel-api-for-64bit-division.patch
+++ b/target/linux/layerscape/patches-4.4/7030-fmd-use-kernel-api-for-64bit-division.patch
@ -0,0 +1,178 @@
+From c86be7b4f9ca4f4c8c916a9c350edbcd0e86a528 Mon Sep 17 00:00:00 2001
+From: Madalin Bucur <madalin.bucur@freescale.com>
+Date: Mon, 18 Apr 2016 16:41:59 +0300
+Subject: [PATCH 30/70] fmd: use kernel api for 64bit division
+
+Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com>
+---
+ .../freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.c  |    1 +
+ .../sdk_fman/Peripherals/FM/Pcd/fm_plcr.c          |    5 +++--
+ .../freescale/sdk_fman/Peripherals/FM/Pcd/fm_prs.c |    1 +
+ .../freescale/sdk_fman/Peripherals/FM/Rtc/fm_rtc.c |   12 ++++++------
+ .../freescale/sdk_fman/Peripherals/FM/fm.c         |    5 +++--
+ .../freescale/sdk_fman/Peripherals/FM/fman.c       |    7 +++----
+ .../net/ethernet/freescale/sdk_fman/inc/math_ext.h |    1 +
+ .../net/ethernet/freescale/sdk_fman/inc/ncsw_ext.h |    2 +-
+ 8 files changed, 19 insertions(+), 15 deletions(-)
+
+--- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.c
+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_cc.c
+@@ -36,6 +36,7 @@
+ 
+  @Description   FM Coarse Classifier implementation
+  *//***************************************************************************/
+#include <linux/math64.h>
+ #include "std_ext.h"
+ #include "error_ext.h"
+ #include "string_ext.h"
+--- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_plcr.c
+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_plcr.c
+@@ -36,6 +36,7 @@
+ 
+  @Description   FM PCD POLICER...
+ *//***************************************************************************/
+#include <linux/math64.h>
+ #include "std_ext.h"
+ #include "error_ext.h"
+ #include "string_ext.h"
+@@ -205,13 +206,13 @@ static void GetInfoRateReg(e_FmPcdPlcrRa
+         div = 1000000000;   /* nano */
+         div *= 10;          /* 10 nano */
+     }
+-    *p_Integer = (tmp<<fppShift)/div;
+    *p_Integer = div64_u64(tmp<<fppShift, div);
+ 
+     /* for calculating the fraction, we will recalculate cir and deduct the integer.
+      * For precision, we will multiply by 2^16. we do not divid back, since we write
+      * this value as fraction - see spec.
+      */
+-    *p_Fraction = (((tmp<<fppShift)<<16) - ((*p_Integer<<16)*div))/div;
+    *p_Fraction = div64_u64(((tmp<<fppShift)<<16) - ((*p_Integer<<16)*div), div);
+ }
+ 
+ /* .......... */
+--- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_prs.c
+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Pcd/fm_prs.c
+@@ -36,6 +36,7 @@
+ 
+  @Description   FM PCD ...
+ *//***************************************************************************/
+#include <linux/math64.h>
+ #include "std_ext.h"
+ #include "error_ext.h"
+ #include "string_ext.h"
+--- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Rtc/fm_rtc.c
+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/Rtc/fm_rtc.c
+@@ -38,7 +38,7 @@
+ 
+  @Cautions      None
+ *//***************************************************************************/
+-
+#include <linux/math64.h>
+ #include "error_ext.h"
+ #include "debug_ext.h"
+ #include "string_ext.h"
+@@ -470,11 +470,11 @@ t_Error FM_RTC_SetAlarm(t_Handle h_FmRtc
+         RETURN_ERROR(MAJOR, E_INVALID_SELECTION,
+                      ("Alarm time must be equal or larger than RTC period - %d nanoseconds",
+                       p_Rtc->clockPeriodNanoSec));
+-    if (p_FmRtcAlarmParams->alarmTime % (uint64_t)p_Rtc->clockPeriodNanoSec)
+    tmpAlarm = p_FmRtcAlarmParams->alarmTime;
+    if (do_div(tmpAlarm, p_Rtc->clockPeriodNanoSec))
+         RETURN_ERROR(MAJOR, E_INVALID_SELECTION,
+                      ("Alarm time must be a multiple of RTC period - %d nanoseconds",
+                       p_Rtc->clockPeriodNanoSec));
+-    tmpAlarm = p_FmRtcAlarmParams->alarmTime/(uint64_t)p_Rtc->clockPeriodNanoSec;
+ 
+     if (p_FmRtcAlarmParams->f_AlarmCallback)
+     {
+@@ -508,11 +508,11 @@ t_Error FM_RTC_SetPeriodicPulse(t_Handle
+         RETURN_ERROR(MAJOR, E_INVALID_SELECTION,
+                      ("Periodic pulse must be equal or larger than RTC period - %d nanoseconds",
+                       p_Rtc->clockPeriodNanoSec));
+-    if (p_FmRtcPeriodicPulseParams->periodicPulsePeriod % (uint64_t)p_Rtc->clockPeriodNanoSec)
+    tmpFiper = p_FmRtcPeriodicPulseParams->periodicPulsePeriod;
+    if (do_div(tmpFiper, p_Rtc->clockPeriodNanoSec))
+         RETURN_ERROR(MAJOR, E_INVALID_SELECTION,
+                      ("Periodic pulse must be a multiple of RTC period - %d nanoseconds",
+                       p_Rtc->clockPeriodNanoSec));
+-    tmpFiper = p_FmRtcPeriodicPulseParams->periodicPulsePeriod/(uint64_t)p_Rtc->clockPeriodNanoSec;
+     if (tmpFiper & 0xffffffff00000000LL)
+         RETURN_ERROR(MAJOR, E_INVALID_SELECTION,
+                      ("Periodic pulse/RTC Period must be smaller than 4294967296",
+@@ -628,7 +628,7 @@ t_Error FM_RTC_SetCurrentTime(t_Handle h
+     SANITY_CHECK_RETURN_ERROR(p_Rtc, E_INVALID_HANDLE);
+     SANITY_CHECK_RETURN_ERROR(!p_Rtc->p_RtcDriverParam, E_INVALID_STATE);
+ 
+-    ts = ts/p_Rtc->clockPeriodNanoSec;
+    do_div(ts, p_Rtc->clockPeriodNanoSec);
+     fman_rtc_set_timer(p_Rtc->p_MemMap, (int64_t)ts);
+ 
+     return E_OK;
+--- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fm.c
+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fm.c
+@@ -43,6 +43,7 @@
+ #include "sprint_ext.h"
+ #include "debug_ext.h"
+ #include "fm_muram_ext.h"
+#include <linux/math64.h>
+ 
+ #include "fm_common.h"
+ #include "fm_ipc.h"
+@@ -5087,9 +5088,9 @@ t_Error FM_CtrlMonGetCounters(t_Handle h
+     effValue = (uint64_t)
+             ((uint64_t)GET_UINT32(p_MonRegs->tpc2h) << 32 | GET_UINT32(p_MonRegs->tpc2l));
+ 
+-    p_Mon->percentCnt[0] = (uint8_t)((clkCnt - utilValue) * 100 / clkCnt);
+    p_Mon->percentCnt[0] = (uint8_t)div64_u64((clkCnt - utilValue) * 100, clkCnt);
+     if (clkCnt != utilValue)
+-        p_Mon->percentCnt[1] = (uint8_t)(((clkCnt - utilValue) - effValue) * 100 / (clkCnt - utilValue));
+        p_Mon->percentCnt[1] = (uint8_t)div64_u64(((clkCnt - utilValue) - effValue) * 100, clkCnt - utilValue);
+     else
+         p_Mon->percentCnt[1] = 0;
+ 
+--- a/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fman.c
+++ b/drivers/net/ethernet/freescale/sdk_fman/Peripherals/FM/fman.c
+@@ -31,7 +31,7 @@
+  */
+ 
+ 
+-
+#include <linux/math64.h>
+ #include "fsl_fman.h"
+ #include "dpaa_integration_ext.h"
+ 
+@@ -186,10 +186,9 @@ void fman_enable_time_stamp(struct fman_
+ 	 * we do not div back, since we write this value as a fraction
+ 	 * see spec */
+ 
+-	frac = (((uint64_t)ts_freq << 16) - ((uint64_t)intgr << 16) * fm_clk_freq)
+-		/ fm_clk_freq;
+	frac = ((uint64_t)ts_freq << 16) - ((uint64_t)intgr << 16) * fm_clk_freq;
+ 	/* we check remainder of the division in order to round up if not int */
+-	if (((ts_freq << 16) - (intgr << 16)*fm_clk_freq) % fm_clk_freq)
+	if (do_div(frac, fm_clk_freq))
+ 		frac++;
+ 
+ 	tmp = (intgr << FPM_TS_INT_SHIFT) | (uint16_t)frac;
+--- a/drivers/net/ethernet/freescale/sdk_fman/inc/math_ext.h
+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/math_ext.h
+@@ -37,6 +37,7 @@
+ 
+ #if defined(NCSW_LINUX) && defined(__KERNEL__)
+ #include <linux/math.h>
+#include <linux/math64.h>
+ 
+ #elif defined(__MWERKS__)
+ #define LOW(x) ( sizeof(x)==8 ? *(1+(int32_t*)&x) : (*(int32_t*)&x))
+--- a/drivers/net/ethernet/freescale/sdk_fman/inc/ncsw_ext.h
+++ b/drivers/net/ethernet/freescale/sdk_fman/inc/ncsw_ext.h
+@@ -142,7 +142,7 @@ do
+ } while (0)
+ 
+ /* Ceiling division - not the fastest way, but safer in terms of overflow */
+-#define DIV_CEIL(x,y)   (((x)/(y)) + ((((((x)/(y)))*(y)) == (x)) ? 0 : 1))
+#define DIV_CEIL(x,y) (div64_u64((x),(y)) + (((div64_u64((x),(y))*(y)) == (x)) ? 0 : 1))
+ 
+ /* Round up a number to be a multiple of a second number */
+ #define ROUND_UP(x,y)   ((((x) + (y) - 1) / (y)) * (y))
--- a/target/linux/layerscape/patches-4.4/7031-fsl_qbman-Enable-DPAA1-QBMan-for-ARM64-platforms.patch
+++ b/target/linux/layerscape/patches-4.4/7031-fsl_qbman-Enable-DPAA1-QBMan-for-ARM64-platforms.patch
@ -0,0 +1,31 @@
+From d0a7d97bdfb7a755d55bb53725d71f81aab90fe7 Mon Sep 17 00:00:00 2001
+From: Roy Pledge <Roy.Pledge@freescale.com>
+Date: Thu, 14 Apr 2016 10:21:02 +0800
+Subject: [PATCH 31/70] fsl_qbman: Enable DPAA1 QBMan for ARM64 platforms
+
+commit ddb0ae0f9d638efc70402d4fb570bca3a3178091
+[context adjustment]
+
+Enable the QBMan device for ARM64 platofrms.  This is needed for
+ARM based SoCs that have DPAA1 such as the LS1043A
+
+Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com>
+Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
+---
+ arch/arm64/Kconfig |    5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
+@@ -187,6 +187,11 @@ source "arch/arm64/Kconfig.platforms"
+ 
+ menu "Bus support"
+ 
+config HAS_FSL_QBMAN
+        bool "Datapath Acceleration Queue and Buffer management"
+        help
+          Datapath Acceleration Queue and Buffer management
+
+ config PCI
+ 	bool "PCI support"
+ 	help
--- a/target/linux/layerscape/patches-4.4/7064-dpaa_eth-repair-issue-introduced-with-2.5G-support.patch
+++ b/target/linux/layerscape/patches-4.4/7064-dpaa_eth-repair-issue-introduced-with-2.5G-support.patch
@ -0,0 +1,22 @@
+From e555d24e5df9b2d5b8a613ff46af68fc3ff3a360 Mon Sep 17 00:00:00 2001
+From: Madalin Bucur <madalin.bucur@freescale.com>
+Date: Wed, 30 Mar 2016 16:12:33 +0300
+Subject: [PATCH 64/70] dpaa_eth: repair issue introduced with 2.5G support
+
+Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com>
+---
+ drivers/net/ethernet/freescale/sdk_dpaa/mac.c |    3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/freescale/sdk_dpaa/mac.c
+++ b/drivers/net/ethernet/freescale/sdk_dpaa/mac.c
+@@ -346,7 +346,8 @@ static int __cold mac_probe(struct platf
+ 					SUPPORTED_100baseT_Half);
+ 
+ 	/* Gigabit support (no half-duplex) */
+-	if (mac_dev->max_speed == 1000)
+	if (mac_dev->max_speed == SPEED_1000 ||
+	    mac_dev->max_speed == SPEED_2500)
+ 		mac_dev->if_support |= SUPPORTED_1000baseT_Full;
+ 
+ 	/* The 10G interface only supports one mode */
--- a/target/linux/layerscape/patches-4.4/7065-dpaa_eth-replace-sgmii-2500-with-qsgmii.patch
+++ b/target/linux/layerscape/patches-4.4/7065-dpaa_eth-replace-sgmii-2500-with-qsgmii.patch
@ -0,0 +1,39 @@
+From a768af05b1ffe644f54303036e5c048952e0f721 Mon Sep 17 00:00:00 2001
+From: Madalin Bucur <madalin.bucur@freescale.com>
+Date: Mon, 4 Apr 2016 20:23:21 +0300
+Subject: [PATCH 65/70] dpaa_eth: replace sgmii-2500 with qsgmii
+
+Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com>
+---
+ drivers/net/ethernet/freescale/sdk_dpaa/mac.c |    6 ------
+ 1 file changed, 6 deletions(-)
+
+--- a/drivers/net/ethernet/freescale/sdk_dpaa/mac.c
+++ b/drivers/net/ethernet/freescale/sdk_dpaa/mac.c
+@@ -74,7 +74,6 @@ static const char phy_str[][11] = {
+ 	[PHY_INTERFACE_MODE_RGMII_TXID]	= "rgmii-txid",
+ 	[PHY_INTERFACE_MODE_RTBI]	= "rtbi",
+ 	[PHY_INTERFACE_MODE_XGMII]	= "xgmii",
+-	[PHY_INTERFACE_MODE_QSGMII]	= "sgmii-2500"
+ };
+ 
+ static phy_interface_t __pure __attribute__((nonnull)) str2phy(const char *str)
+@@ -101,7 +100,6 @@ static const uint16_t phy2speed[] = {
+ 	[PHY_INTERFACE_MODE_RGMII_TXID]	= SPEED_1000,
+ 	[PHY_INTERFACE_MODE_RTBI]	= SPEED_1000,
+ 	[PHY_INTERFACE_MODE_XGMII]	= SPEED_10000,
+-	[PHY_INTERFACE_MODE_QSGMII]	= SPEED_2500
+ };
+ 
+ static struct mac_device * __cold
+@@ -341,10 +339,6 @@ static int __cold mac_probe(struct platf
+ 		mac_dev->if_support &= ~(SUPPORTED_10baseT_Half |
+ 					SUPPORTED_100baseT_Half);
+ 
+-	if (strstr(char_prop, "sgmii-2500"))
+-		mac_dev->if_support &= ~(SUPPORTED_10baseT_Half |
+-					SUPPORTED_100baseT_Half);
+-
+ 	/* Gigabit support (no half-duplex) */
+ 	if (mac_dev->max_speed == SPEED_1000 ||
+ 	    mac_dev->max_speed == SPEED_2500)
--- a/target/linux/layerscape/patches-4.4/7066-fmd-add-2.5G-SGMII-mode-suport.patch
+++ b/target/linux/layerscape/patches-4.4/7066-fmd-add-2.5G-SGMII-mode-suport.patch
@ -0,0 +1,38 @@
+From 95d12688fa875f7a00590aaf6de5f34d55531d68 Mon Sep 17 00:00:00 2001
+From: Madalin Bucur <madalin.bucur@freescale.com>
+Date: Thu, 14 Apr 2016 14:12:38 +0300
+Subject: [PATCH 66/70] fmd: add 2.5G SGMII mode suport
+
+Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com>
+---
+ drivers/net/ethernet/freescale/sdk_dpaa/mac.c |    5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/freescale/sdk_dpaa/mac.c
+++ b/drivers/net/ethernet/freescale/sdk_dpaa/mac.c
+@@ -74,6 +74,7 @@ static const char phy_str[][11] = {
+ 	[PHY_INTERFACE_MODE_RGMII_TXID]	= "rgmii-txid",
+ 	[PHY_INTERFACE_MODE_RTBI]	= "rtbi",
+ 	[PHY_INTERFACE_MODE_XGMII]	= "xgmii",
+	[PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500",
+ };
+ 
+ static phy_interface_t __pure __attribute__((nonnull)) str2phy(const char *str)
+@@ -100,6 +101,7 @@ static const uint16_t phy2speed[] = {
+ 	[PHY_INTERFACE_MODE_RGMII_TXID]	= SPEED_1000,
+ 	[PHY_INTERFACE_MODE_RTBI]	= SPEED_1000,
+ 	[PHY_INTERFACE_MODE_XGMII]	= SPEED_10000,
+	[PHY_INTERFACE_MODE_SGMII_2500] = SPEED_2500,
+ };
+ 
+ static struct mac_device * __cold
+@@ -335,7 +337,8 @@ static int __cold mac_probe(struct platf
+ 	mac_dev->max_speed	= mac_dev->speed;
+ 	mac_dev->if_support = DTSEC_SUPPORTED;
+ 	/* We don't support half-duplex in SGMII mode */
+-	if (strstr(char_prop, "sgmii") || strstr(char_prop, "qsgmii"))
+	if (strstr(char_prop, "sgmii") || strstr(char_prop, "qsgmii") ||
+	    strstr(char_prop, "sgmii-2500"))
+ 		mac_dev->if_support &= ~(SUPPORTED_10baseT_Half |
+ 					SUPPORTED_100baseT_Half);
+ 
--- a/target/linux/layerscape/patches-4.4/7067-net-phy-add-SGMII-2500-PHY.patch
+++ b/target/linux/layerscape/patches-4.4/7067-net-phy-add-SGMII-2500-PHY.patch
@ -0,0 +1,20 @@
+From 6e4322d938f01f58156b0a5929daa648ecad4754 Mon Sep 17 00:00:00 2001
+From: Madalin Bucur <madalin.bucur@freescale.com>
+Date: Thu, 14 Apr 2016 12:03:52 +0300
+Subject: [PATCH 67/70] net: phy: add SGMII 2500 PHY
+
+Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com>
+---
+ include/linux/phy.h |    1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/include/linux/phy.h
+++ b/include/linux/phy.h
+@@ -77,6 +77,7 @@ typedef enum {
+ 	PHY_INTERFACE_MODE_XGMII,
+ 	PHY_INTERFACE_MODE_MOCA,
+ 	PHY_INTERFACE_MODE_QSGMII,
+	PHY_INTERFACE_MODE_SGMII_2500,
+ 	PHY_INTERFACE_MODE_MAX,
+ } phy_interface_t;
+ 
--- a/target/linux/layerscape/patches-4.4/7068-dpaa_ethernet-fix-link-state-detect-for-10G-interfac.patch
+++ b/target/linux/layerscape/patches-4.4/7068-dpaa_ethernet-fix-link-state-detect-for-10G-interfac.patch
@ -0,0 +1,63 @@
+From f77f25498902f84d53a64a6397db2fa4b0d0dd4b Mon Sep 17 00:00:00 2001
+From: Shaohui Xie <Shaohui.Xie@nxp.com>
+Date: Thu, 31 Mar 2016 10:53:06 +0800
+Subject: [PATCH 68/70] dpaa_ethernet: fix link state detect for 10G interface
+
+There are drivers to support 10G PHYs with copper interface, so we
+change binding between MAC and 10G PHY to use phy_state_machine to
+detect link state.
+
+Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
+---
+ drivers/net/ethernet/freescale/sdk_dpaa/mac-api.c |   20 ++++++++------------
+ 1 file changed, 8 insertions(+), 12 deletions(-)
+
+--- a/drivers/net/ethernet/freescale/sdk_dpaa/mac-api.c
+++ b/drivers/net/ethernet/freescale/sdk_dpaa/mac-api.c
+@@ -279,20 +279,15 @@ static int __cold start(struct mac_devic
+ 
+ 	_errno = fm_mac_enable(mac_dev->get_mac_handle(mac_dev));
+ 
+-	if (!_errno && phy_dev) {
+-		if (macdev2enetinterface(mac_dev) != e_ENET_MODE_XGMII_10000)
+-			phy_start(phy_dev);
+-		else if (phy_dev->drv->read_status)
+-			phy_dev->drv->read_status(phy_dev);
+-	}
+	if (!_errno && phy_dev)
+		phy_start(phy_dev);
+ 
+ 	return _errno;
+ }
+ 
+ static int __cold stop(struct mac_device *mac_dev)
+ {
+-	if (mac_dev->phy_dev &&
+-		(macdev2enetinterface(mac_dev) != e_ENET_MODE_XGMII_10000))
+	if (mac_dev->phy_dev)
+ 		phy_stop(mac_dev->phy_dev);
+ 
+ 	return fm_mac_disable(mac_dev->get_mac_handle(mac_dev));
+@@ -477,8 +472,8 @@ static int xgmac_init_phy(struct net_dev
+ 		phy_dev = phy_attach(net_dev, mac_dev->fixed_bus_id,
+ 				     mac_dev->phy_if);
+ 	else
+-		phy_dev = of_phy_attach(net_dev, mac_dev->phy_node, 0,
+-					mac_dev->phy_if);
+		phy_dev = of_phy_connect(net_dev, mac_dev->phy_node,
+					 &adjust_link, 0, mac_dev->phy_if);
+ 	if (unlikely(phy_dev == NULL) || IS_ERR(phy_dev)) {
+ 		netdev_err(net_dev, "Could not attach to PHY %s\n",
+ 				mac_dev->phy_node ?
+@@ -510,8 +505,9 @@ static int memac_init_phy(struct net_dev
+ 			mac_dev->phy_dev = NULL;
+ 			return 0;
+ 		} else
+-			phy_dev = of_phy_attach(net_dev, mac_dev->phy_node, 0,
+-						mac_dev->phy_if);
+			phy_dev = of_phy_connect(net_dev, mac_dev->phy_node,
+						 &adjust_link, 0,
+						 mac_dev->phy_if);
+ 	} else {
+ 		if (!mac_dev->phy_node)
+ 			phy_dev = phy_connect(net_dev, mac_dev->fixed_bus_id,
--- a/target/linux/layerscape/patches-4.4/8026-cpufreq-qoriq-Don-t-look-at-clock-implementation-det.patch
+++ b/target/linux/layerscape/patches-4.4/8026-cpufreq-qoriq-Don-t-look-at-clock-implementation-det.patch
@ -0,0 +1,274 @@
+From 8f3768a7c649526f821a6a4cd32cc44a8e7fa317 Mon Sep 17 00:00:00 2001
+From: Scott Wood <scottwood@freescale.com>
+Date: Fri, 15 Jan 2016 07:34:33 +0000
+Subject: [PATCH 26/70] cpufreq: qoriq: Don't look at clock implementation
+ details
+
+Get the CPU clock's potential parent clocks from the clock interface
+itself, rather than manually parsing the clocks property to find a
+phandle, looking at the clock-names property of that, and assuming that
+those are valid parent clocks for the cpu clock.
+
+This is necessary now that the clocks are generated based on the clock
+driver's knowledge of the chip rather than a fragile device-tree
+description of the mux options.
+
+We can now rely on the clock driver to ensure that the mux only exposes
+options that are valid.  The cpufreq driver was currently being overly
+conservative in some cases -- for example, the "min_cpufreq =
+get_bus_freq()" restriction only applies to chips with erratum
+A-004510, and whether the freq_mask used on p5020 is needed depends on
+the actual frequencies of the PLLs (FWIW, p5040 has a similar
+limitation but its .freq_mask was zero) -- and the frequency mask
+mechanism made assumptions about particular parent clock indices that
+are no longer valid.
+
+Signed-off-by: Scott Wood <scottwood@freescale.com>
+Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
+---
+ drivers/cpufreq/qoriq-cpufreq.c |  138 ++++++++++++---------------------------
+ 1 file changed, 41 insertions(+), 97 deletions(-)
+
+--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
+@@ -11,6 +11,7 @@
+ #define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
+ 
+ #include <linux/clk.h>
+#include <linux/clk-provider.h>
+ #include <linux/cpufreq.h>
+ #include <linux/errno.h>
+ #include <linux/init.h>
+@@ -35,53 +36,20 @@ struct cpu_data {
+ 	struct cpufreq_frequency_table *table;
+ };
+ 
+/*
+ * Don't use cpufreq on this SoC -- used when the SoC would have otherwise
+ * matched a more generic compatible.
+ */
+#define SOC_BLACKLIST		1
+
+ /**
+  * struct soc_data - SoC specific data
+- * @freq_mask: mask the disallowed frequencies
+- * @flag: unique flags
+ * @flags: SOC_xxx
+  */
+ struct soc_data {
+-	u32 freq_mask[4];
+-	u32 flag;
+-};
+-
+-#define FREQ_MASK	1
+-/* see hardware specification for the allowed frqeuencies */
+-static const struct soc_data sdata[] = {
+-	{ /* used by p2041 and p3041 */
+-		.freq_mask = {0x8, 0x8, 0x2, 0x2},
+-		.flag = FREQ_MASK,
+-	},
+-	{ /* used by p5020 */
+-		.freq_mask = {0x8, 0x2},
+-		.flag = FREQ_MASK,
+-	},
+-	{ /* used by p4080, p5040 */
+-		.freq_mask = {0},
+-		.flag = 0,
+-	},
+	u32 flags;
+ };
+ 
+-/*
+- * the minimum allowed core frequency, in Hz
+- * for chassis v1.0, >= platform frequency
+- * for chassis v2.0, >= platform frequency / 2
+- */
+-static u32 min_cpufreq;
+-static const u32 *fmask;
+-
+-#if defined(CONFIG_ARM)
+-static int get_cpu_physical_id(int cpu)
+-{
+-	return topology_core_id(cpu);
+-}
+-#else
+-static int get_cpu_physical_id(int cpu)
+-{
+-	return get_hard_smp_processor_id(cpu);
+-}
+-#endif
+-
+ static u32 get_bus_freq(void)
+ {
+ 	struct device_node *soc;
+@@ -99,9 +67,10 @@ static u32 get_bus_freq(void)
+ 	return sysfreq;
+ }
+ 
+-static struct device_node *cpu_to_clk_node(int cpu)
+static struct clk *cpu_to_clk(int cpu)
+ {
+-	struct device_node *np, *clk_np;
+	struct device_node *np;
+	struct clk *clk;
+ 
+ 	if (!cpu_present(cpu))
+ 		return NULL;
+@@ -110,37 +79,28 @@ static struct device_node *cpu_to_clk_no
+ 	if (!np)
+ 		return NULL;
+ 
+-	clk_np = of_parse_phandle(np, "clocks", 0);
+-	if (!clk_np)
+-		return NULL;
+-
+	clk = of_clk_get(np, 0);
+ 	of_node_put(np);
+-
+-	return clk_np;
+	return clk;
+ }
+ 
+ /* traverse cpu nodes to get cpu mask of sharing clock wire */
+ static void set_affected_cpus(struct cpufreq_policy *policy)
+ {
+-	struct device_node *np, *clk_np;
+ 	struct cpumask *dstp = policy->cpus;
+	struct clk *clk;
+ 	int i;
+ 
+-	np = cpu_to_clk_node(policy->cpu);
+-	if (!np)
+-		return;
+-
+ 	for_each_present_cpu(i) {
+-		clk_np = cpu_to_clk_node(i);
+-		if (!clk_np)
+		clk = cpu_to_clk(i);
+		if (IS_ERR(clk)) {
+			pr_err("%s: no clock for cpu %d\n", __func__, i);
+ 			continue;
+		}
+ 
+-		if (clk_np == np)
+		if (clk_is_match(policy->clk, clk))
+ 			cpumask_set_cpu(i, dstp);
+-
+-		of_node_put(clk_np);
+ 	}
+-	of_node_put(np);
+ }
+ 
+ /* reduce the duplicated frequencies in frequency table */
+@@ -198,7 +158,7 @@ static int qoriq_cpufreq_cpu_init(struct
+ {
+ 	struct device_node *np, *pnode;
+ 	int i, count, ret;
+-	u32 freq, mask;
+	u32 freq;
+ 	struct clk *clk;
+ 	struct cpufreq_frequency_table *table;
+ 	struct cpu_data *data;
+@@ -219,17 +179,12 @@ static int qoriq_cpufreq_cpu_init(struct
+ 		goto err_nomem2;
+ 	}
+ 
+-	pnode = of_parse_phandle(np, "clocks", 0);
+-	if (!pnode) {
+-		pr_err("%s: could not get clock information\n", __func__);
+-		goto err_nomem2;
+-	}
+	count = clk_get_num_parents(policy->clk);
+ 
+-	count = of_property_count_strings(pnode, "clock-names");
+ 	data->pclk = kcalloc(count, sizeof(struct clk *), GFP_KERNEL);
+ 	if (!data->pclk) {
+ 		pr_err("%s: no memory\n", __func__);
+-		goto err_node;
+		goto err_nomem2;
+ 	}
+ 
+ 	table = kcalloc(count + 1, sizeof(*table), GFP_KERNEL);
+@@ -238,23 +193,11 @@ static int qoriq_cpufreq_cpu_init(struct
+ 		goto err_pclk;
+ 	}
+ 
+-	if (fmask)
+-		mask = fmask[get_cpu_physical_id(cpu)];
+-	else
+-		mask = 0x0;
+-
+ 	for (i = 0; i < count; i++) {
+-		clk = of_clk_get(pnode, i);
+		clk = clk_get_parent_by_index(policy->clk, i);
+ 		data->pclk[i] = clk;
+ 		freq = clk_get_rate(clk);
+-		/*
+-		 * the clock is valid if its frequency is not masked
+-		 * and large than minimum allowed frequency.
+-		 */
+-		if (freq < min_cpufreq || (mask & (1 << i)))
+-			table[i].frequency = CPUFREQ_ENTRY_INVALID;
+-		else
+-			table[i].frequency = freq / 1000;
+		table[i].frequency = freq / 1000;
+ 		table[i].driver_data = i;
+ 	}
+ 	freq_table_redup(table, count);
+@@ -288,10 +231,7 @@ err_nomem1:
+ 	kfree(table);
+ err_pclk:
+ 	kfree(data->pclk);
+-err_node:
+-	of_node_put(pnode);
+ err_nomem2:
+-	policy->driver_data = NULL;
+ 	kfree(data);
+ err_np:
+ 	of_node_put(np);
+@@ -332,12 +272,20 @@ static struct cpufreq_driver qoriq_cpufr
+ 	.attr		= cpufreq_generic_attr,
+ };
+ 
+static const struct soc_data blacklist = {
+	.flags = SOC_BLACKLIST,
+};
+
+ static const struct of_device_id node_matches[] __initconst = {
+-	{ .compatible = "fsl,p2041-clockgen", .data = &sdata[0], },
+-	{ .compatible = "fsl,p3041-clockgen", .data = &sdata[0], },
+-	{ .compatible = "fsl,p5020-clockgen", .data = &sdata[1], },
+-	{ .compatible = "fsl,p4080-clockgen", .data = &sdata[2], },
+-	{ .compatible = "fsl,p5040-clockgen", .data = &sdata[2], },
+	/* e6500 cannot use cpufreq due to erratum A-008083 */
+	{ .compatible = "fsl,b4420-clockgen", &blacklist },
+	{ .compatible = "fsl,b4860-clockgen", &blacklist },
+	{ .compatible = "fsl,t2080-clockgen", &blacklist },
+	{ .compatible = "fsl,t4240-clockgen", &blacklist },
+
+	{ .compatible = "fsl,ls1021a-clockgen", },
+	{ .compatible = "fsl,p4080-clockgen", },
+	{ .compatible = "fsl,qoriq-clockgen-1.0", },
+ 	{ .compatible = "fsl,qoriq-clockgen-2.0", },
+ 	{}
+ };
+@@ -355,16 +303,12 @@ static int __init qoriq_cpufreq_init(voi
+ 
+ 	match = of_match_node(node_matches, np);
+ 	data = match->data;
+-	if (data) {
+-		if (data->flag)
+-			fmask = data->freq_mask;
+-		min_cpufreq = get_bus_freq();
+-	} else {
+-		min_cpufreq = get_bus_freq() / 2;
+-	}
+ 
+ 	of_node_put(np);
+ 
+	if (data && data->flags & SOC_BLACKLIST)
+		return -ENODEV;
+
+ 	ret = cpufreq_register_driver(&qoriq_cpufreq_driver);
+ 	if (!ret)
+ 		pr_info("Freescale QorIQ CPU frequency scaling driver\n");
--- a/target/linux/layerscape/patches-4.4/8036-ls2085a-Add-support-for-reset.patch
+++ b/target/linux/layerscape/patches-4.4/8036-ls2085a-Add-support-for-reset.patch
@ -0,0 +1,135 @@
+From 4b9227ba510562a51e87487905895aea97e17e77 Mon Sep 17 00:00:00 2001
+From: pankaj chauhan <pankaj.chauhan@freescale.com>
+Date: Tue, 3 Feb 2015 13:08:52 +0530
+Subject: [PATCH 36/70] ls2085a: Add support for reset
+
+Add support for layerscape reset driver.
+Reset is implemented by raising RESET_REQ_B.
+
+Signed-off-by: pankaj chauhan <pankaj.chauhan@freescale.com>
+Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
+(cherry picked from commit f248be3aea58ca32b7d77413d742996249b293e9)
+---
+ drivers/power/reset/Kconfig     |    7 ++-
+ drivers/power/reset/Makefile    |    1 +
+ drivers/power/reset/ls-reboot.c |   93 +++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 100 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/power/reset/ls-reboot.c
+
+--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
+@@ -173,5 +173,10 @@ config POWER_RESET_ZX
+ 	help
+ 	  Reboot support for ZTE SoCs.
+ 
+-endif
+config POWER_RESET_LAYERSCAPE
+	bool "Freescale LayerScape reset driver"
+	depends on ARCH_FSL_LS2085A
+	help
+	  Reboot support for the Freescale LayerScape SoCs.
+ 
+endif
+--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
+@@ -20,3 +20,4 @@ obj-$(CONFIG_POWER_RESET_SYSCON) += sysc
+ obj-$(CONFIG_POWER_RESET_SYSCON_POWEROFF) += syscon-poweroff.o
+ obj-$(CONFIG_POWER_RESET_RMOBILE) += rmobile-reset.o
+ obj-$(CONFIG_POWER_RESET_ZX) += zx-reboot.o
+obj-$(CONFIG_POWER_RESET_LAYERSCAPE) += ls-reboot.o
+--- /dev/null
+++ b/drivers/power/reset/ls-reboot.c
+@@ -0,0 +1,93 @@
+/*
+ * Freescale LayerScape reboot driver
+ *
+ * Copyright (c) 2015, Freescale Semiconductor.
+ * Author: Pankaj Chauhan <pankaj.chauhan@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/stat.h>
+#include <linux/slab.h>
+#include <asm/system_misc.h>
+
+struct	ls_reboot_priv {
+	struct device *dev;
+	u32 *rstcr;
+};
+
+static struct ls_reboot_priv	*ls_reboot_priv;
+
+static void ls_reboot(enum reboot_mode reboot_mode, const char *cmd)
+{
+	struct ls_reboot_priv	*priv = ls_reboot_priv;
+	u32 val;
+	unsigned long timeout;
+
+	if (ls_reboot_priv) {
+		val = readl(priv->rstcr);
+		val |= 0x02;
+		writel(val, priv->rstcr);
+	}
+
+	timeout = jiffies + HZ;
+	while (time_before(jiffies, timeout))
+		cpu_relax();
+
+}
+
+static int ls_reboot_probe(struct platform_device *pdev)
+{
+	ls_reboot_priv = devm_kzalloc(&pdev->dev,
+				sizeof(*ls_reboot_priv), GFP_KERNEL);
+	if (!ls_reboot_priv) {
+		dev_err(&pdev->dev, "out of memory for context\n");
+		return -ENODEV;
+	}
+
+	ls_reboot_priv->rstcr = of_iomap(pdev->dev.of_node, 0);
+	if (!ls_reboot_priv->rstcr) {
+		devm_kfree(&pdev->dev, ls_reboot_priv);
+		dev_err(&pdev->dev, "can not map resource\n");
+		return -ENODEV;
+	}
+
+	ls_reboot_priv->dev = &pdev->dev;
+
+	arm_pm_restart = ls_reboot;
+
+	return 0;
+}
+
+static struct of_device_id ls_reboot_of_match[] = {
+	{ .compatible = "fsl,ls-reset" },
+	{}
+};
+
+static struct platform_driver ls_reboot_driver = {
+	.probe = ls_reboot_probe,
+	.driver = {
+		.name = "ls-reset",
+		.of_match_table = ls_reboot_of_match,
+	},
+};
+
+static int __init ls_reboot_init(void)
+{
+	return platform_driver_register(&ls_reboot_driver);
+}
+device_initcall(ls_reboot_init);
--- a/target/linux/layerscape/patches-4.4/8037-ls1043a-Add-support-for-reset.patch
+++ b/target/linux/layerscape/patches-4.4/8037-ls1043a-Add-support-for-reset.patch
@ -0,0 +1,56 @@
+From 5d7f8473e3472c16703bf5692d0b13f47d08c70a Mon Sep 17 00:00:00 2001
+From: Shaohui Xie <Shaohui.Xie@freescale.com>
+Date: Fri, 22 Jan 2016 12:01:28 +0800
+Subject: [PATCH 37/70] ls1043a: Add support for reset
+
+The reset in ls1043a is similar to ls2085a, but accessed in big endian,
+so we modify the existing driver to handle endianness, if driver probes
+property 'big-endian' in DTS, driver works in big endian mode,
+otherwise, driver works in little endian by default.
+
+Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
+---
+ drivers/power/reset/ls-reboot.c |   18 +++++++++++++++---
+ 1 file changed, 15 insertions(+), 3 deletions(-)
+
+--- a/drivers/power/reset/ls-reboot.c
+++ b/drivers/power/reset/ls-reboot.c
+@@ -28,6 +28,7 @@
+ struct	ls_reboot_priv {
+ 	struct device *dev;
+ 	u32 *rstcr;
+	bool is_big_endian;
+ };
+ 
+ static struct ls_reboot_priv	*ls_reboot_priv;
+@@ -39,9 +40,15 @@ static void ls_reboot(enum reboot_mode r
+ 	unsigned long timeout;
+ 
+ 	if (ls_reboot_priv) {
+-		val = readl(priv->rstcr);
+-		val |= 0x02;
+-		writel(val, priv->rstcr);
+		if (priv->is_big_endian) {
+			val = ioread32be(priv->rstcr);
+			val |= 0x02;
+			iowrite32be(val, priv->rstcr);
+		} else {
+			val = readl(priv->rstcr);
+			val |= 0x02;
+			writel(val, priv->rstcr);
+		}
+ 	}
+ 
+ 	timeout = jiffies + HZ;
+@@ -66,6 +73,11 @@ static int ls_reboot_probe(struct platfo
+ 		return -ENODEV;
+ 	}
+ 
+	if (of_get_property(pdev->dev.of_node, "big-endian", NULL))
+		ls_reboot_priv->is_big_endian = true;
+	else
+		ls_reboot_priv->is_big_endian = false;
+
+ 	ls_reboot_priv->dev = &pdev->dev;
+ 
+ 	arm_pm_restart = ls_reboot;
--- a/target/linux/layerscape/patches-4.4/8038-reset-driver-Kconfig-Change-define-to-ARCH_LAYERSCAP.patch
+++ b/target/linux/layerscape/patches-4.4/8038-reset-driver-Kconfig-Change-define-to-ARCH_LAYERSCAP.patch
@ -0,0 +1,22 @@
+From 6569dc5ba472db76aefe65ef552c3f448348fbec Mon Sep 17 00:00:00 2001
+From: Rai Harninder-B01044 <harninder.rai@freescale.com>
+Date: Wed, 28 Oct 2015 13:24:44 +0530
+Subject: [PATCH 38/70] reset driver: Kconfig: Change define to
+ ARCH_LAYERSCAPE
+
+Signed-off-by: Rai Harninder-B01044 <harninder.rai@freescale.com>
+---
+ drivers/power/reset/Kconfig |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
+@@ -175,7 +175,7 @@ config POWER_RESET_ZX
+ 
+ config POWER_RESET_LAYERSCAPE
+ 	bool "Freescale LayerScape reset driver"
+-	depends on ARCH_FSL_LS2085A
+	depends on ARCH_LAYERSCAPE
+ 	help
+ 	  Reboot support for the Freescale LayerScape SoCs.
+ 
--- a/target/linux/layerscape/patches-4.4/8042-drivers-gpio-Port-gpio-driver-to-support-layerscape-.patch
+++ b/target/linux/layerscape/patches-4.4/8042-drivers-gpio-Port-gpio-driver-to-support-layerscape-.patch
@ -0,0 +1,289 @@
+From c2d0a12b5cfa61e43494483f5d1ee466b4998830 Mon Sep 17 00:00:00 2001
+From: Liu Gang <Gang.Liu@nxp.com>
+Date: Thu, 14 Jan 2016 19:48:09 +0800
+Subject: [PATCH 42/70] drivers/gpio: Port gpio driver to support layerscape
+ platform
+
+Layerscape has the same ip block/controller as
+GPIO on powerpc platform(MPC8XXX).
+
+So use portable i/o accessors, as in_be32/out_be32
+accessors are Power architecture specific whereas
+ioread32/iowrite32 and ioread32be/iowrite32be are
+available in other architectures.
+
+Layerscape GPIO controller's registers may be big
+or little endian, so the code needs to get the
+endian property from DTB, then make additional
+functions to fit right register read/write
+operations.
+
+Currently the code can support ls2080a GPIO with
+little endian registers. And it can also work well
+on other layerscape platform with big endian GPIO
+registers.
+
+Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
+---
+ drivers/gpio/Kconfig        |    7 ++--
+ drivers/gpio/gpio-mpc8xxx.c |   87 +++++++++++++++++++++++++++++++------------
+ 2 files changed, 68 insertions(+), 26 deletions(-)
+
+--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
+@@ -281,12 +281,13 @@ config GPIO_MPC5200
+ 	depends on PPC_MPC52xx
+ 
+ config GPIO_MPC8XXX
+-	bool "MPC512x/MPC8xxx GPIO support"
+	bool "MPC512x/MPC8xxx/QorIQ GPIO support"
+ 	depends on PPC_MPC512x || PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || \
+-		   FSL_SOC_BOOKE || PPC_86xx
+		   FSL_SOC_BOOKE || PPC_86xx || ARCH_LAYERSCAPE || ARM || \
+		   COMPILE_TEST
+ 	help
+ 	  Say Y here if you're going to use hardware that connects to the
+-	  MPC512x/831x/834x/837x/8572/8610 GPIOs.
+	  MPC512x/831x/834x/837x/8572/8610/QorIQ GPIOs.
+ 
+ config GPIO_MVEBU
+ 	def_bool y
+--- a/drivers/gpio/gpio-mpc8xxx.c
+++ b/drivers/gpio/gpio-mpc8xxx.c
+@@ -1,5 +1,5 @@
+ /*
+- * GPIOs on MPC512x/8349/8572/8610 and compatible
+ * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
+  *
+  * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
+  *
+@@ -19,6 +19,7 @@
+ #include <linux/gpio.h>
+ #include <linux/slab.h>
+ #include <linux/irq.h>
+#include <linux/irqdomain.h>
+ 
+ #define MPC8XXX_GPIO_PINS	32
+ 
+@@ -44,6 +45,27 @@ struct mpc8xxx_gpio_chip {
+ 	const void *of_dev_id_data;
+ };
+ 
+static bool gpio_little_endian;
+static inline u32 gpio_in32(void __iomem *addr)
+{
+	u32 val;
+
+	if (gpio_little_endian)
+		val = ioread32(addr);
+	else
+		val = ioread32be(addr);
+
+	return val;
+}
+
+static inline void gpio_out32(u32 val, void __iomem *addr)
+{
+	if (gpio_little_endian)
+		iowrite32(val, addr);
+	else
+		iowrite32be(val, addr);
+}
+
+ static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
+ {
+ 	return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
+@@ -59,9 +81,17 @@ static void mpc8xxx_gpio_save_regs(struc
+ {
+ 	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
+ 
+-	mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
+	mpc8xxx_gc->data = gpio_in32(mm->regs + GPIO_DAT);
+ }
+ 
+/* Generic set and clear bits accessor ports */
+#define bgpio_setbits32(_addr, _v) \
+		gpio_out32(gpio_in32(_addr) |  (_v), (_addr))
+#define bgpio_clrbits32(_addr, _v) \
+		gpio_out32(gpio_in32(_addr) & ~(_v), (_addr))
+#define bgpio_clrsetbits32(addr, clear, set) \
+		gpio_out32((gpio_in32(addr) & ~(clear)) | (set), (addr))
+
+ /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
+  * defined as output cannot be determined by reading GPDAT register,
+  * so we use shadow data register instead. The status of input pins
+@@ -74,9 +104,9 @@ static int mpc8572_gpio_get(struct gpio_
+ 	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
+ 	u32 out_mask, out_shadow;
+ 
+-	out_mask = in_be32(mm->regs + GPIO_DIR);
+	out_mask = gpio_in32(mm->regs + GPIO_DIR);
+ 
+-	val = in_be32(mm->regs + GPIO_DAT) & ~out_mask;
+	val = gpio_in32(mm->regs + GPIO_DAT) & ~out_mask;
+ 	out_shadow = mpc8xxx_gc->data & out_mask;
+ 
+ 	return (val | out_shadow) & mpc8xxx_gpio2mask(gpio);
+@@ -86,7 +116,7 @@ static int mpc8xxx_gpio_get(struct gpio_
+ {
+ 	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
+ 
+-	return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
+	return gpio_in32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
+ }
+ 
+ static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
+@@ -102,7 +132,7 @@ static void mpc8xxx_gpio_set(struct gpio
+ 	else
+ 		mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
+ 
+-	out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
+	gpio_out32(mpc8xxx_gc->data, mm->regs + GPIO_DAT);
+ 
+ 	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+ }
+@@ -128,7 +158,7 @@ static void mpc8xxx_gpio_set_multiple(st
+ 		}
+ 	}
+ 
+-	out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
+	gpio_out32(mpc8xxx_gc->data, mm->regs + GPIO_DAT);
+ 
+ 	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+ }
+@@ -141,7 +171,7 @@ static int mpc8xxx_gpio_dir_in(struct gp
+ 
+ 	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+ 
+-	clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
+	bgpio_clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
+ 
+ 	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+ 
+@@ -158,7 +188,7 @@ static int mpc8xxx_gpio_dir_out(struct g
+ 
+ 	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+ 
+-	setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
+	bgpio_setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
+ 
+ 	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+ 
+@@ -201,7 +231,8 @@ static void mpc8xxx_gpio_irq_cascade(str
+ 	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
+ 	unsigned int mask;
+ 
+-	mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
+	mask = gpio_in32(mm->regs + GPIO_IER)
+		& gpio_in32(mm->regs + GPIO_IMR);
+ 	if (mask)
+ 		generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
+ 						     32 - ffs(mask)));
+@@ -217,7 +248,8 @@ static void mpc8xxx_irq_unmask(struct ir
+ 
+ 	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+ 
+-	setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
+	bgpio_setbits32(mm->regs + GPIO_IMR,
+			mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
+ 
+ 	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+ }
+@@ -230,7 +262,8 @@ static void mpc8xxx_irq_mask(struct irq_
+ 
+ 	raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+ 
+-	clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
+	bgpio_clrbits32(mm->regs + GPIO_IMR,
+			mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
+ 
+ 	raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+ }
+@@ -240,7 +273,7 @@ static void mpc8xxx_irq_ack(struct irq_d
+ 	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
+ 	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
+ 
+-	out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
+	gpio_out32(mpc8xxx_gpio2mask(irqd_to_hwirq(d)), mm->regs + GPIO_IER);
+ }
+ 
+ static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
+@@ -252,15 +285,15 @@ static int mpc8xxx_irq_set_type(struct i
+ 	switch (flow_type) {
+ 	case IRQ_TYPE_EDGE_FALLING:
+ 		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+-		setbits32(mm->regs + GPIO_ICR,
+-			  mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
+		bgpio_setbits32(mm->regs + GPIO_ICR,
+				mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
+ 		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+ 		break;
+ 
+ 	case IRQ_TYPE_EDGE_BOTH:
+ 		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+-		clrbits32(mm->regs + GPIO_ICR,
+-			  mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
+		bgpio_clrbits32(mm->regs + GPIO_ICR,
+				mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
+ 		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+ 		break;
+ 
+@@ -292,20 +325,20 @@ static int mpc512x_irq_set_type(struct i
+ 	case IRQ_TYPE_EDGE_FALLING:
+ 	case IRQ_TYPE_LEVEL_LOW:
+ 		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+-		clrsetbits_be32(reg, 3 << shift, 2 << shift);
+		bgpio_clrsetbits32(reg, 3 << shift, 2 << shift);
+ 		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+ 		break;
+ 
+ 	case IRQ_TYPE_EDGE_RISING:
+ 	case IRQ_TYPE_LEVEL_HIGH:
+ 		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+-		clrsetbits_be32(reg, 3 << shift, 1 << shift);
+		bgpio_clrsetbits32(reg, 3 << shift, 1 << shift);
+ 		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+ 		break;
+ 
+ 	case IRQ_TYPE_EDGE_BOTH:
+ 		raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
+-		clrbits32(reg, 3 << shift);
+		bgpio_clrbits32(reg, 3 << shift);
+ 		raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
+ 		break;
+ 
+@@ -398,6 +431,14 @@ static int mpc8xxx_probe(struct platform
+ 	mm_gc = &mpc8xxx_gc->mm_gc;
+ 	gc = &mm_gc->gc;
+ 
+	if (of_property_read_bool(np, "little-endian")) {
+		gpio_little_endian = true;
+		dev_dbg(&pdev->dev, "GPIO REGISTERS are LITTLE endian\n");
+	} else {
+		gpio_little_endian = false;
+		dev_dbg(&pdev->dev, "GPIO REGISTERS are BIG endian\n");
+	}
+
+ 	mm_gc->save_regs = mpc8xxx_gpio_save_regs;
+ 	gc->ngpio = MPC8XXX_GPIO_PINS;
+ 	gc->direction_input = mpc8xxx_gpio_dir_in;
+@@ -422,7 +463,7 @@ static int mpc8xxx_probe(struct platform
+ 		return ret;
+ 
+ 	mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
+-	if (mpc8xxx_gc->irqn == NO_IRQ)
+	if (mpc8xxx_gc->irqn == 0)
+ 		return 0;
+ 
+ 	mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
+@@ -435,8 +476,8 @@ static int mpc8xxx_probe(struct platform
+ 		mpc8xxx_gc->of_dev_id_data = id->data;
+ 
+ 	/* ack and mask all irqs */
+-	out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
+-	out_be32(mm_gc->regs + GPIO_IMR, 0);
+	gpio_out32(0xffffffff, mm_gc->regs + GPIO_IER);
+	gpio_out32(0, mm_gc->regs + GPIO_IMR);
+ 
+ 	irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
+ 					 mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
--- a/target/linux/layerscape/patches-4.4/8048-mmc-sdhci-of-esdhc-add-remove-some-quirks-according-.patch
+++ b/target/linux/layerscape/patches-4.4/8048-mmc-sdhci-of-esdhc-add-remove-some-quirks-according-.patch
@ -0,0 +1,60 @@
+From dfc4661c2499aeb0a43b8a13b55213d1c190f640 Mon Sep 17 00:00:00 2001
+From: yangbo lu <yangbo.lu@freescale.com>
+Date: Tue, 19 Apr 2016 09:47:15 +0800
+Subject: [PATCH 48/70] mmc: sdhci-of-esdhc: add/remove some quirks according
+ to vendor version
+
+commit 6c42cb309fee2e126beed6b96a986dc7d85a033d
+[context adjustment]
+
+A previous patch had removed esdhc_of_platform_init() by mistake.
+static void esdhc_of_platform_init(struct sdhci_host *host)
+{
+	u32 vvn;
+
+	vvn = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);
+	vvn = (vvn & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT;
+	if (vvn == VENDOR_V_22)
+		host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
+
+	if (vvn > VENDOR_V_22)
+		host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
+}
+
+This patch is used to fix it by add/remove some quirks according to
+verdor version in probe.
+
+Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
+Fixes: f4932cfd22f1 ("mmc: sdhci-of-esdhc: support both BE and LE host controller")
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
+---
+ drivers/mmc/host/sdhci-of-esdhc.c |   10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
+@@ -584,6 +584,8 @@ static int sdhci_esdhc_probe(struct plat
+ {
+ 	struct sdhci_host *host;
+ 	struct device_node *np;
+	struct sdhci_pltfm_host *pltfm_host;
+	struct sdhci_esdhc *esdhc;
+ 	int ret;
+ 
+ 	np = pdev->dev.of_node;
+@@ -611,6 +613,14 @@ static int sdhci_esdhc_probe(struct plat
+ 	if (of_device_is_compatible(np, "fsl,ls1021a-esdhc"))
+ 		host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
+ 
+	pltfm_host = sdhci_priv(host);
+	esdhc = pltfm_host->priv;
+	if (esdhc->vendor_ver == VENDOR_V_22)
+		host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
+
+	if (esdhc->vendor_ver > VENDOR_V_22)
+		host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
+
+ 	if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
+ 		/*
+ 		 * Freescale messed up with P2020 as it has a non-standard
--- a/target/linux/layerscape/patches-4.4/8049-PCI-layerscape-Add-fsl-ls2085a-pcie-compatible-ID.patch
+++ b/target/linux/layerscape/patches-4.4/8049-PCI-layerscape-Add-fsl-ls2085a-pcie-compatible-ID.patch
@ -0,0 +1,25 @@
+From f2d357f86d79141969e29ec1dc1669da5120e022 Mon Sep 17 00:00:00 2001
+From: Yang Shi <yang.shi@linaro.org>
+Date: Wed, 27 Jan 2016 09:32:05 -0800
+Subject: [PATCH 49/70] PCI: layerscape: Add "fsl,ls2085a-pcie" compatible ID
+
+The Layerscape PCI host driver must recognize ls2085a compatible when using
+firmware with ls2085a compatible property, otherwise the PCI bus won't be
+detected even though ls2085a compatible is included by the dts.
+
+Signed-off-by: Yang Shi <yang.shi@linaro.org>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+---
+ drivers/pci/host/pci-layerscape.c |    1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/pci/host/pci-layerscape.c
+++ b/drivers/pci/host/pci-layerscape.c
+@@ -203,6 +203,7 @@ static const struct of_device_id ls_pcie
+ 	{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
+ 	{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
+ 	{ .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
+	{ .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
+ 	{ },
+ };
+ MODULE_DEVICE_TABLE(of, ls_pcie_of_match);
--- a/target/linux/layerscape/patches-4.4/8050-PCI-layerscape-Fix-MSG-TLP-drop-setting.patch
+++ b/target/linux/layerscape/patches-4.4/8050-PCI-layerscape-Fix-MSG-TLP-drop-setting.patch
@ -0,0 +1,66 @@
+From 61959c53020fff0584d88e28d6dae9806184f1a8 Mon Sep 17 00:00:00 2001
+From: Minghuan Lian <Minghuan.Lian@nxp.com>
+Date: Mon, 29 Feb 2016 17:24:15 -0600
+Subject: [PATCH 50/70] PCI: layerscape: Fix MSG TLP drop setting
+
+Some kinds of Layerscape PCIe controllers will forward the received message
+TLPs to system application address space, which could corrupt system memory
+or lead to a system hang.  Enable MSG_DROP to fix this issue.
+
+Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+---
+ drivers/pci/host/pci-layerscape.c |   21 +++++++++++++--------
+ 1 file changed, 13 insertions(+), 8 deletions(-)
+
+--- a/drivers/pci/host/pci-layerscape.c
+++ b/drivers/pci/host/pci-layerscape.c
+@@ -77,6 +77,16 @@ static void ls_pcie_fix_class(struct ls_
+ 	iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
+ }
+ 
+/* Drop MSG TLP except for Vendor MSG */
+static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
+{
+	u32 val;
+
+	val = ioread32(pcie->dbi + PCIE_STRFMR1);
+	val &= 0xDFFFFFFF;
+	iowrite32(val, pcie->dbi + PCIE_STRFMR1);
+}
+
+ static int ls1021_pcie_link_up(struct pcie_port *pp)
+ {
+ 	u32 state;
+@@ -97,7 +107,7 @@ static int ls1021_pcie_link_up(struct pc
+ static void ls1021_pcie_host_init(struct pcie_port *pp)
+ {
+ 	struct ls_pcie *pcie = to_ls_pcie(pp);
+-	u32 val, index[2];
+	u32 index[2];
+ 
+ 	pcie->scfg = syscon_regmap_lookup_by_phandle(pp->dev->of_node,
+ 						     "fsl,pcie-scfg");
+@@ -116,13 +126,7 @@ static void ls1021_pcie_host_init(struct
+ 
+ 	dw_pcie_setup_rc(pp);
+ 
+-	/*
+-	 * LS1021A Workaround for internal TKT228622
+-	 * to fix the INTx hang issue
+-	 */
+-	val = ioread32(pcie->dbi + PCIE_STRFMR1);
+-	val &= 0xffff;
+-	iowrite32(val, pcie->dbi + PCIE_STRFMR1);
+	ls_pcie_drop_msg_tlp(pcie);
+ }
+ 
+ static int ls_pcie_link_up(struct pcie_port *pp)
+@@ -147,6 +151,7 @@ static void ls_pcie_host_init(struct pci
+ 	iowrite32(1, pcie->dbi + PCIE_DBI_RO_WR_EN);
+ 	ls_pcie_fix_class(pcie);
+ 	ls_pcie_clear_multifunction(pcie);
+	ls_pcie_drop_msg_tlp(pcie);
+ 	iowrite32(0, pcie->dbi + PCIE_DBI_RO_WR_EN);
+ }
+ 
--- a/target/linux/layerscape/patches-4.4/8060-irqchip-Add-Layerscape-SCFG-MSI-controller-support.patch
+++ b/target/linux/layerscape/patches-4.4/8060-irqchip-Add-Layerscape-SCFG-MSI-controller-support.patch
@ -0,0 +1,285 @@
+From 83ec4322b33e8d7908a3df0343246882e4e6b83a Mon Sep 17 00:00:00 2001
+From: Minghuan Lian <Minghuan.Lian@nxp.com>
+Date: Wed, 23 Mar 2016 19:08:20 +0800
+Subject: [PATCH 60/70] irqchip: Add Layerscape SCFG MSI controller support
+
+upstream b8f3ebe630a4f1b4ff9340103d3b565ad5d78d43 commit
+[context adjustment]
+
+Some kind of Freescale Layerscape SoC provides a MSI
+implementation which uses two SCFG registers MSIIR and
+MSIR to support 32 MSI interrupts for each PCIe controller.
+The patch is to support it.
+
+Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
+Tested-by: Alexander Stein <alexander.stein@systec-electronic.com>
+Acked-by: Marc Zyngier <marc.zyngier@arm.com>
+Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
+---
+ drivers/irqchip/Kconfig           |    5 +
+ drivers/irqchip/Makefile          |    1 +
+ drivers/irqchip/irq-ls-scfg-msi.c |  240 +++++++++++++++++++++++++++++++++++++
+ 3 files changed, 246 insertions(+)
+ create mode 100644 drivers/irqchip/irq-ls-scfg-msi.c
+
+--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
+@@ -193,3 +193,8 @@ config IRQ_MXS
+ 	def_bool y if MACH_ASM9260 || ARCH_MXS
+ 	select IRQ_DOMAIN
+ 	select STMP_DEVICE
+
+config LS_SCFG_MSI
+	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
+	depends on PCI && PCI_MSI
+	select PCI_MSI_IRQ_DOMAIN
+--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
+@@ -55,3 +55,4 @@ obj-$(CONFIG_RENESAS_H8S_INTC)		+= irq-r
+ obj-$(CONFIG_ARCH_SA1100)		+= irq-sa11x0.o
+ obj-$(CONFIG_INGENIC_IRQ)		+= irq-ingenic.o
+ obj-$(CONFIG_IMX_GPCV2)			+= irq-imx-gpcv2.o
+obj-$(CONFIG_LS_SCFG_MSI)		+= irq-ls-scfg-msi.o
+--- /dev/null
+++ b/drivers/irqchip/irq-ls-scfg-msi.c
+@@ -0,0 +1,240 @@
+/*
+ * Freescale SCFG MSI(-X) support
+ *
+ * Copyright (C) 2016 Freescale Semiconductor.
+ *
+ * Author: Minghuan Lian <Minghuan.Lian@nxp.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/msi.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/spinlock.h>
+
+#define MSI_MAX_IRQS	32
+#define MSI_IBS_SHIFT	3
+#define MSIR		4
+
+struct ls_scfg_msi {
+	spinlock_t		lock;
+	struct platform_device	*pdev;
+	struct irq_domain	*parent;
+	struct irq_domain	*msi_domain;
+	void __iomem		*regs;
+	phys_addr_t		msiir_addr;
+	int			irq;
+	DECLARE_BITMAP(used, MSI_MAX_IRQS);
+};
+
+static struct irq_chip ls_scfg_msi_irq_chip = {
+	.name = "MSI",
+	.irq_mask	= pci_msi_mask_irq,
+	.irq_unmask	= pci_msi_unmask_irq,
+};
+
+static struct msi_domain_info ls_scfg_msi_domain_info = {
+	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS |
+		   MSI_FLAG_USE_DEF_CHIP_OPS |
+		   MSI_FLAG_PCI_MSIX),
+	.chip	= &ls_scfg_msi_irq_chip,
+};
+
+static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
+{
+	struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data);
+
+	msg->address_hi = upper_32_bits(msi_data->msiir_addr);
+	msg->address_lo = lower_32_bits(msi_data->msiir_addr);
+	msg->data = data->hwirq << MSI_IBS_SHIFT;
+}
+
+static int ls_scfg_msi_set_affinity(struct irq_data *irq_data,
+				    const struct cpumask *mask, bool force)
+{
+	return -EINVAL;
+}
+
+static struct irq_chip ls_scfg_msi_parent_chip = {
+	.name			= "SCFG",
+	.irq_compose_msi_msg	= ls_scfg_msi_compose_msg,
+	.irq_set_affinity	= ls_scfg_msi_set_affinity,
+};
+
+static int ls_scfg_msi_domain_irq_alloc(struct irq_domain *domain,
+					unsigned int virq,
+					unsigned int nr_irqs,
+					void *args)
+{
+	struct ls_scfg_msi *msi_data = domain->host_data;
+	int pos, err = 0;
+
+	WARN_ON(nr_irqs != 1);
+
+	spin_lock(&msi_data->lock);
+	pos = find_first_zero_bit(msi_data->used, MSI_MAX_IRQS);
+	if (pos < MSI_MAX_IRQS)
+		__set_bit(pos, msi_data->used);
+	else
+		err = -ENOSPC;
+	spin_unlock(&msi_data->lock);
+
+	if (err)
+		return err;
+
+	irq_domain_set_info(domain, virq, pos,
+			    &ls_scfg_msi_parent_chip, msi_data,
+			    handle_simple_irq, NULL, NULL);
+
+	return 0;
+}
+
+static void ls_scfg_msi_domain_irq_free(struct irq_domain *domain,
+				   unsigned int virq, unsigned int nr_irqs)
+{
+	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
+	struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(d);
+	int pos;
+
+	pos = d->hwirq;
+	if (pos < 0 || pos >= MSI_MAX_IRQS) {
+		pr_err("failed to teardown msi. Invalid hwirq %d\n", pos);
+		return;
+	}
+
+	spin_lock(&msi_data->lock);
+	__clear_bit(pos, msi_data->used);
+	spin_unlock(&msi_data->lock);
+}
+
+static const struct irq_domain_ops ls_scfg_msi_domain_ops = {
+	.alloc	= ls_scfg_msi_domain_irq_alloc,
+	.free	= ls_scfg_msi_domain_irq_free,
+};
+
+static void ls_scfg_msi_irq_handler(struct irq_desc *desc)
+{
+	struct ls_scfg_msi *msi_data = irq_desc_get_handler_data(desc);
+	unsigned long val;
+	int pos, virq;
+
+	chained_irq_enter(irq_desc_get_chip(desc), desc);
+
+	val = ioread32be(msi_data->regs + MSIR);
+	for_each_set_bit(pos, &val, MSI_MAX_IRQS) {
+		virq = irq_find_mapping(msi_data->parent, (31 - pos));
+		if (virq)
+			generic_handle_irq(virq);
+	}
+
+	chained_irq_exit(irq_desc_get_chip(desc), desc);
+}
+
+static int ls_scfg_msi_domains_init(struct ls_scfg_msi *msi_data)
+{
+	/* Initialize MSI domain parent */
+	msi_data->parent = irq_domain_add_linear(NULL,
+						 MSI_MAX_IRQS,
+						 &ls_scfg_msi_domain_ops,
+						 msi_data);
+	if (!msi_data->parent) {
+		dev_err(&msi_data->pdev->dev, "failed to create IRQ domain\n");
+		return -ENOMEM;
+	}
+
+	msi_data->msi_domain = pci_msi_create_irq_domain(
+				of_node_to_fwnode(msi_data->pdev->dev.of_node),
+				&ls_scfg_msi_domain_info,
+				msi_data->parent);
+	if (!msi_data->msi_domain) {
+		dev_err(&msi_data->pdev->dev, "failed to create MSI domain\n");
+		irq_domain_remove(msi_data->parent);
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+static int ls_scfg_msi_probe(struct platform_device *pdev)
+{
+	struct ls_scfg_msi *msi_data;
+	struct resource *res;
+	int ret;
+
+	msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL);
+	if (!msi_data)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	msi_data->regs = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(msi_data->regs)) {
+		dev_err(&pdev->dev, "failed to initialize 'regs'\n");
+		return PTR_ERR(msi_data->regs);
+	}
+	msi_data->msiir_addr = res->start;
+
+	msi_data->irq = platform_get_irq(pdev, 0);
+	if (msi_data->irq <= 0) {
+		dev_err(&pdev->dev, "failed to get MSI irq\n");
+		return -ENODEV;
+	}
+
+	msi_data->pdev = pdev;
+	spin_lock_init(&msi_data->lock);
+
+	ret = ls_scfg_msi_domains_init(msi_data);
+	if (ret)
+		return ret;
+
+	irq_set_chained_handler_and_data(msi_data->irq,
+					 ls_scfg_msi_irq_handler,
+					 msi_data);
+
+	platform_set_drvdata(pdev, msi_data);
+
+	return 0;
+}
+
+static int ls_scfg_msi_remove(struct platform_device *pdev)
+{
+	struct ls_scfg_msi *msi_data = platform_get_drvdata(pdev);
+
+	irq_set_chained_handler_and_data(msi_data->irq, NULL, NULL);
+
+	irq_domain_remove(msi_data->msi_domain);
+	irq_domain_remove(msi_data->parent);
+
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+static const struct of_device_id ls_scfg_msi_id[] = {
+	{ .compatible = "fsl,1s1021a-msi", },
+	{ .compatible = "fsl,1s1043a-msi", },
+	{},
+};
+
+static struct platform_driver ls_scfg_msi_driver = {
+	.driver = {
+		.name = "ls-scfg-msi",
+		.of_match_table = ls_scfg_msi_id,
+	},
+	.probe = ls_scfg_msi_probe,
+	.remove = ls_scfg_msi_remove,
+};
+
+module_platform_driver(ls_scfg_msi_driver);
+
+MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@nxp.com>");
+MODULE_DESCRIPTION("Freescale Layerscape SCFG MSI controller driver");
+MODULE_LICENSE("GPL v2");
--- a/target/linux/layerscape/patches-4.4/8061-arm64-layerscape-Enable-PCIe-for-Layerscape.patch
+++ b/target/linux/layerscape/patches-4.4/8061-arm64-layerscape-Enable-PCIe-for-Layerscape.patch
@ -0,0 +1,22 @@
+From 99b0e55881b217e9de4efd4d812dd3bd4f8c9380 Mon Sep 17 00:00:00 2001
+From: Mingkai Hu <Mingkai.Hu@freescale.com>
+Date: Thu, 19 Nov 2015 12:49:50 +0800
+Subject: [PATCH 61/70] arm64/layerscape: Enable PCIe for Layerscape
+
+Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
+Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
+---
+ arch/arm64/Kconfig.platforms |    2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
+@@ -31,6 +31,8 @@ config ARCH_EXYNOS7
+ 
+ config ARCH_LAYERSCAPE
+ 	bool "ARMv8 based Freescale Layerscape SoC family"
+	select PCI_LAYERSCAPE if PCI
+	select LS_SCFG_MSI if PCI_MSI
+ 	help
+ 	  This enables support for the Freescale Layerscape SoC family.
+ 
--- a/target/linux/layerscape/patches-4.4/8062-armv8-aarch32-enable-pci_domains-for-armv8-32bit.patch
+++ b/target/linux/layerscape/patches-4.4/8062-armv8-aarch32-enable-pci_domains-for-armv8-32bit.patch
@ -0,0 +1,20 @@
+From 53ff2bc222c446dfb6ffa9b708a23e7b8b82abb3 Mon Sep 17 00:00:00 2001
+From: Pan Jiafei <Jiafei.Pan@nxp.com>
+Date: Fri, 3 Jun 2016 06:45:57 +0000
+Subject: [PATCH 62/70] armv8: aarch32: enable pci_domains for armv8-32bit
+
+Signed-off-by: Pan Jiafei <Jiafei.Pan@nxp.com>
+---
+ arch/arm/mach-imx/Kconfig |    1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
+@@ -617,6 +617,7 @@ config ARCH_LAYERSCAPE
+ 	select ARM_GIC
+ 	select HAVE_ARM_ARCH_TIMER
+ 	select PCI_LAYERSCAPE if PCI
+	select PCI_DOMAINS if PCI
+ 	select LS1_MSI if PCI_MSI
+ 
+ 	help
--- a/target/linux/layerscape/patches-4.4/9069-Revert-arm64-simplify-dma_get_ops.patch
+++ b/target/linux/layerscape/patches-4.4/9069-Revert-arm64-simplify-dma_get_ops.patch
@ -0,0 +1,93 @@
+From 4885eb650b27f5639c8c72b8d4daa37f533b0b4d Mon Sep 17 00:00:00 2001
+From: Yutang Jiang <yutang.jiang@nxp.com>
+Date: Fri, 22 Jul 2016 01:03:29 +0800
+Subject: [PATCH 69/70] Revert "arm64: simplify dma_get_ops"
+
+This reverts commit 1dccb598df549d892b6450c261da54cdd7af44b4.
+---
+ arch/arm64/include/asm/dma-mapping.h |   13 ++++++++++---
+ arch/arm64/mm/dma-mapping.c          |   16 ++++++++++++----
+ 2 files changed, 22 insertions(+), 7 deletions(-)
+
+--- a/arch/arm64/include/asm/dma-mapping.h
+++ b/arch/arm64/include/asm/dma-mapping.h
+@@ -18,6 +18,7 @@
+ 
+ #ifdef __KERNEL__
+ 
+#include <linux/acpi.h>
+ #include <linux/types.h>
+ #include <linux/vmalloc.h>
+ 
+@@ -25,16 +26,22 @@
+ #include <asm/xen/hypervisor.h>
+ 
+ #define DMA_ERROR_CODE	(~(dma_addr_t)0)
+extern struct dma_map_ops *dma_ops;
+ extern struct dma_map_ops dummy_dma_ops;
+ 
+ static inline struct dma_map_ops *__generic_dma_ops(struct device *dev)
+ {
+-	if (dev && dev->archdata.dma_ops)
+	if (unlikely(!dev))
+		return dma_ops;
+	else if (dev->archdata.dma_ops)
+ 		return dev->archdata.dma_ops;
+	else if (acpi_disabled)
+		return dma_ops;
+ 
+ 	/*
+-	 * We expect no ISA devices, and all other DMA masters are expected to
+-	 * have someone call arch_setup_dma_ops at device creation time.
+	 * When ACPI is enabled, if arch_set_dma_ops is not called,
+	 * we will disable device DMA capability by setting it
+	 * to dummy_dma_ops.
+ 	 */
+ 	return &dummy_dma_ops;
+ }
+--- a/arch/arm64/mm/dma-mapping.c
+++ b/arch/arm64/mm/dma-mapping.c
+@@ -18,7 +18,6 @@
+  */
+ 
+ #include <linux/gfp.h>
+-#include <linux/acpi.h>
+ #include <linux/export.h>
+ #include <linux/slab.h>
+ #include <linux/genalloc.h>
+@@ -29,6 +28,9 @@
+ 
+ #include <asm/cacheflush.h>
+ 
+struct dma_map_ops *dma_ops;
+EXPORT_SYMBOL(dma_ops);
+
+ static pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot,
+ 				 bool coherent)
+ {
+@@ -513,7 +515,13 @@ EXPORT_SYMBOL(dummy_dma_ops);
+ 
+ static int __init arm64_dma_init(void)
+ {
+-	return atomic_pool_init();
+	int ret;
+
+	dma_ops = &swiotlb_dma_ops;
+
+	ret = atomic_pool_init();
+
+	return ret;
+ }
+ arch_initcall(arm64_dma_init);
+ 
+@@ -987,8 +995,8 @@ static void __iommu_setup_dma_ops(struct
+ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
+ 			struct iommu_ops *iommu, bool coherent)
+ {
+-	if (!dev->archdata.dma_ops)
+-		dev->archdata.dma_ops = &swiotlb_dma_ops;
+	if (!acpi_disabled && !dev->archdata.dma_ops)
+		dev->archdata.dma_ops = dma_ops;
+ 
+ 	dev->archdata.dma_coherent = coherent;
+ 	__iommu_setup_dma_ops(dev, dma_base, size, iommu);
--- a/target/linux/layerscape/patches-4.4/9070-Revert-arm64-use-fixmap-region-for-permanent-FDT-map.patch
+++ b/target/linux/layerscape/patches-4.4/9070-Revert-arm64-use-fixmap-region-for-permanent-FDT-map.patch
@ -0,0 +1,304 @@
+From 6f7a129e59721f6d97a0f06f7078d06f19ade69e Mon Sep 17 00:00:00 2001
+From: Yutang Jiang <yutang.jiang@nxp.com>
+Date: Thu, 21 Jul 2016 19:37:42 +0800
+Subject: [PATCH 70/70] Revert "arm64: use fixmap region for permanent FDT
+ mapping"
+
+Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
+---
+ Documentation/arm64/booting.txt |   10 +++----
+ arch/arm64/include/asm/boot.h   |   14 ----------
+ arch/arm64/include/asm/fixmap.h |   15 -----------
+ arch/arm64/include/asm/mmu.h    |    1 -
+ arch/arm64/kernel/head.S        |   39 ++++++++++++++++++++++++++-
+ arch/arm64/kernel/setup.c       |   29 +++++++++++++-------
+ arch/arm64/mm/init.c            |    1 +
+ arch/arm64/mm/mmu.c             |   57 ---------------------------------------
+ 8 files changed, 62 insertions(+), 104 deletions(-)
+ delete mode 100644 arch/arm64/include/asm/boot.h
+
+--- a/Documentation/arm64/booting.txt
+++ b/Documentation/arm64/booting.txt
+@@ -45,13 +45,11 @@ sees fit.)
+ 
+ Requirement: MANDATORY
+ 
+-The device tree blob (dtb) must be placed on an 8-byte boundary and must
+-not exceed 2 megabytes in size. Since the dtb will be mapped cacheable
+-using blocks of up to 2 megabytes in size, it must not be placed within
+-any 2M region which must be mapped with any specific attributes.
+The device tree blob (dtb) must be placed on an 8-byte boundary within
+the first 512 megabytes from the start of the kernel image and must not
+cross a 2-megabyte boundary. This is to allow the kernel to map the
+blob using a single section mapping in the initial page tables.
+ 
+-NOTE: versions prior to v4.2 also require that the DTB be placed within
+-the 512 MB region starting at text_offset bytes below the kernel Image.
+ 
+ 3. Decompress the kernel image
+ ------------------------------
+--- a/arch/arm64/include/asm/boot.h
+++ /dev/null
+@@ -1,14 +0,0 @@
+-
+-#ifndef __ASM_BOOT_H
+-#define __ASM_BOOT_H
+-
+-#include <asm/sizes.h>
+-
+-/*
+- * arm64 requires the DTB to be 8 byte aligned and
+- * not exceed 2MB in size.
+- */
+-#define MIN_FDT_ALIGN		8
+-#define MAX_FDT_SIZE		SZ_2M
+-
+-#endif
+--- a/arch/arm64/include/asm/fixmap.h
+++ b/arch/arm64/include/asm/fixmap.h
+@@ -18,7 +18,6 @@
+ #ifndef __ASSEMBLY__
+ #include <linux/kernel.h>
+ #include <linux/sizes.h>
+-#include <asm/boot.h>
+ #include <asm/page.h>
+ 
+ /*
+@@ -34,20 +33,6 @@
+  */
+ enum fixed_addresses {
+ 	FIX_HOLE,
+-
+-	/*
+-	 * Reserve a virtual window for the FDT that is 2 MB larger than the
+-	 * maximum supported size, and put it at the top of the fixmap region.
+-	 * The additional space ensures that any FDT that does not exceed
+-	 * MAX_FDT_SIZE can be mapped regardless of whether it crosses any
+-	 * 2 MB alignment boundaries.
+-	 *
+-	 * Keep this at the top so it remains 2 MB aligned.
+-	 */
+-#define FIX_FDT_SIZE		(MAX_FDT_SIZE + SZ_2M)
+-	FIX_FDT_END,
+-	FIX_FDT = FIX_FDT_END + FIX_FDT_SIZE / PAGE_SIZE - 1,
+-
+ 	FIX_EARLYCON_MEM_BASE,
+ 	FIX_TEXT_POKE0,
+ 	__end_of_permanent_fixed_addresses,
+--- a/arch/arm64/include/asm/mmu.h
+++ b/arch/arm64/include/asm/mmu.h
+@@ -34,6 +34,5 @@ extern void init_mem_pgprot(void);
+ extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys,
+ 			       unsigned long virt, phys_addr_t size,
+ 			       pgprot_t prot);
+-extern void *fixmap_remap_fdt(phys_addr_t dt_phys);
+ 
+ #endif
+--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
+@@ -212,6 +212,8 @@ ENTRY(stext)
+ 	bl	el2_setup			// Drop to EL1, w20=cpu_boot_mode
+ 	adrp	x24, __PHYS_OFFSET
+ 	bl	set_cpu_boot_mode_flag
+
+	bl	__vet_fdt
+ 	bl	__create_page_tables		// x25=TTBR0, x26=TTBR1
+ 	/*
+ 	 * The following calls CPU setup code, see arch/arm64/mm/proc.S for
+@@ -243,6 +245,24 @@ preserve_boot_args:
+ ENDPROC(preserve_boot_args)
+ 
+ /*
+ * Determine validity of the x21 FDT pointer.
+ * The dtb must be 8-byte aligned and live in the first 512M of memory.
+ */
+__vet_fdt:
+	tst	x21, #0x7
+	b.ne	1f
+	cmp	x21, x24
+	b.lt	1f
+	mov	x0, #(1 << 29)
+	add	x0, x0, x24
+	cmp	x21, x0
+	b.ge	1f
+	ret
+1:
+	mov	x21, #0
+	ret
+ENDPROC(__vet_fdt)
+/*
+  * Macro to create a table entry to the next page.
+  *
+  *	tbl:	page table address
+@@ -306,7 +326,8 @@ ENDPROC(preserve_boot_args)
+  * required to get the kernel running. The following sections are required:
+  *   - identity mapping to enable the MMU (low address, TTBR0)
+  *   - first few MB of the kernel linear mapping to jump to once the MMU has
+- *     been enabled
+ *     been enabled, including the FDT blob (TTBR1)
+ *   - pgd entry for fixed mappings (TTBR1)
+  */
+ __create_page_tables:
+ 	adrp	x25, idmap_pg_dir
+@@ -396,6 +417,22 @@ __create_page_tables:
+ 	create_block_map x0, x7, x3, x5, x6
+ 
+ 	/*
+	 * Map the FDT blob (maximum 2MB; must be within 512MB of
+	 * PHYS_OFFSET).
+	 */
+	mov	x3, x21				// FDT phys address
+	and	x3, x3, #~((1 << 21) - 1)	// 2MB aligned
+	mov	x6, #PAGE_OFFSET
+	sub	x5, x3, x24			// subtract PHYS_OFFSET
+	tst	x5, #~((1 << 29) - 1)		// within 512MB?
+	csel	x21, xzr, x21, ne		// zero the FDT pointer
+	b.ne	1f
+	add	x5, x5, x6			// __va(FDT blob)
+	add	x6, x5, #1 << 21		// 2MB for the FDT blob
+	sub	x6, x6, #1			// inclusive range
+	create_block_map x0, x7, x3, x5, x6
+1:
+	/*
+ 	 * Since the page tables have been populated with non-cacheable
+ 	 * accesses (MMU disabled), invalidate the idmap and swapper page
+ 	 * tables again to remove any speculatively loaded cache lines.
+--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
+@@ -87,6 +87,18 @@ static struct resource mem_res[] = {
+ #define kernel_code mem_res[0]
+ #define kernel_data mem_res[1]
+ 
+void __init early_print(const char *str, ...)
+{
+	char buf[256];
+	va_list ap;
+
+	va_start(ap, str);
+	vsnprintf(buf, sizeof(buf), str, ap);
+	va_end(ap);
+
+	printk("%s", buf);
+}
+
+ /*
+  * The recorded values of x0 .. x3 upon kernel entry.
+  */
+@@ -180,14 +192,12 @@ static void __init smp_build_mpidr_hash(
+ 
+ static void __init setup_machine_fdt(phys_addr_t dt_phys)
+ {
+-	void *dt_virt = fixmap_remap_fdt(dt_phys);
+-
+-	if (!dt_virt || !early_init_dt_scan(dt_virt)) {
+-		pr_crit("\n"
+-			"Error: invalid device tree blob at physical address %pa (virtual address 0x%p)\n"
+-			"The dtb must be 8-byte aligned and must not exceed 2 MB in size\n"
+-			"\nPlease check your bootloader.",
+-			&dt_phys, dt_virt);
+	if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) {
+		early_print("\n"
+			"Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n"
+			"The dtb must be 8-byte aligned and passed in the first 512MB of memory\n"
+			"\nPlease check your bootloader.\n",
+			dt_phys, phys_to_virt(dt_phys));
+ 
+ 		while (true)
+ 			cpu_relax();
+@@ -294,6 +304,7 @@ void __init setup_arch(char **cmdline_p)
+ 	pr_info("Boot CPU: AArch64 Processor [%08x]\n", read_cpuid_id());
+ 
+ 	sprintf(init_utsname()->machine, ELF_PLATFORM);
+	setup_machine_fdt(__fdt_pointer);
+ 	init_mm.start_code = (unsigned long) _text;
+ 	init_mm.end_code   = (unsigned long) _etext;
+ 	init_mm.end_data   = (unsigned long) _edata;
+@@ -304,8 +315,6 @@ void __init setup_arch(char **cmdline_p)
+ 	early_fixmap_init();
+ 	early_ioremap_init();
+ 
+-	setup_machine_fdt(__fdt_pointer);
+-
+ 	parse_early_param();
+ 
+ 	/*
+--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
+@@ -171,6 +171,7 @@ void __init arm64_memblock_init(void)
+ 		memblock_reserve(__virt_to_phys(initrd_start), initrd_end - initrd_start);
+ #endif
+ 
+	early_init_fdt_reserve_self();
+ 	early_init_fdt_scan_reserved_mem();
+ 
+ 	/* 4GB maximum for 32-bit only capable devices */
+--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
+@@ -21,7 +21,6 @@
+ #include <linux/kernel.h>
+ #include <linux/errno.h>
+ #include <linux/init.h>
+-#include <linux/libfdt.h>
+ #include <linux/mman.h>
+ #include <linux/nodemask.h>
+ #include <linux/memblock.h>
+@@ -641,59 +640,3 @@ void __set_fixmap(enum fixed_addresses i
+ 		flush_tlb_kernel_range(addr, addr+PAGE_SIZE);
+ 	}
+ }
+-
+-void *__init fixmap_remap_fdt(phys_addr_t dt_phys)
+-{
+-	const u64 dt_virt_base = __fix_to_virt(FIX_FDT);
+-	pgprot_t prot = PAGE_KERNEL_RO;
+-	int size, offset;
+-	void *dt_virt;
+-
+-	/*
+-	 * Check whether the physical FDT address is set and meets the minimum
+-	 * alignment requirement. Since we are relying on MIN_FDT_ALIGN to be
+-	 * at least 8 bytes so that we can always access the magic and size
+-	 * fields of the FDT header after mapping the first chunk, double check
+-	 * here if that is indeed the case.
+-	 */
+-	BUILD_BUG_ON(MIN_FDT_ALIGN < 8);
+-	if (!dt_phys || dt_phys % MIN_FDT_ALIGN)
+-		return NULL;
+-
+-	/*
+-	 * Make sure that the FDT region can be mapped without the need to
+-	 * allocate additional translation table pages, so that it is safe
+-	 * to call create_mapping() this early.
+-	 *
+-	 * On 64k pages, the FDT will be mapped using PTEs, so we need to
+-	 * be in the same PMD as the rest of the fixmap.
+-	 * On 4k pages, we'll use section mappings for the FDT so we only
+-	 * have to be in the same PUD.
+-	 */
+-	BUILD_BUG_ON(dt_virt_base % SZ_2M);
+-
+-	BUILD_BUG_ON(__fix_to_virt(FIX_FDT_END) >> SWAPPER_TABLE_SHIFT !=
+-		     __fix_to_virt(FIX_BTMAP_BEGIN) >> SWAPPER_TABLE_SHIFT);
+-
+-	offset = dt_phys % SWAPPER_BLOCK_SIZE;
+-	dt_virt = (void *)dt_virt_base + offset;
+-
+-	/* map the first chunk so we can read the size from the header */
+-	create_mapping(round_down(dt_phys, SWAPPER_BLOCK_SIZE), dt_virt_base,
+-		       SWAPPER_BLOCK_SIZE, prot);
+-
+-	if (fdt_magic(dt_virt) != FDT_MAGIC)
+-		return NULL;
+-
+-	size = fdt_totalsize(dt_virt);
+-	if (size > MAX_FDT_SIZE)
+-		return NULL;
+-
+-	if (offset + size > SWAPPER_BLOCK_SIZE)
+-		create_mapping(round_down(dt_phys, SWAPPER_BLOCK_SIZE), dt_virt_base,
+-			       round_up(offset + size, SWAPPER_BLOCK_SIZE), prot);
+-
+-	memblock_reserve(dt_phys, size);
+-
+-	return dt_virt;
+-}