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250 lines
7.5 KiB
Diff
250 lines
7.5 KiB
Diff
From f0c3f31a8bd81b8e7354a187c49200f3ce52740d Mon Sep 17 00:00:00 2001
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From: Joao Pinto <Joao.Pinto@synopsys.com>
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Date: Thu, 10 Mar 2016 14:44:35 -0600
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Subject: [PATCH 56/70] PCI: designware: Add generic dw_pcie_wait_for_link()
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commit 886bc5ceb5cc3ad4b219502d72b277e3c3255a32 upstream
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[context adjustment]
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[remove drivers/pci/host/pcie-qcom.c related changes]
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Several DesignWare-based drivers (dra7xx, exynos, imx6, keystone, qcom, and
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spear13xx) had similar loops waiting for the link to come up.
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Add a generic dw_pcie_wait_for_link() for use by all these drivers so the
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waiting is done consistently, e.g., always using usleep_range() rather than
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mdelay() and using similar timeouts and retry counts.
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Note that this changes the Keystone link training/wait for link strategy,
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so we initiate link training, then wait longer for the link to come up
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before re-initiating link training.
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[bhelgaas: changelog, split into its own patch, update pci-keystone.c, pcie-qcom.c]
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Signed-off-by: Joao Pinto <jpinto@synopsys.com>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
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Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
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---
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drivers/pci/host/pci-dra7xx.c | 11 +----------
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drivers/pci/host/pci-exynos.c | 13 +++----------
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drivers/pci/host/pci-imx6.c | 13 ++++---------
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drivers/pci/host/pci-keystone.c | 10 ++++------
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drivers/pci/host/pcie-designware.c | 19 +++++++++++++++++++
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drivers/pci/host/pcie-designware.h | 6 ++++++
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drivers/pci/host/pcie-spear13xx.c | 14 +-------------
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7 files changed, 38 insertions(+), 48 deletions(-)
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--- a/drivers/pci/host/pci-dra7xx.c
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+++ b/drivers/pci/host/pci-dra7xx.c
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@@ -10,7 +10,6 @@
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* published by the Free Software Foundation.
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*/
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-#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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@@ -108,7 +107,6 @@ static int dra7xx_pcie_establish_link(st
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{
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struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
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u32 reg;
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- unsigned int retries;
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if (dw_pcie_link_up(pp)) {
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dev_err(pp->dev, "link is already up\n");
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@@ -119,14 +117,7 @@ static int dra7xx_pcie_establish_link(st
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reg |= LTSSM_EN;
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dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
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- for (retries = 0; retries < 1000; retries++) {
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- if (dw_pcie_link_up(pp))
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- return 0;
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- usleep_range(10, 20);
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- }
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-
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- dev_err(pp->dev, "link is not up\n");
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- return -EINVAL;
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+ return dw_pcie_wait_for_link(pp);
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}
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static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp)
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--- a/drivers/pci/host/pci-exynos.c
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+++ b/drivers/pci/host/pci-exynos.c
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@@ -318,7 +318,6 @@ static int exynos_pcie_establish_link(st
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{
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
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u32 val;
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- unsigned int retries;
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if (dw_pcie_link_up(pp)) {
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dev_err(pp->dev, "Link already up\n");
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@@ -357,13 +356,8 @@ static int exynos_pcie_establish_link(st
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PCIE_APP_LTSSM_ENABLE);
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/* check if the link is up or not */
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- for (retries = 0; retries < 10; retries++) {
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- if (dw_pcie_link_up(pp)) {
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- dev_info(pp->dev, "Link up\n");
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- return 0;
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- }
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- mdelay(100);
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- }
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+ if (!dw_pcie_wait_for_link(pp))
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+ return 0;
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while (exynos_phy_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED) == 0) {
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val = exynos_blk_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED);
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@@ -372,8 +366,7 @@ static int exynos_pcie_establish_link(st
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/* power off phy */
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exynos_pcie_power_off_phy(pp);
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- dev_err(pp->dev, "PCIe Link Fail\n");
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- return -EINVAL;
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+ return -ETIMEDOUT;
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}
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static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp)
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--- a/drivers/pci/host/pci-imx6.c
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+++ b/drivers/pci/host/pci-imx6.c
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@@ -330,19 +330,14 @@ static void imx6_pcie_init_phy(struct pc
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static int imx6_pcie_wait_for_link(struct pcie_port *pp)
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{
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- unsigned int retries;
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+ /* check if the link is up or not */
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+ if (!dw_pcie_wait_for_link(pp))
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+ return 0;
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- for (retries = 0; retries < 200; retries++) {
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- if (dw_pcie_link_up(pp))
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- return 0;
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- usleep_range(100, 1000);
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- }
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-
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- dev_err(pp->dev, "phy link never came up\n");
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dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
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readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
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readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
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- return -EINVAL;
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+ return -ETIMEDOUT;
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}
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static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp)
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--- a/drivers/pci/host/pci-keystone.c
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+++ b/drivers/pci/host/pci-keystone.c
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@@ -97,17 +97,15 @@ static int ks_pcie_establish_link(struct
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return 0;
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}
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- ks_dw_pcie_initiate_link_train(ks_pcie);
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/* check if the link is up or not */
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- for (retries = 0; retries < 200; retries++) {
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- if (dw_pcie_link_up(pp))
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- return 0;
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- usleep_range(100, 1000);
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+ for (retries = 0; retries < 5; retries++) {
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ks_dw_pcie_initiate_link_train(ks_pcie);
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+ if (!dw_pcie_wait_for_link(pp))
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+ return 0;
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}
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dev_err(pp->dev, "phy link never came up\n");
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- return -EINVAL;
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+ return -ETIMEDOUT;
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}
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static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
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--- a/drivers/pci/host/pcie-designware.c
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+++ b/drivers/pci/host/pcie-designware.c
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@@ -22,6 +22,7 @@
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#include <linux/pci_regs.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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+#include <linux/delay.h>
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#include "pcie-designware.h"
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@@ -380,6 +381,24 @@ static struct msi_controller dw_pcie_msi
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.teardown_irq = dw_msi_teardown_irq,
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};
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+int dw_pcie_wait_for_link(struct pcie_port *pp)
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+{
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+ int retries;
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+
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+ /* check if the link is up or not */
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+ for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
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+ if (dw_pcie_link_up(pp)) {
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+ dev_info(pp->dev, "link up\n");
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+ return 0;
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+ }
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+ usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
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+ }
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+
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+ dev_err(pp->dev, "phy link never came up\n");
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+
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+ return -ETIMEDOUT;
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+}
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+
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int dw_pcie_link_up(struct pcie_port *pp)
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{
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if (pp->ops->link_up)
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--- a/drivers/pci/host/pcie-designware.h
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+++ b/drivers/pci/host/pcie-designware.h
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@@ -22,6 +22,11 @@
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#define MAX_MSI_IRQS 32
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#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
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+/* Parameters for the waiting for link up routine */
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+#define LINK_WAIT_MAX_RETRIES 10
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+#define LINK_WAIT_USLEEP_MIN 90000
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+#define LINK_WAIT_USLEEP_MAX 100000
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+
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struct pcie_port {
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struct device *dev;
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u8 root_bus_nr;
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@@ -76,6 +81,7 @@ int dw_pcie_cfg_read(void __iomem *addr,
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int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val);
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irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
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void dw_pcie_msi_init(struct pcie_port *pp);
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+int dw_pcie_wait_for_link(struct pcie_port *pp);
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int dw_pcie_link_up(struct pcie_port *pp);
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void dw_pcie_setup_rc(struct pcie_port *pp);
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int dw_pcie_host_init(struct pcie_port *pp);
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--- a/drivers/pci/host/pcie-spear13xx.c
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+++ b/drivers/pci/host/pcie-spear13xx.c
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@@ -13,7 +13,6 @@
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*/
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#include <linux/clk.h>
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-#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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@@ -149,7 +148,6 @@ static int spear13xx_pcie_establish_link
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struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
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struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
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u32 exp_cap_off = EXP_CAP_ID_OFFSET;
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- unsigned int retries;
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if (dw_pcie_link_up(pp)) {
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dev_err(pp->dev, "link already up\n");
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@@ -200,17 +198,7 @@ static int spear13xx_pcie_establish_link
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| ((u32)1 << REG_TRANSLATION_ENABLE),
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&app_reg->app_ctrl_0);
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- /* check if the link is up or not */
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- for (retries = 0; retries < 10; retries++) {
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- if (dw_pcie_link_up(pp)) {
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- dev_info(pp->dev, "link up\n");
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- return 0;
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- }
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- mdelay(100);
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- }
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-
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- dev_err(pp->dev, "link Fail\n");
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- return -EINVAL;
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+ return dw_pcie_wait_for_link(pp);
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}
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static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
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