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290 lines
9.3 KiB
Diff
290 lines
9.3 KiB
Diff
From c2d0a12b5cfa61e43494483f5d1ee466b4998830 Mon Sep 17 00:00:00 2001
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From: Liu Gang <Gang.Liu@nxp.com>
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Date: Thu, 14 Jan 2016 19:48:09 +0800
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Subject: [PATCH 42/70] drivers/gpio: Port gpio driver to support layerscape
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platform
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Layerscape has the same ip block/controller as
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GPIO on powerpc platform(MPC8XXX).
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So use portable i/o accessors, as in_be32/out_be32
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accessors are Power architecture specific whereas
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ioread32/iowrite32 and ioread32be/iowrite32be are
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available in other architectures.
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Layerscape GPIO controller's registers may be big
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or little endian, so the code needs to get the
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endian property from DTB, then make additional
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functions to fit right register read/write
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operations.
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Currently the code can support ls2080a GPIO with
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little endian registers. And it can also work well
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on other layerscape platform with big endian GPIO
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registers.
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Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
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---
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drivers/gpio/Kconfig | 7 ++--
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drivers/gpio/gpio-mpc8xxx.c | 87 +++++++++++++++++++++++++++++++------------
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2 files changed, 68 insertions(+), 26 deletions(-)
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--- a/drivers/gpio/Kconfig
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+++ b/drivers/gpio/Kconfig
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@@ -281,12 +281,13 @@ config GPIO_MPC5200
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depends on PPC_MPC52xx
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config GPIO_MPC8XXX
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- bool "MPC512x/MPC8xxx GPIO support"
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+ bool "MPC512x/MPC8xxx/QorIQ GPIO support"
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depends on PPC_MPC512x || PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || \
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- FSL_SOC_BOOKE || PPC_86xx
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+ FSL_SOC_BOOKE || PPC_86xx || ARCH_LAYERSCAPE || ARM || \
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+ COMPILE_TEST
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help
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Say Y here if you're going to use hardware that connects to the
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- MPC512x/831x/834x/837x/8572/8610 GPIOs.
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+ MPC512x/831x/834x/837x/8572/8610/QorIQ GPIOs.
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config GPIO_MVEBU
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def_bool y
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--- a/drivers/gpio/gpio-mpc8xxx.c
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+++ b/drivers/gpio/gpio-mpc8xxx.c
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@@ -1,5 +1,5 @@
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/*
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- * GPIOs on MPC512x/8349/8572/8610 and compatible
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+ * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
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*
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* Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
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*
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@@ -19,6 +19,7 @@
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/irq.h>
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+#include <linux/irqdomain.h>
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#define MPC8XXX_GPIO_PINS 32
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@@ -44,6 +45,27 @@ struct mpc8xxx_gpio_chip {
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const void *of_dev_id_data;
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};
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+static bool gpio_little_endian;
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+static inline u32 gpio_in32(void __iomem *addr)
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+{
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+ u32 val;
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+
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+ if (gpio_little_endian)
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+ val = ioread32(addr);
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+ else
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+ val = ioread32be(addr);
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+
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+ return val;
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+}
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+
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+static inline void gpio_out32(u32 val, void __iomem *addr)
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+{
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+ if (gpio_little_endian)
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+ iowrite32(val, addr);
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+ else
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+ iowrite32be(val, addr);
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+}
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+
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static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
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{
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return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
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@@ -59,9 +81,17 @@ static void mpc8xxx_gpio_save_regs(struc
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
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- mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
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+ mpc8xxx_gc->data = gpio_in32(mm->regs + GPIO_DAT);
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}
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+/* Generic set and clear bits accessor ports */
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+#define bgpio_setbits32(_addr, _v) \
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+ gpio_out32(gpio_in32(_addr) | (_v), (_addr))
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+#define bgpio_clrbits32(_addr, _v) \
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+ gpio_out32(gpio_in32(_addr) & ~(_v), (_addr))
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+#define bgpio_clrsetbits32(addr, clear, set) \
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+ gpio_out32((gpio_in32(addr) & ~(clear)) | (set), (addr))
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+
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/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
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* defined as output cannot be determined by reading GPDAT register,
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* so we use shadow data register instead. The status of input pins
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@@ -74,9 +104,9 @@ static int mpc8572_gpio_get(struct gpio_
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
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u32 out_mask, out_shadow;
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- out_mask = in_be32(mm->regs + GPIO_DIR);
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+ out_mask = gpio_in32(mm->regs + GPIO_DIR);
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- val = in_be32(mm->regs + GPIO_DAT) & ~out_mask;
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+ val = gpio_in32(mm->regs + GPIO_DAT) & ~out_mask;
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out_shadow = mpc8xxx_gc->data & out_mask;
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return (val | out_shadow) & mpc8xxx_gpio2mask(gpio);
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@@ -86,7 +116,7 @@ static int mpc8xxx_gpio_get(struct gpio_
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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- return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
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+ return gpio_in32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
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}
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static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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@@ -102,7 +132,7 @@ static void mpc8xxx_gpio_set(struct gpio
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else
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mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
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- out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
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+ gpio_out32(mpc8xxx_gc->data, mm->regs + GPIO_DAT);
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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@@ -128,7 +158,7 @@ static void mpc8xxx_gpio_set_multiple(st
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}
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}
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- out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
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+ gpio_out32(mpc8xxx_gc->data, mm->regs + GPIO_DAT);
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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@@ -141,7 +171,7 @@ static int mpc8xxx_gpio_dir_in(struct gp
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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- clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
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+ bgpio_clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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@@ -158,7 +188,7 @@ static int mpc8xxx_gpio_dir_out(struct g
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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- setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
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+ bgpio_setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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@@ -201,7 +231,8 @@ static void mpc8xxx_gpio_irq_cascade(str
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned int mask;
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- mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
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+ mask = gpio_in32(mm->regs + GPIO_IER)
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+ & gpio_in32(mm->regs + GPIO_IMR);
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if (mask)
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generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
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32 - ffs(mask)));
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@@ -217,7 +248,8 @@ static void mpc8xxx_irq_unmask(struct ir
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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- setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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+ bgpio_setbits32(mm->regs + GPIO_IMR,
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+ mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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@@ -230,7 +262,8 @@ static void mpc8xxx_irq_mask(struct irq_
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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- clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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+ bgpio_clrbits32(mm->regs + GPIO_IMR,
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+ mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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@@ -240,7 +273,7 @@ static void mpc8xxx_irq_ack(struct irq_d
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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- out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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+ gpio_out32(mpc8xxx_gpio2mask(irqd_to_hwirq(d)), mm->regs + GPIO_IER);
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}
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static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
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@@ -252,15 +285,15 @@ static int mpc8xxx_irq_set_type(struct i
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switch (flow_type) {
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case IRQ_TYPE_EDGE_FALLING:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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- setbits32(mm->regs + GPIO_ICR,
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- mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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+ bgpio_setbits32(mm->regs + GPIO_ICR,
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+ mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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- clrbits32(mm->regs + GPIO_ICR,
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- mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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+ bgpio_clrbits32(mm->regs + GPIO_ICR,
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+ mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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@@ -292,20 +325,20 @@ static int mpc512x_irq_set_type(struct i
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_LEVEL_LOW:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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- clrsetbits_be32(reg, 3 << shift, 2 << shift);
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+ bgpio_clrsetbits32(reg, 3 << shift, 2 << shift);
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_LEVEL_HIGH:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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- clrsetbits_be32(reg, 3 << shift, 1 << shift);
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+ bgpio_clrsetbits32(reg, 3 << shift, 1 << shift);
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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- clrbits32(reg, 3 << shift);
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+ bgpio_clrbits32(reg, 3 << shift);
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raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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@@ -398,6 +431,14 @@ static int mpc8xxx_probe(struct platform
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mm_gc = &mpc8xxx_gc->mm_gc;
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gc = &mm_gc->gc;
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+ if (of_property_read_bool(np, "little-endian")) {
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+ gpio_little_endian = true;
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+ dev_dbg(&pdev->dev, "GPIO REGISTERS are LITTLE endian\n");
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+ } else {
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+ gpio_little_endian = false;
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+ dev_dbg(&pdev->dev, "GPIO REGISTERS are BIG endian\n");
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+ }
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+
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mm_gc->save_regs = mpc8xxx_gpio_save_regs;
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gc->ngpio = MPC8XXX_GPIO_PINS;
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gc->direction_input = mpc8xxx_gpio_dir_in;
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@@ -422,7 +463,7 @@ static int mpc8xxx_probe(struct platform
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return ret;
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mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
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- if (mpc8xxx_gc->irqn == NO_IRQ)
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+ if (mpc8xxx_gc->irqn == 0)
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return 0;
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mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
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@@ -435,8 +476,8 @@ static int mpc8xxx_probe(struct platform
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mpc8xxx_gc->of_dev_id_data = id->data;
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/* ack and mask all irqs */
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- out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
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- out_be32(mm_gc->regs + GPIO_IMR, 0);
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+ gpio_out32(0xffffffff, mm_gc->regs + GPIO_IER);
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+ gpio_out32(0, mm_gc->regs + GPIO_IMR);
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irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
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mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);
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