ath79: replace patches
replace our downstream version of the patches with the ones that were sent upstream. Signed-off-by: John Crispin <john@phrozen.org>v19.07.3_mercusys_ac12_duma
John Crispin
6 years ago
parent
af6e901ae8
commit
9300eda00f
@ -0,0 +1,400 @@
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From 2741304648dbdab7697d7758166a582b5291c53d Mon Sep 17 00:00:00 2001
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From: Matthias Schiffer <mschiffer@universe-factory.net>
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Date: Sat, 23 Jun 2018 15:08:56 +0200
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Subject: [PATCH 10/33] MIPS: ath79: add support for QCA953x QCA956x TP9343
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This patch adds support for 2 new types of QCA silicon. TP9343 is
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essentially the same as the QCA956X but is licensed by TPLink.
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Signed-off-by: Weijie Gao <hackpascal@gmail.com>
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Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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arch/mips/ath79/clock.c | 193 +++++++++++++++++++++++++++++++
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arch/mips/ath79/common.c | 8 ++
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arch/mips/ath79/early_printk.c | 4 +
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arch/mips/ath79/setup.c | 34 +++++-
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arch/mips/include/asm/mach-ath79/ath79.h | 33 ++++++
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5 files changed, 269 insertions(+), 3 deletions(-)
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -355,6 +355,91 @@ static void __init ar934x_clocks_init(vo
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iounmap(dpll_base);
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}
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+static void __init qca953x_clocks_init(void)
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+{
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+ unsigned long ref_rate;
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+ unsigned long cpu_rate;
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+ unsigned long ddr_rate;
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+ unsigned long ahb_rate;
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+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
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+ u32 cpu_pll, ddr_pll;
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+ u32 bootstrap;
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+
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+ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
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+ if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
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+ ref_rate = 40 * 1000 * 1000;
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+ else
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+ ref_rate = 25 * 1000 * 1000;
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+
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+ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
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+ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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+ QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
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+ ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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+ QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
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+ nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
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+ QCA953X_PLL_CPU_CONFIG_NINT_MASK;
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+ frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
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+ QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
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+
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+ cpu_pll = nint * ref_rate / ref_div;
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+ cpu_pll += frac * (ref_rate >> 6) / ref_div;
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+ cpu_pll /= (1 << out_div);
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+
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+ pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
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+ out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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+ QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
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+ ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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+ QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
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+ nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
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+ QCA953X_PLL_DDR_CONFIG_NINT_MASK;
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+ frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
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+ QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
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+
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+ ddr_pll = nint * ref_rate / ref_div;
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+ ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
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+ ddr_pll /= (1 << out_div);
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+
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+ clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
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+
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+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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+ QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
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+ cpu_rate = ref_rate;
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+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
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+ cpu_rate = cpu_pll / (postdiv + 1);
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+ else
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+ cpu_rate = ddr_pll / (postdiv + 1);
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+
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+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
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+ QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
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+ ddr_rate = ref_rate;
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+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
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+ ddr_rate = ddr_pll / (postdiv + 1);
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+ else
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+ ddr_rate = cpu_pll / (postdiv + 1);
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+
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+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
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+ QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
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+ ahb_rate = ref_rate;
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+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
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+ ahb_rate = ddr_pll / (postdiv + 1);
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+ else
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+ ahb_rate = cpu_pll / (postdiv + 1);
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+
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+ ath79_add_sys_clkdev("ref", ref_rate);
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+ ath79_add_sys_clkdev("cpu", cpu_rate);
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+ ath79_add_sys_clkdev("ddr", ddr_rate);
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+ ath79_add_sys_clkdev("ahb", ahb_rate);
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+
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+ clk_add_alias("wdt", NULL, "ref", NULL);
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+ clk_add_alias("uart", NULL, "ref", NULL);
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+}
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+
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static void __init qca955x_clocks_init(void)
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{
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unsigned long ref_rate;
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@@ -440,6 +525,110 @@ static void __init qca955x_clocks_init(v
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clk_add_alias("uart", NULL, "ref", NULL);
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}
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+static void __init qca956x_clocks_init(void)
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+{
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+ unsigned long ref_rate;
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+ unsigned long cpu_rate;
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+ unsigned long ddr_rate;
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+ unsigned long ahb_rate;
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+ u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
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+ u32 cpu_pll, ddr_pll;
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+ u32 bootstrap;
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+
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+ /*
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+ * QCA956x timer init workaround has to be applied right before setting
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+ * up the clock. Else, there will be no jiffies
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+ */
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+ u32 misc;
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+
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+ misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
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+ misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
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+ ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
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+
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+ bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
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+ if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
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+ ref_rate = 40 * 1000 * 1000;
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+ else
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+ ref_rate = 25 * 1000 * 1000;
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+
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+ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
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+ out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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+ QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
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+ ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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+ QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
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+
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+ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
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+ nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
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+ QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
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+ hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
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+ QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
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+ lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
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+ QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
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+
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+ cpu_pll = nint * ref_rate / ref_div;
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+ cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
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+ cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
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+ cpu_pll /= (1 << out_div);
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+
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+ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
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+ out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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+ QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
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+ ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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+ QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
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+ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
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+ nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
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+ QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
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+ hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
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+ QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
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+ lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
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+ QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
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+
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+ ddr_pll = nint * ref_rate / ref_div;
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+ ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
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+ ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
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+ ddr_pll /= (1 << out_div);
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+
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+ clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
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+
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+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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+ QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
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+ cpu_rate = ref_rate;
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+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
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+ cpu_rate = ddr_pll / (postdiv + 1);
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+ else
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+ cpu_rate = cpu_pll / (postdiv + 1);
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+
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+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
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+ QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
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+ ddr_rate = ref_rate;
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+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
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+ ddr_rate = cpu_pll / (postdiv + 1);
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+ else
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+ ddr_rate = ddr_pll / (postdiv + 1);
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+
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+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
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+ QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
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+ ahb_rate = ref_rate;
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+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
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+ ahb_rate = ddr_pll / (postdiv + 1);
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+ else
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+ ahb_rate = cpu_pll / (postdiv + 1);
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+
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+ ath79_add_sys_clkdev("ref", ref_rate);
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+ ath79_add_sys_clkdev("cpu", cpu_rate);
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+ ath79_add_sys_clkdev("ddr", ddr_rate);
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+ ath79_add_sys_clkdev("ahb", ahb_rate);
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+
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+ clk_add_alias("wdt", NULL, "ref", NULL);
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+ clk_add_alias("uart", NULL, "ref", NULL);
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+}
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+
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void __init ath79_clocks_init(void)
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{
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if (soc_is_ar71xx())
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@@ -450,8 +639,12 @@ void __init ath79_clocks_init(void)
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ar933x_clocks_init();
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else if (soc_is_ar934x())
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ar934x_clocks_init();
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+ else if (soc_is_qca953x())
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+ qca953x_clocks_init();
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else if (soc_is_qca955x())
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qca955x_clocks_init();
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+ else if (soc_is_qca956x() || soc_is_tp9343())
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+ qca956x_clocks_init();
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else
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BUG();
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}
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--- a/arch/mips/ath79/common.c
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+++ b/arch/mips/ath79/common.c
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@@ -103,8 +103,12 @@ void ath79_device_reset_set(u32 mask)
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reg = AR933X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar934x())
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reg = AR934X_RESET_REG_RESET_MODULE;
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+ else if (soc_is_qca953x())
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+ reg = QCA953X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_RESET_MODULE;
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+ else if (soc_is_qca956x() || soc_is_tp9343())
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+ reg = QCA956X_RESET_REG_RESET_MODULE;
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else
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BUG();
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@@ -131,8 +135,12 @@ void ath79_device_reset_clear(u32 mask)
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reg = AR933X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar934x())
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reg = AR934X_RESET_REG_RESET_MODULE;
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+ else if (soc_is_qca953x())
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+ reg = QCA953X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_RESET_MODULE;
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+ else if (soc_is_qca956x() || soc_is_tp9343())
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+ reg = QCA956X_RESET_REG_RESET_MODULE;
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else
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BUG();
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--- a/arch/mips/ath79/early_printk.c
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+++ b/arch/mips/ath79/early_printk.c
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@@ -76,8 +76,12 @@ static void prom_putchar_init(void)
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case REV_ID_MAJOR_AR9341:
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case REV_ID_MAJOR_AR9342:
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case REV_ID_MAJOR_AR9344:
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+ case REV_ID_MAJOR_QCA9533:
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+ case REV_ID_MAJOR_QCA9533_V2:
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case REV_ID_MAJOR_QCA9556:
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case REV_ID_MAJOR_QCA9558:
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+ case REV_ID_MAJOR_TP9343:
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+ case REV_ID_MAJOR_QCA956X:
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_prom_putchar = prom_putchar_ar71xx;
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break;
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--- a/arch/mips/ath79/setup.c
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+++ b/arch/mips/ath79/setup.c
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@@ -59,6 +59,7 @@ static void __init ath79_detect_sys_type
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u32 major;
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u32 minor;
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u32 rev = 0;
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+ u32 ver = 1;
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id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
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major = id & REV_ID_MAJOR_MASK;
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@@ -151,6 +152,17 @@ static void __init ath79_detect_sys_type
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rev = id & AR934X_REV_ID_REVISION_MASK;
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break;
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+ case REV_ID_MAJOR_QCA9533_V2:
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+ ver = 2;
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+ ath79_soc_rev = 2;
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+ /* drop through */
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+
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+ case REV_ID_MAJOR_QCA9533:
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+ ath79_soc = ATH79_SOC_QCA9533;
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+ chip = "9533";
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+ rev = id & QCA953X_REV_ID_REVISION_MASK;
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+ break;
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+
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case REV_ID_MAJOR_QCA9556:
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ath79_soc = ATH79_SOC_QCA9556;
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chip = "9556";
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@@ -163,14 +175,30 @@ static void __init ath79_detect_sys_type
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rev = id & QCA955X_REV_ID_REVISION_MASK;
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break;
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+ case REV_ID_MAJOR_QCA956X:
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+ ath79_soc = ATH79_SOC_QCA956X;
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+ chip = "956X";
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+ rev = id & QCA956X_REV_ID_REVISION_MASK;
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+ break;
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+
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+ case REV_ID_MAJOR_TP9343:
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+ ath79_soc = ATH79_SOC_TP9343;
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+ chip = "9343";
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+ rev = id & QCA956X_REV_ID_REVISION_MASK;
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+ break;
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+
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default:
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panic("ath79: unknown SoC, id:0x%08x", id);
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}
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- ath79_soc_rev = rev;
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+ if (ver == 1)
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+ ath79_soc_rev = rev;
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- if (soc_is_qca955x())
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- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
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+ if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
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+ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
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+ chip, ver, rev);
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+ else if (soc_is_tp9343())
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+ sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
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chip, rev);
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else
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sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
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--- a/arch/mips/include/asm/mach-ath79/ath79.h
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+++ b/arch/mips/include/asm/mach-ath79/ath79.h
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@@ -32,8 +32,11 @@ enum ath79_soc_type {
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ATH79_SOC_AR9341,
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ATH79_SOC_AR9342,
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ATH79_SOC_AR9344,
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+ ATH79_SOC_QCA9533,
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ATH79_SOC_QCA9556,
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ATH79_SOC_QCA9558,
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+ ATH79_SOC_TP9343,
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+ ATH79_SOC_QCA956X,
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};
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extern enum ath79_soc_type ath79_soc;
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@@ -100,6 +103,16 @@ static inline int soc_is_ar934x(void)
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return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
|
||||
}
|
||||
|
||||
+static inline int soc_is_qca9533(void)
|
||||
+{
|
||||
+ return ath79_soc == ATH79_SOC_QCA9533;
|
||||
+}
|
||||
+
|
||||
+static inline int soc_is_qca953x(void)
|
||||
+{
|
||||
+ return soc_is_qca9533();
|
||||
+}
|
||||
+
|
||||
static inline int soc_is_qca9556(void)
|
||||
{
|
||||
return ath79_soc == ATH79_SOC_QCA9556;
|
||||
@@ -115,6 +128,26 @@ static inline int soc_is_qca955x(void)
|
||||
return soc_is_qca9556() || soc_is_qca9558();
|
||||
}
|
||||
|
||||
+static inline int soc_is_tp9343(void)
|
||||
+{
|
||||
+ return ath79_soc == ATH79_SOC_TP9343;
|
||||
+}
|
||||
+
|
||||
+static inline int soc_is_qca9561(void)
|
||||
+{
|
||||
+ return ath79_soc == ATH79_SOC_QCA956X;
|
||||
+}
|
||||
+
|
||||
+static inline int soc_is_qca9563(void)
|
||||
+{
|
||||
+ return ath79_soc == ATH79_SOC_QCA956X;
|
||||
+}
|
||||
+
|
||||
+static inline int soc_is_qca956x(void)
|
||||
+{
|
||||
+ return soc_is_qca9561() || soc_is_qca9563();
|
||||
+}
|
||||
+
|
||||
void ath79_ddr_wb_flush(unsigned int reg);
|
||||
void ath79_ddr_set_pci_windows(void);
|
||||
|
||||
@ -1,7 +1,11 @@
|
||||
From f3d5027255ef0752ed12b65c3bf7eb363fc3c096 Mon Sep 17 00:00:00 2001
|
||||
From 0c8856211d26f84277f7fcb0b9595e5c646bc464 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <john@phrozen.org>
|
||||
Date: Tue, 6 Mar 2018 10:00:55 +0100
|
||||
Subject: [PATCH 10/27] MIPS: ath79: select the PINCTRL subsystem
|
||||
Subject: [PATCH 11/33] MIPS: ath79: select the PINCTRL subsystem
|
||||
|
||||
The pinmux on QCA SoCs is controlled by a single register. The
|
||||
"pinctrl-single" driver can be used but requires the target
|
||||
to select PINCTRL.
|
||||
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
---
|
||||
@ -1,42 +0,0 @@
|
||||
From ac3a5ee699f3baa7654c93a3ffda46be82443344 Mon Sep 17 00:00:00 2001
|
||||
From: Markos Chandras <markos.chandras@imgtec.com>
|
||||
Date: Wed, 21 Aug 2013 11:47:22 +0100
|
||||
Subject: [PATCH 12/27] MIPS: ath79: Avoid using unitialized 'reg' variable
|
||||
|
||||
Fixes the following build error:
|
||||
arch/mips/include/asm/mach-ath79/ath79.h:139:20: error: 'reg' may be used
|
||||
uninitialized in this function [-Werror=maybe-uninitialized]
|
||||
arch/mips/ath79/common.c:62:6: note: 'reg' was declared here
|
||||
In file included from arch/mips/ath79/common.c:20:0:
|
||||
arch/mips/ath79/common.c: In function 'ath79_device_reset_clear':
|
||||
arch/mips/include/asm/mach-ath79/ath79.h:139:20:
|
||||
error: 'reg' may be used uninitialized in this function
|
||||
[-Werror=maybe-uninitialized]
|
||||
arch/mips/ath79/common.c:90:6: note: 'reg' was declared here
|
||||
|
||||
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
|
||||
Acked-by: Gabor Juhos <juhosg@openwrt.org>
|
||||
---
|
||||
arch/mips/ath79/common.c | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/mips/ath79/common.c
|
||||
+++ b/arch/mips/ath79/common.c
|
||||
@@ -106,7 +106,7 @@ void ath79_device_reset_set(u32 mask)
|
||||
else if (soc_is_qca955x())
|
||||
reg = QCA955X_RESET_REG_RESET_MODULE;
|
||||
else
|
||||
- BUG();
|
||||
+ panic("Reset register not defined for this SOC");
|
||||
|
||||
spin_lock_irqsave(&ath79_device_reset_lock, flags);
|
||||
t = ath79_reset_rr(reg);
|
||||
@@ -134,7 +134,7 @@ void ath79_device_reset_clear(u32 mask)
|
||||
else if (soc_is_qca955x())
|
||||
reg = QCA955X_RESET_REG_RESET_MODULE;
|
||||
else
|
||||
- BUG();
|
||||
+ panic("Reset register not defined for this SOC");
|
||||
|
||||
spin_lock_irqsave(&ath79_device_reset_lock, flags);
|
||||
t = ath79_reset_rr(reg);
|
||||
@ -1,331 +0,0 @@
|
||||
From cff23ba486e3c5d17c4d7e446f5eddead855c101 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <john@phrozen.org>
|
||||
Date: Tue, 6 Mar 2018 08:45:55 +0100
|
||||
Subject: [PATCH 16/27] MIPS: ath79: add support for QCA953x SoC
|
||||
|
||||
Note that the clock calculation looks very similar to the QCA955x, but the
|
||||
meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
||||
|
||||
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
|
||||
---
|
||||
arch/mips/ath79/Kconfig | 6 ++-
|
||||
arch/mips/ath79/clock.c | 87 ++++++++++++++++++++++++++++++++
|
||||
arch/mips/ath79/common.c | 4 ++
|
||||
arch/mips/ath79/dev-common.c | 4 ++
|
||||
arch/mips/ath79/early_printk.c | 2 +
|
||||
arch/mips/ath79/irq.c | 33 +++++++++++-
|
||||
arch/mips/ath79/setup.c | 21 ++++++--
|
||||
arch/mips/include/asm/mach-ath79/ath79.h | 11 ++++
|
||||
8 files changed, 162 insertions(+), 6 deletions(-)
|
||||
|
||||
--- a/arch/mips/ath79/Kconfig
|
||||
+++ b/arch/mips/ath79/Kconfig
|
||||
@@ -94,6 +94,10 @@ config SOC_AR934X
|
||||
select PCI_AR724X if PCI
|
||||
def_bool n
|
||||
|
||||
+config SOC_QCA953X
|
||||
+ select USB_ARCH_HAS_EHCI
|
||||
+ def_bool n
|
||||
+
|
||||
config SOC_QCA955X
|
||||
select HW_HAS_PCI
|
||||
select PCI_AR724X if PCI
|
||||
@@ -115,7 +119,7 @@ config ATH79_DEV_USB
|
||||
def_bool n
|
||||
|
||||
config ATH79_DEV_WMAC
|
||||
- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
|
||||
+ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
|
||||
def_bool n
|
||||
|
||||
endif
|
||||
--- a/arch/mips/ath79/clock.c
|
||||
+++ b/arch/mips/ath79/clock.c
|
||||
@@ -355,6 +355,91 @@ static void __init ar934x_clocks_init(vo
|
||||
iounmap(dpll_base);
|
||||
}
|
||||
|
||||
+static void __init qca953x_clocks_init(void)
|
||||
+{
|
||||
+ unsigned long ref_rate;
|
||||
+ unsigned long cpu_rate;
|
||||
+ unsigned long ddr_rate;
|
||||
+ unsigned long ahb_rate;
|
||||
+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
|
||||
+ u32 cpu_pll, ddr_pll;
|
||||
+ u32 bootstrap;
|
||||
+
|
||||
+ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
|
||||
+ if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
|
||||
+ ref_rate = 40 * 1000 * 1000;
|
||||
+ else
|
||||
+ ref_rate = 25 * 1000 * 1000;
|
||||
+
|
||||
+ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
|
||||
+ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
|
||||
+ QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
|
||||
+ ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
|
||||
+ QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
|
||||
+ nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
|
||||
+ QCA953X_PLL_CPU_CONFIG_NINT_MASK;
|
||||
+ frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
|
||||
+ QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
|
||||
+
|
||||
+ cpu_pll = nint * ref_rate / ref_div;
|
||||
+ cpu_pll += frac * (ref_rate >> 6) / ref_div;
|
||||
+ cpu_pll /= (1 << out_div);
|
||||
+
|
||||
+ pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
|
||||
+ out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
|
||||
+ QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
|
||||
+ ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
|
||||
+ QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
|
||||
+ nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
|
||||
+ QCA953X_PLL_DDR_CONFIG_NINT_MASK;
|
||||
+ frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
|
||||
+ QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
|
||||
+
|
||||
+ ddr_pll = nint * ref_rate / ref_div;
|
||||
+ ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
|
||||
+ ddr_pll /= (1 << out_div);
|
||||
+
|
||||
+ clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
|
||||
+
|
||||
+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
|
||||
+ QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
|
||||
+
|
||||
+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
|
||||
+ cpu_rate = ref_rate;
|
||||
+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
|
||||
+ cpu_rate = cpu_pll / (postdiv + 1);
|
||||
+ else
|
||||
+ cpu_rate = ddr_pll / (postdiv + 1);
|
||||
+
|
||||
+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
|
||||
+ QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
|
||||
+
|
||||
+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
|
||||
+ ddr_rate = ref_rate;
|
||||
+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
|
||||
+ ddr_rate = ddr_pll / (postdiv + 1);
|
||||
+ else
|
||||
+ ddr_rate = cpu_pll / (postdiv + 1);
|
||||
+
|
||||
+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
|
||||
+ QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
|
||||
+
|
||||
+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
|
||||
+ ahb_rate = ref_rate;
|
||||
+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
|
||||
+ ahb_rate = ddr_pll / (postdiv + 1);
|
||||
+ else
|
||||
+ ahb_rate = cpu_pll / (postdiv + 1);
|
||||
+
|
||||
+ ath79_add_sys_clkdev("ref", ref_rate);
|
||||
+ ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
+ ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
+ ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
+
|
||||
+ clk_add_alias("wdt", NULL, "ref", NULL);
|
||||
+ clk_add_alias("uart", NULL, "ref", NULL);
|
||||
+}
|
||||
+
|
||||
static void __init qca955x_clocks_init(void)
|
||||
{
|
||||
unsigned long ref_rate;
|
||||
@@ -450,6 +535,8 @@ void __init ath79_clocks_init(void)
|
||||
ar933x_clocks_init();
|
||||
else if (soc_is_ar934x())
|
||||
ar934x_clocks_init();
|
||||
+ else if (soc_is_qca953x())
|
||||
+ qca953x_clocks_init();
|
||||
else if (soc_is_qca955x())
|
||||
qca955x_clocks_init();
|
||||
else
|
||||
--- a/arch/mips/ath79/common.c
|
||||
+++ b/arch/mips/ath79/common.c
|
||||
@@ -103,6 +103,8 @@ void ath79_device_reset_set(u32 mask)
|
||||
reg = AR933X_RESET_REG_RESET_MODULE;
|
||||
else if (soc_is_ar934x())
|
||||
reg = AR934X_RESET_REG_RESET_MODULE;
|
||||
+ else if (soc_is_qca953x())
|
||||
+ reg = QCA953X_RESET_REG_RESET_MODULE;
|
||||
else if (soc_is_qca955x())
|
||||
reg = QCA955X_RESET_REG_RESET_MODULE;
|
||||
else
|
||||
@@ -131,6 +133,8 @@ void ath79_device_reset_clear(u32 mask)
|
||||
reg = AR933X_RESET_REG_RESET_MODULE;
|
||||
else if (soc_is_ar934x())
|
||||
reg = AR934X_RESET_REG_RESET_MODULE;
|
||||
+ else if (soc_is_qca953x())
|
||||
+ reg = QCA953X_RESET_REG_RESET_MODULE;
|
||||
else if (soc_is_qca955x())
|
||||
reg = QCA955X_RESET_REG_RESET_MODULE;
|
||||
else
|
||||
--- a/arch/mips/ath79/dev-common.c
|
||||
+++ b/arch/mips/ath79/dev-common.c
|
||||
@@ -85,6 +85,7 @@ void __init ath79_register_uart(void)
|
||||
soc_is_ar724x() ||
|
||||
soc_is_ar913x() ||
|
||||
soc_is_ar934x() ||
|
||||
+ soc_is_qca953x() ||
|
||||
soc_is_qca955x()) {
|
||||
ath79_uart_data[0].uartclk = uart_clk_rate;
|
||||
platform_device_register(&ath79_uart_device);
|
||||
@@ -148,6 +149,9 @@ void __init ath79_gpio_init(void)
|
||||
} else if (soc_is_ar934x()) {
|
||||
ath79_gpio_pdata.ngpios = AR934X_GPIO_COUNT;
|
||||
ath79_gpio_pdata.oe_inverted = 1;
|
||||
+ } else if (soc_is_qca953x()) {
|
||||
+ ath79_gpio_pdata.ngpios = QCA953X_GPIO_COUNT;
|
||||
+ ath79_gpio_pdata.oe_inverted = 1;
|
||||
} else if (soc_is_qca955x()) {
|
||||
ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
|
||||
ath79_gpio_pdata.oe_inverted = 1;
|
||||
--- a/arch/mips/ath79/early_printk.c
|
||||
+++ b/arch/mips/ath79/early_printk.c
|
||||
@@ -116,6 +116,8 @@ static void prom_putchar_init(void)
|
||||
case REV_ID_MAJOR_AR9341:
|
||||
case REV_ID_MAJOR_AR9342:
|
||||
case REV_ID_MAJOR_AR9344:
|
||||
+ case REV_ID_MAJOR_QCA9533:
|
||||
+ case REV_ID_MAJOR_QCA9533_V2:
|
||||
case REV_ID_MAJOR_QCA9556:
|
||||
case REV_ID_MAJOR_QCA9558:
|
||||
_prom_putchar = prom_putchar_ar71xx;
|
||||
--- a/arch/mips/ath79/irq.c
|
||||
+++ b/arch/mips/ath79/irq.c
|
||||
@@ -56,6 +56,34 @@ static void ar934x_ip2_irq_init(void)
|
||||
irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
|
||||
}
|
||||
|
||||
+static void qca953x_ip2_irq_dispatch(struct irq_desc *desc)
|
||||
+{
|
||||
+ u32 status;
|
||||
+
|
||||
+ status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
|
||||
+
|
||||
+ if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
|
||||
+ ath79_ddr_wb_flush(3);
|
||||
+ generic_handle_irq(ATH79_IP2_IRQ(0));
|
||||
+ } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
|
||||
+ ath79_ddr_wb_flush(4);
|
||||
+ generic_handle_irq(ATH79_IP2_IRQ(1));
|
||||
+ } else {
|
||||
+ spurious_interrupt();
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void qca953x_irq_init(void)
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ for (i = ATH79_IP2_IRQ_BASE;
|
||||
+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
|
||||
+ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
|
||||
+
|
||||
+ irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
|
||||
+}
|
||||
+
|
||||
static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
|
||||
{
|
||||
u32 status;
|
||||
@@ -143,7 +171,7 @@ void __init arch_init_irq(void)
|
||||
soc_is_ar913x() || soc_is_ar933x()) {
|
||||
irq_wb_chan2 = 3;
|
||||
irq_wb_chan3 = 2;
|
||||
- } else if (soc_is_ar934x()) {
|
||||
+ } else if (soc_is_ar934x() || soc_is_qca953x()) {
|
||||
irq_wb_chan3 = 2;
|
||||
}
|
||||
|
||||
@@ -154,6 +182,7 @@ void __init arch_init_irq(void)
|
||||
else if (soc_is_ar724x() ||
|
||||
soc_is_ar933x() ||
|
||||
soc_is_ar934x() ||
|
||||
+ soc_is_qca953x() ||
|
||||
soc_is_qca955x())
|
||||
misc_is_ar71xx = false;
|
||||
else
|
||||
@@ -164,6 +193,8 @@ void __init arch_init_irq(void)
|
||||
|
||||
if (soc_is_ar934x())
|
||||
ar934x_ip2_irq_init();
|
||||
+ else if (soc_is_qca953x())
|
||||
+ qca953x_irq_init();
|
||||
else if (soc_is_qca955x())
|
||||
qca955x_irq_init();
|
||||
}
|
||||
--- a/arch/mips/ath79/setup.c
|
||||
+++ b/arch/mips/ath79/setup.c
|
||||
@@ -60,6 +60,7 @@ static void __init ath79_detect_sys_type
|
||||
u32 major;
|
||||
u32 minor;
|
||||
u32 rev = 0;
|
||||
+ u32 ver = 1;
|
||||
|
||||
id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
|
||||
major = id & REV_ID_MAJOR_MASK;
|
||||
@@ -152,6 +153,17 @@ static void __init ath79_detect_sys_type
|
||||
rev = id & AR934X_REV_ID_REVISION_MASK;
|
||||
break;
|
||||
|
||||
+ case REV_ID_MAJOR_QCA9533_V2:
|
||||
+ ver = 2;
|
||||
+ ath79_soc_rev = 2;
|
||||
+ /* drop through */
|
||||
+
|
||||
+ case REV_ID_MAJOR_QCA9533:
|
||||
+ ath79_soc = ATH79_SOC_QCA9533;
|
||||
+ chip = "9533";
|
||||
+ rev = id & QCA953X_REV_ID_REVISION_MASK;
|
||||
+ break;
|
||||
+
|
||||
case REV_ID_MAJOR_QCA9556:
|
||||
ath79_soc = ATH79_SOC_QCA9556;
|
||||
chip = "9556";
|
||||
@@ -168,11 +180,12 @@ static void __init ath79_detect_sys_type
|
||||
panic("ath79: unknown SoC, id:0x%08x", id);
|
||||
}
|
||||
|
||||
- ath79_soc_rev = rev;
|
||||
+ if (ver == 1)
|
||||
+ ath79_soc_rev = rev;
|
||||
|
||||
- if (soc_is_qca955x())
|
||||
- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
|
||||
- chip, rev);
|
||||
+ if (soc_is_qca953x() || soc_is_qca955x())
|
||||
+ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
|
||||
+ chip, ver, rev);
|
||||
else
|
||||
sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
|
||||
pr_info("SoC: %s\n", ath79_sys_type);
|
||||
--- a/arch/mips/include/asm/mach-ath79/ath79.h
|
||||
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
|
||||
@@ -32,6 +32,7 @@ enum ath79_soc_type {
|
||||
ATH79_SOC_AR9341,
|
||||
ATH79_SOC_AR9342,
|
||||
ATH79_SOC_AR9344,
|
||||
+ ATH79_SOC_QCA9533,
|
||||
ATH79_SOC_QCA9556,
|
||||
ATH79_SOC_QCA9558,
|
||||
};
|
||||
@@ -100,6 +101,16 @@ static inline int soc_is_ar934x(void)
|
||||
return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
|
||||
}
|
||||
|
||||
+static inline int soc_is_qca9533(void)
|
||||
+{
|
||||
+ return ath79_soc == ATH79_SOC_QCA9533;
|
||||
+}
|
||||
+
|
||||
+static inline int soc_is_qca953x(void)
|
||||
+{
|
||||
+ return soc_is_qca9533();
|
||||
+}
|
||||
+
|
||||
static inline int soc_is_qca9556(void)
|
||||
{
|
||||
return ath79_soc == ATH79_SOC_QCA9556;
|
||||
@ -1,410 +0,0 @@
|
||||
From 6aeb24b9508bbe91f89cd4eb21d0d7582d971146 Mon Sep 17 00:00:00 2001
|
||||
From: Weijie Gao <hackpascal@gmail.com>
|
||||
Date: Tue, 6 Mar 2018 08:48:31 +0100
|
||||
Subject: [PATCH 17/27] MIPS: ath79: add support for qca956x soc
|
||||
|
||||
This patch adds soc support for QCA9561 and TP9343.
|
||||
TP9343 is a reduced version of QCA9561, which can be found in TP-LINK routers in China.
|
||||
The qca956x_wmac has not yet been supported by ath9k.
|
||||
|
||||
tested on TL-WDR6500 and TL-WR882N v1 (Chinese version)
|
||||
|
||||
Signed-off-by: Weijie Gao <hackpascal@gmail.com>
|
||||
---
|
||||
arch/mips/ath79/Kconfig | 2 +-
|
||||
arch/mips/ath79/clock.c | 96 ++++++++++++++++++++++++++++++++
|
||||
arch/mips/ath79/common.c | 4 ++
|
||||
arch/mips/ath79/dev-common.c | 7 ++-
|
||||
arch/mips/ath79/early_printk.c | 2 +
|
||||
arch/mips/ath79/irq.c | 87 ++++++++++++++++++++++++++++-
|
||||
arch/mips/ath79/pci.c | 12 ++++
|
||||
arch/mips/ath79/setup.c | 17 +++++-
|
||||
arch/mips/include/asm/mach-ath79/ath79.h | 22 ++++++++
|
||||
9 files changed, 245 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/arch/mips/ath79/Kconfig
|
||||
+++ b/arch/mips/ath79/Kconfig
|
||||
@@ -119,7 +119,7 @@ config ATH79_DEV_USB
|
||||
def_bool n
|
||||
|
||||
config ATH79_DEV_WMAC
|
||||
- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
|
||||
+ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X)
|
||||
def_bool n
|
||||
|
||||
endif
|
||||
--- a/arch/mips/ath79/clock.c
|
||||
+++ b/arch/mips/ath79/clock.c
|
||||
@@ -525,6 +525,100 @@ static void __init qca955x_clocks_init(v
|
||||
clk_add_alias("uart", NULL, "ref", NULL);
|
||||
}
|
||||
|
||||
+static void __init qca956x_clocks_init(void)
|
||||
+{
|
||||
+ unsigned long ref_rate;
|
||||
+ unsigned long cpu_rate;
|
||||
+ unsigned long ddr_rate;
|
||||
+ unsigned long ahb_rate;
|
||||
+ u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
|
||||
+ u32 cpu_pll, ddr_pll;
|
||||
+ u32 bootstrap;
|
||||
+
|
||||
+ bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
|
||||
+ if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
|
||||
+ ref_rate = 40 * 1000 * 1000;
|
||||
+ else
|
||||
+ ref_rate = 25 * 1000 * 1000;
|
||||
+
|
||||
+ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
|
||||
+ out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
|
||||
+ QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
|
||||
+ ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
|
||||
+ QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
|
||||
+
|
||||
+ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
|
||||
+ nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
|
||||
+ QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
|
||||
+ hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
|
||||
+ QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
|
||||
+ lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
|
||||
+ QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
|
||||
+
|
||||
+ cpu_pll = nint * ref_rate / ref_div;
|
||||
+ cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
|
||||
+ cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
|
||||
+ cpu_pll /= (1 << out_div);
|
||||
+
|
||||
+ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
|
||||
+ out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
|
||||
+ QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
|
||||
+ ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
|
||||
+ QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
|
||||
+ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
|
||||
+ nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
|
||||
+ QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
|
||||
+ hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
|
||||
+ QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
|
||||
+ lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
|
||||
+ QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
|
||||
+
|
||||
+ ddr_pll = nint * ref_rate / ref_div;
|
||||
+ ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
|
||||
+ ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
|
||||
+ ddr_pll /= (1 << out_div);
|
||||
+
|
||||
+ clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
|
||||
+
|
||||
+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
|
||||
+ QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
|
||||
+
|
||||
+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
|
||||
+ cpu_rate = ref_rate;
|
||||
+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
|
||||
+ cpu_rate = ddr_pll / (postdiv + 1);
|
||||
+ else
|
||||
+ cpu_rate = cpu_pll / (postdiv + 1);
|
||||
+
|
||||
+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
|
||||
+ QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
|
||||
+
|
||||
+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
|
||||
+ ddr_rate = ref_rate;
|
||||
+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
|
||||
+ ddr_rate = cpu_pll / (postdiv + 1);
|
||||
+ else
|
||||
+ ddr_rate = ddr_pll / (postdiv + 1);
|
||||
+
|
||||
+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
|
||||
+ QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
|
||||
+
|
||||
+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
|
||||
+ ahb_rate = ref_rate;
|
||||
+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
|
||||
+ ahb_rate = ddr_pll / (postdiv + 1);
|
||||
+ else
|
||||
+ ahb_rate = cpu_pll / (postdiv + 1);
|
||||
+
|
||||
+ ath79_add_sys_clkdev("ref", ref_rate);
|
||||
+ ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
+ ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
+ ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
+
|
||||
+ clk_add_alias("wdt", NULL, "ref", NULL);
|
||||
+ clk_add_alias("uart", NULL, "ref", NULL);
|
||||
+}
|
||||
+
|
||||
void __init ath79_clocks_init(void)
|
||||
{
|
||||
if (soc_is_ar71xx())
|
||||
@@ -539,6 +633,8 @@ void __init ath79_clocks_init(void)
|
||||
qca953x_clocks_init();
|
||||
else if (soc_is_qca955x())
|
||||
qca955x_clocks_init();
|
||||
+ else if (soc_is_qca956x() || soc_is_tp9343())
|
||||
+ qca956x_clocks_init();
|
||||
else
|
||||
BUG();
|
||||
}
|
||||
--- a/arch/mips/ath79/common.c
|
||||
+++ b/arch/mips/ath79/common.c
|
||||
@@ -107,6 +107,8 @@ void ath79_device_reset_set(u32 mask)
|
||||
reg = QCA953X_RESET_REG_RESET_MODULE;
|
||||
else if (soc_is_qca955x())
|
||||
reg = QCA955X_RESET_REG_RESET_MODULE;
|
||||
+ else if (soc_is_qca956x() || soc_is_tp9343())
|
||||
+ reg = QCA956X_RESET_REG_RESET_MODULE;
|
||||
else
|
||||
panic("Reset register not defined for this SOC");
|
||||
|
||||
@@ -137,6 +139,8 @@ void ath79_device_reset_clear(u32 mask)
|
||||
reg = QCA953X_RESET_REG_RESET_MODULE;
|
||||
else if (soc_is_qca955x())
|
||||
reg = QCA955X_RESET_REG_RESET_MODULE;
|
||||
+ else if (soc_is_qca956x() || soc_is_tp9343())
|
||||
+ reg = QCA956X_RESET_REG_RESET_MODULE;
|
||||
else
|
||||
panic("Reset register not defined for this SOC");
|
||||
|
||||
--- a/arch/mips/ath79/dev-common.c
|
||||
+++ b/arch/mips/ath79/dev-common.c
|
||||
@@ -86,7 +86,9 @@ void __init ath79_register_uart(void)
|
||||
soc_is_ar913x() ||
|
||||
soc_is_ar934x() ||
|
||||
soc_is_qca953x() ||
|
||||
- soc_is_qca955x()) {
|
||||
+ soc_is_qca955x() ||
|
||||
+ soc_is_qca956x() ||
|
||||
+ soc_is_tp9343()) {
|
||||
ath79_uart_data[0].uartclk = uart_clk_rate;
|
||||
platform_device_register(&ath79_uart_device);
|
||||
} else if (soc_is_ar933x()) {
|
||||
@@ -155,6 +157,9 @@ void __init ath79_gpio_init(void)
|
||||
} else if (soc_is_qca955x()) {
|
||||
ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
|
||||
ath79_gpio_pdata.oe_inverted = 1;
|
||||
+ } else if (soc_is_qca956x() || soc_is_tp9343()) {
|
||||
+ ath79_gpio_pdata.ngpios = QCA956X_GPIO_COUNT;
|
||||
+ ath79_gpio_pdata.oe_inverted = 1;
|
||||
} else {
|
||||
BUG();
|
||||
}
|
||||
--- a/arch/mips/ath79/early_printk.c
|
||||
+++ b/arch/mips/ath79/early_printk.c
|
||||
@@ -120,6 +120,8 @@ static void prom_putchar_init(void)
|
||||
case REV_ID_MAJOR_QCA9533_V2:
|
||||
case REV_ID_MAJOR_QCA9556:
|
||||
case REV_ID_MAJOR_QCA9558:
|
||||
+ case REV_ID_MAJOR_TP9343:
|
||||
+ case REV_ID_MAJOR_QCA956X:
|
||||
_prom_putchar = prom_putchar_ar71xx;
|
||||
break;
|
||||
|
||||
--- a/arch/mips/ath79/irq.c
|
||||
+++ b/arch/mips/ath79/irq.c
|
||||
@@ -156,6 +156,87 @@ static void qca955x_irq_init(void)
|
||||
irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
|
||||
}
|
||||
|
||||
+static void qca956x_ip2_irq_dispatch(struct irq_desc *desc)
|
||||
+{
|
||||
+ u32 status;
|
||||
+
|
||||
+ status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
|
||||
+ status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL;
|
||||
+
|
||||
+ if (status == 0) {
|
||||
+ spurious_interrupt();
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) {
|
||||
+ /* TODO: flush DDR? */
|
||||
+ generic_handle_irq(ATH79_IP2_IRQ(0));
|
||||
+ }
|
||||
+
|
||||
+ if (status & QCA956X_EXT_INT_WMAC_ALL) {
|
||||
+ /* TODO: flsuh DDR? */
|
||||
+ generic_handle_irq(ATH79_IP2_IRQ(1));
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void qca956x_ip3_irq_dispatch(struct irq_desc *desc)
|
||||
+{
|
||||
+ u32 status;
|
||||
+
|
||||
+ status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
|
||||
+ status &= QCA956X_EXT_INT_PCIE_RC2_ALL |
|
||||
+ QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2;
|
||||
+
|
||||
+ if (status == 0) {
|
||||
+ spurious_interrupt();
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
+ if (status & QCA956X_EXT_INT_USB1) {
|
||||
+ /* TODO: flush DDR? */
|
||||
+ generic_handle_irq(ATH79_IP3_IRQ(0));
|
||||
+ }
|
||||
+
|
||||
+ if (status & QCA956X_EXT_INT_USB2) {
|
||||
+ /* TODO: flush DDR? */
|
||||
+ generic_handle_irq(ATH79_IP3_IRQ(1));
|
||||
+ }
|
||||
+
|
||||
+ if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) {
|
||||
+ /* TODO: flush DDR? */
|
||||
+ generic_handle_irq(ATH79_IP3_IRQ(2));
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void qca956x_enable_timer_cb(void) {
|
||||
+ u32 misc;
|
||||
+
|
||||
+ misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
|
||||
+ misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
|
||||
+ ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
|
||||
+}
|
||||
+
|
||||
+static void qca956x_irq_init(void)
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ for (i = ATH79_IP2_IRQ_BASE;
|
||||
+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
|
||||
+ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
|
||||
+
|
||||
+ irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
|
||||
+
|
||||
+ for (i = ATH79_IP3_IRQ_BASE;
|
||||
+ i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
|
||||
+ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
|
||||
+
|
||||
+ irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
|
||||
+
|
||||
+ /* QCA956x timer init workaround has to be applied right before setting
|
||||
+ * up the clock. Else, there will be no jiffies */
|
||||
+ late_time_init = &qca956x_enable_timer_cb;
|
||||
+}
|
||||
+
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
unsigned irq_wb_chan2 = -1;
|
||||
@@ -183,7 +264,9 @@ void __init arch_init_irq(void)
|
||||
soc_is_ar933x() ||
|
||||
soc_is_ar934x() ||
|
||||
soc_is_qca953x() ||
|
||||
- soc_is_qca955x())
|
||||
+ soc_is_qca955x() ||
|
||||
+ soc_is_qca956x() ||
|
||||
+ soc_is_tp9343())
|
||||
misc_is_ar71xx = false;
|
||||
else
|
||||
BUG();
|
||||
@@ -197,4 +280,6 @@ void __init arch_init_irq(void)
|
||||
qca953x_irq_init();
|
||||
else if (soc_is_qca955x())
|
||||
qca955x_irq_init();
|
||||
+ else if (soc_is_qca956x() || soc_is_tp9343())
|
||||
+ qca956x_irq_init();
|
||||
}
|
||||
--- a/arch/mips/ath79/pci.c
|
||||
+++ b/arch/mips/ath79/pci.c
|
||||
@@ -82,6 +82,9 @@ int pcibios_map_irq(const struct pci_dev
|
||||
} else if (soc_is_qca955x()) {
|
||||
ath79_pci_irq_map = qca955x_pci_irq_map;
|
||||
ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
|
||||
+ } else if (soc_is_qca956x()) {
|
||||
+ ath79_pci_irq_map = qca956x_pci_irq_map;
|
||||
+ ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map);
|
||||
} else {
|
||||
pr_crit("pci %s: invalid irq map\n",
|
||||
pci_name((struct pci_dev *) dev));
|
||||
@@ -261,6 +264,15 @@ int __init ath79_register_pci(void)
|
||||
QCA955X_PCI_MEM_SIZE,
|
||||
1,
|
||||
ATH79_IP3_IRQ(2));
|
||||
+ } else if (soc_is_qca956x()) {
|
||||
+ pdev = ath79_register_pci_ar724x(0,
|
||||
+ QCA956X_PCI_CFG_BASE1,
|
||||
+ QCA956X_PCI_CTRL_BASE1,
|
||||
+ QCA956X_PCI_CRP_BASE1,
|
||||
+ QCA956X_PCI_MEM_BASE1,
|
||||
+ QCA956X_PCI_MEM_SIZE,
|
||||
+ 1,
|
||||
+ ATH79_IP3_IRQ(2));
|
||||
} else {
|
||||
/* No PCI support */
|
||||
return -ENODEV;
|
||||
--- a/arch/mips/ath79/setup.c
|
||||
+++ b/arch/mips/ath79/setup.c
|
||||
@@ -176,6 +176,18 @@ static void __init ath79_detect_sys_type
|
||||
rev = id & QCA955X_REV_ID_REVISION_MASK;
|
||||
break;
|
||||
|
||||
+ case REV_ID_MAJOR_QCA956X:
|
||||
+ ath79_soc = ATH79_SOC_QCA956X;
|
||||
+ chip = "956X";
|
||||
+ rev = id & QCA956X_REV_ID_REVISION_MASK;
|
||||
+ break;
|
||||
+
|
||||
+ case REV_ID_MAJOR_TP9343:
|
||||
+ ath79_soc = ATH79_SOC_TP9343;
|
||||
+ chip = "9343";
|
||||
+ rev = id & QCA956X_REV_ID_REVISION_MASK;
|
||||
+ break;
|
||||
+
|
||||
default:
|
||||
panic("ath79: unknown SoC, id:0x%08x", id);
|
||||
}
|
||||
@@ -183,9 +195,12 @@ static void __init ath79_detect_sys_type
|
||||
if (ver == 1)
|
||||
ath79_soc_rev = rev;
|
||||
|
||||
- if (soc_is_qca953x() || soc_is_qca955x())
|
||||
+ if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
|
||||
sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
|
||||
chip, ver, rev);
|
||||
+ else if (soc_is_tp9343())
|
||||
+ sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
|
||||
+ chip, rev);
|
||||
else
|
||||
sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
|
||||
pr_info("SoC: %s\n", ath79_sys_type);
|
||||
--- a/arch/mips/include/asm/mach-ath79/ath79.h
|
||||
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
|
||||
@@ -35,6 +35,8 @@ enum ath79_soc_type {
|
||||
ATH79_SOC_QCA9533,
|
||||
ATH79_SOC_QCA9556,
|
||||
ATH79_SOC_QCA9558,
|
||||
+ ATH79_SOC_TP9343,
|
||||
+ ATH79_SOC_QCA956X,
|
||||
};
|
||||
|
||||
extern enum ath79_soc_type ath79_soc;
|
||||
@@ -126,6 +128,26 @@ static inline int soc_is_qca955x(void)
|
||||
return soc_is_qca9556() || soc_is_qca9558();
|
||||
}
|
||||
|
||||
+static inline int soc_is_tp9343(void)
|
||||
+{
|
||||
+ return ath79_soc == ATH79_SOC_TP9343;
|
||||
+}
|
||||
+
|
||||
+static inline int soc_is_qca9561(void)
|
||||
+{
|
||||
+ return ath79_soc == ATH79_SOC_QCA956X;
|
||||
+}
|
||||
+
|
||||
+static inline int soc_is_qca9563(void)
|
||||
+{
|
||||
+ return ath79_soc == ATH79_SOC_QCA956X;
|
||||
+}
|
||||
+
|
||||
+static inline int soc_is_qca956x(void)
|
||||
+{
|
||||
+ return soc_is_qca9561() || soc_is_qca9563();
|
||||
+}
|
||||
+
|
||||
void ath79_ddr_wb_flush(unsigned int reg);
|
||||
void ath79_ddr_set_pci_windows(void);
|
||||
|
||||
@ -0,0 +1,57 @@
|
||||
From 4a4f869ec58ed8910b9b2e68d0eee50957e9bb20 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <john@phrozen.org>
|
||||
Date: Mon, 25 Jun 2018 15:52:10 +0200
|
||||
Subject: [PATCH 17/33] dt-bindings: PCI: qcom,ar7100: adds binding doc
|
||||
|
||||
With the driver being converted from platform_data to pure OF, we need to
|
||||
also add some docs.
|
||||
|
||||
Cc: Rob Herring <robh+dt@kernel.org>
|
||||
Cc: devicetree@vger.kernel.org
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
---
|
||||
.../devicetree/bindings/pci/qcom,ar7100-pci.txt | 38 ++++++++++++++++++++++
|
||||
1 file changed, 38 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
|
||||
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/pci/qcom,ar7100-pci.txt
|
||||
@@ -0,0 +1,38 @@
|
||||
+* Qualcomm Atheros AR7100 PCI express root complex
|
||||
+
|
||||
+Required properties:
|
||||
+- compatible: should contain "qcom,ar7100-pci" to identify the core.
|
||||
+- reg: Should contain the register ranges as listed in the reg-names property.
|
||||
+- reg-names: Definition: Must include the following entries
|
||||
+ - "cfg_base" IO Memory
|
||||
+- #address-cells: set to <3>
|
||||
+- #size-cells: set to <2>
|
||||
+- ranges: ranges for the PCI memory and I/O regions
|
||||
+- interrupt-map-mask and interrupt-map: standard PCI
|
||||
+ properties to define the mapping of the PCIe interface to interrupt
|
||||
+ numbers.
|
||||
+- #interrupt-cells: set to <1>
|
||||
+- interrupt-controller: define to enable the builtin IRQ cascade.
|
||||
+
|
||||
+Optional properties:
|
||||
+- interrupt-parent: phandle to the MIPS IRQ controller
|
||||
+
|
||||
+* Example for ar7100
|
||||
+ pcie-controller@180c0000 {
|
||||
+ compatible = "qca,ar7100-pci";
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+ bus-range = <0x0 0x0>;
|
||||
+ reg = <0x17010000 0x100>;
|
||||
+ reg-names = "cfg_base";
|
||||
+ ranges = <0x2000000 0 0x10000000 0x10000000 0 0x07000000
|
||||
+ 0x1000000 0 0x00000000 0x00000000 0 0x00000001>;
|
||||
+ interrupt-parent = <&cpuintc>;
|
||||
+ interrupts = <2>;
|
||||
+
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <1>;
|
||||
+
|
||||
+ interrupt-map-mask = <0 0 0 1>;
|
||||
+ interrupt-map = <0 0 0 0 &pcie0 0>;
|
||||
+ };
|
||||
@ -0,0 +1,61 @@
|
||||
From ea27764bc3ef2a05decf3ae05edffc289cd0d93c Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <john@phrozen.org>
|
||||
Date: Mon, 25 Jun 2018 15:52:02 +0200
|
||||
Subject: [PATCH 19/33] dt-bindings: PCI: qcom,ar7240: adds binding doc
|
||||
|
||||
With the driver being converted from platform_data to pure OF, we need to
|
||||
also add some docs.
|
||||
|
||||
Cc: Rob Herring <robh+dt@kernel.org>
|
||||
Cc: devicetree@vger.kernel.org
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
---
|
||||
.../devicetree/bindings/pci/qcom,ar7240-pci.txt | 42 ++++++++++++++++++++++
|
||||
1 file changed, 42 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt
|
||||
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/pci/qcom,ar7240-pci.txt
|
||||
@@ -0,0 +1,42 @@
|
||||
+* Qualcomm Atheros AR724X PCI express root complex
|
||||
+
|
||||
+Required properties:
|
||||
+- compatible: should contain "qcom,ar7240-pci" to identify the core.
|
||||
+- reg: Should contain the register ranges as listed in the reg-names property.
|
||||
+- reg-names: Definition: Must include the following entries
|
||||
+ - "crp_base" Configuration registers
|
||||
+ - "ctrl_base" Control registers
|
||||
+ - "cfg_base" IO Memory
|
||||
+- #address-cells: set to <3>
|
||||
+- #size-cells: set to <2>
|
||||
+- ranges: ranges for the PCI memory and I/O regions
|
||||
+- interrupt-map-mask and interrupt-map: standard PCI
|
||||
+ properties to define the mapping of the PCIe interface to interrupt
|
||||
+ numbers.
|
||||
+- #interrupt-cells: set to <1>
|
||||
+- interrupt-parent: phandle to the MIPS IRQ controller
|
||||
+
|
||||
+Optional properties:
|
||||
+- interrupt-controller: define to enable the builtin IRQ cascade.
|
||||
+
|
||||
+* Example for qca9557
|
||||
+ pcie-controller@180c0000 {
|
||||
+ compatible = "qcom,ar7240-pci";
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+ bus-range = <0x0 0x0>;
|
||||
+ reg = <0x180c0000 0x1000>,
|
||||
+ <0x180f0000 0x100>,
|
||||
+ <0x14000000 0x1000>;
|
||||
+ reg-names = "crp_base", "ctrl_base", "cfg_base";
|
||||
+ ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000
|
||||
+ 0x1000000 0 0x00000000 0x00000000 0 0x00000001>;
|
||||
+ interrupt-parent = <&intc2>;
|
||||
+ interrupts = <1>;
|
||||
+
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <1>;
|
||||
+
|
||||
+ interrupt-map-mask = <0 0 0 1>;
|
||||
+ interrupt-map = <0 0 0 0 &pcie0 0>;
|
||||
+ };
|
||||
@ -1,172 +0,0 @@
|
||||
From e03edbc8e68063b3fca7457fa048d8abe0045f1f Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <john@phrozen.org>
|
||||
Date: Tue, 6 Mar 2018 10:15:54 +0100
|
||||
Subject: [PATCH 27/27] MIPS: ath79: drop mips_machine support
|
||||
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
---
|
||||
arch/mips/Kconfig | 1 -
|
||||
arch/mips/ath79/machtypes.h | 28 -----------------
|
||||
arch/mips/ath79/setup.c | 74 ++++++---------------------------------------
|
||||
3 files changed, 10 insertions(+), 93 deletions(-)
|
||||
delete mode 100644 arch/mips/ath79/machtypes.h
|
||||
|
||||
--- a/arch/mips/Kconfig
|
||||
+++ b/arch/mips/Kconfig
|
||||
@@ -196,7 +196,6 @@ config ATH79
|
||||
select COMMON_CLK
|
||||
select CLKDEV_LOOKUP
|
||||
select IRQ_MIPS_CPU
|
||||
- select MIPS_MACHINE
|
||||
select SYS_HAS_CPU_MIPS32_R2
|
||||
select SYS_HAS_EARLY_PRINTK
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
--- a/arch/mips/ath79/machtypes.h
|
||||
+++ /dev/null
|
||||
@@ -1,28 +0,0 @@
|
||||
-/*
|
||||
- * Atheros AR71XX/AR724X/AR913X machine type definitions
|
||||
- *
|
||||
- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
|
||||
- * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
|
||||
- *
|
||||
- * This program is free software; you can redistribute it and/or modify it
|
||||
- * under the terms of the GNU General Public License version 2 as published
|
||||
- * by the Free Software Foundation.
|
||||
- */
|
||||
-
|
||||
-#ifndef _ATH79_MACHTYPE_H
|
||||
-#define _ATH79_MACHTYPE_H
|
||||
-
|
||||
-#include <asm/mips_machine.h>
|
||||
-
|
||||
-enum ath79_mach_type {
|
||||
- ATH79_MACH_GENERIC_OF = -1, /* Device tree board */
|
||||
- ATH79_MACH_GENERIC = 0,
|
||||
- ATH79_MACH_AP121, /* Atheros AP121 reference board */
|
||||
- ATH79_MACH_AP136_010, /* Atheros AP136-010 reference board */
|
||||
- ATH79_MACH_AP81, /* Atheros AP81 reference board */
|
||||
- ATH79_MACH_DB120, /* Atheros DB120 reference board */
|
||||
- ATH79_MACH_PB44, /* Atheros PB44 reference board */
|
||||
- ATH79_MACH_UBNT_XM, /* Ubiquiti Networks XM board rev 1.0 */
|
||||
-};
|
||||
-
|
||||
-#endif /* _ATH79_MACHTYPE_H */
|
||||
--- a/arch/mips/ath79/setup.c
|
||||
+++ b/arch/mips/ath79/setup.c
|
||||
@@ -32,7 +32,6 @@
|
||||
#include <asm/mach-ath79/ath79.h>
|
||||
#include <asm/mach-ath79/ar71xx_regs.h>
|
||||
#include "common.h"
|
||||
-#include "machtypes.h"
|
||||
|
||||
#define ATH79_SYS_TYPE_LEN 64
|
||||
|
||||
@@ -235,25 +234,21 @@ void __init plat_mem_setup(void)
|
||||
else if (fw_passed_dtb)
|
||||
__dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb));
|
||||
|
||||
- if (mips_machtype != ATH79_MACH_GENERIC_OF) {
|
||||
- ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
|
||||
- AR71XX_RESET_SIZE);
|
||||
- ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
|
||||
- AR71XX_PLL_SIZE);
|
||||
- ath79_detect_sys_type();
|
||||
- ath79_ddr_ctrl_init();
|
||||
+ ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
|
||||
+ AR71XX_RESET_SIZE);
|
||||
+ ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
|
||||
+ AR71XX_PLL_SIZE);
|
||||
+ ath79_detect_sys_type();
|
||||
+ ath79_ddr_ctrl_init();
|
||||
|
||||
- detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
|
||||
-
|
||||
- /* OF machines should use the reset driver */
|
||||
- _machine_restart = ath79_restart;
|
||||
- }
|
||||
+ detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
|
||||
|
||||
+ _machine_restart = ath79_restart;
|
||||
_machine_halt = ath79_halt;
|
||||
pm_power_off = ath79_halt;
|
||||
}
|
||||
|
||||
-static void __init ath79_of_plat_time_init(void)
|
||||
+void __init plat_time_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct clk *clk;
|
||||
@@ -283,62 +278,12 @@ static void __init ath79_of_plat_time_in
|
||||
clk_put(clk);
|
||||
}
|
||||
|
||||
-void __init plat_time_init(void)
|
||||
-{
|
||||
- unsigned long cpu_clk_rate;
|
||||
- unsigned long ahb_clk_rate;
|
||||
- unsigned long ddr_clk_rate;
|
||||
- unsigned long ref_clk_rate;
|
||||
-
|
||||
- if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) {
|
||||
- ath79_of_plat_time_init();
|
||||
- return;
|
||||
- }
|
||||
-
|
||||
- ath79_clocks_init();
|
||||
-
|
||||
- cpu_clk_rate = ath79_get_sys_clk_rate("cpu");
|
||||
- ahb_clk_rate = ath79_get_sys_clk_rate("ahb");
|
||||
- ddr_clk_rate = ath79_get_sys_clk_rate("ddr");
|
||||
- ref_clk_rate = ath79_get_sys_clk_rate("ref");
|
||||
-
|
||||
- pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz\n",
|
||||
- cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000,
|
||||
- ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000,
|
||||
- ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000,
|
||||
- ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000);
|
||||
-
|
||||
- mips_hpt_frequency = cpu_clk_rate / 2;
|
||||
-}
|
||||
-
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
irqchip_init();
|
||||
}
|
||||
|
||||
-static int __init ath79_setup(void)
|
||||
-{
|
||||
- if (mips_machtype == ATH79_MACH_GENERIC_OF)
|
||||
- return 0;
|
||||
-
|
||||
- mips_machine_setup();
|
||||
-
|
||||
- return 0;
|
||||
-}
|
||||
-
|
||||
-arch_initcall(ath79_setup);
|
||||
-
|
||||
void __init device_tree_init(void)
|
||||
{
|
||||
unflatten_and_copy_device_tree();
|
||||
}
|
||||
-
|
||||
-MIPS_MACHINE(ATH79_MACH_GENERIC,
|
||||
- "Generic",
|
||||
- "Generic AR71XX/AR724X/AR913X based board",
|
||||
- NULL);
|
||||
-
|
||||
-MIPS_MACHINE(ATH79_MACH_GENERIC_OF,
|
||||
- "DTB",
|
||||
- "Generic AR71XX/AR724X/AR913X based board (DT)",
|
||||
- NULL);
|
||||
--- a/arch/mips/ath79/clock.c
|
||||
+++ b/arch/mips/ath79/clock.c
|
||||
@@ -26,7 +26,6 @@
|
||||
#include <asm/mach-ath79/ath79.h>
|
||||
#include <asm/mach-ath79/ar71xx_regs.h>
|
||||
#include "common.h"
|
||||
-#include "machtypes.h"
|
||||
|
||||
#define AR71XX_BASE_FREQ 40000000
|
||||
#define AR724X_BASE_FREQ 40000000
|
||||
@ -0,0 +1,95 @@
|
||||
From 00e4313da4609074fff134e61dd9ffe3fd37474d Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <john@phrozen.org>
|
||||
Date: Sun, 24 Jun 2018 09:39:41 +0200
|
||||
Subject: [PATCH 31/33] MIPS: ath79: drop !OF clock code
|
||||
|
||||
With the target now being fully OF based, we can drop the legacy clock
|
||||
registration code. All clocks are now probed via devicetree.
|
||||
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
---
|
||||
arch/mips/ath79/clock.c | 56 ------------------------------------------------
|
||||
arch/mips/ath79/common.h | 3 ---
|
||||
2 files changed, 59 deletions(-)
|
||||
|
||||
--- a/arch/mips/ath79/clock.c
|
||||
+++ b/arch/mips/ath79/clock.c
|
||||
@@ -617,60 +617,6 @@ static void __init qca956x_clocks_init(v
|
||||
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
|
||||
}
|
||||
|
||||
-void __init ath79_clocks_init(void)
|
||||
-{
|
||||
- const char *wdt;
|
||||
- const char *uart;
|
||||
-
|
||||
- if (soc_is_ar71xx())
|
||||
- ar71xx_clocks_init(ath79_pll_base);
|
||||
- else if (soc_is_ar724x() || soc_is_ar913x())
|
||||
- ar724x_clocks_init(ath79_pll_base);
|
||||
- else if (soc_is_ar933x())
|
||||
- ar933x_clocks_init(ath79_pll_base);
|
||||
- else if (soc_is_ar934x())
|
||||
- ar934x_clocks_init(ath79_pll_base);
|
||||
- else if (soc_is_qca953x())
|
||||
- qca953x_clocks_init(ath79_pll_base);
|
||||
- else if (soc_is_qca955x())
|
||||
- qca955x_clocks_init(ath79_pll_base);
|
||||
- else if (soc_is_qca956x() || soc_is_tp9343())
|
||||
- qca956x_clocks_init(ath79_pll_base);
|
||||
- else
|
||||
- BUG();
|
||||
-
|
||||
- if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) {
|
||||
- wdt = "ahb";
|
||||
- uart = "ahb";
|
||||
- } else if (soc_is_ar933x()) {
|
||||
- wdt = "ahb";
|
||||
- uart = "ref";
|
||||
- } else {
|
||||
- wdt = "ref";
|
||||
- uart = "ref";
|
||||
- }
|
||||
-
|
||||
- clk_add_alias("wdt", NULL, wdt, NULL);
|
||||
- clk_add_alias("uart", NULL, uart, NULL);
|
||||
-}
|
||||
-
|
||||
-unsigned long __init
|
||||
-ath79_get_sys_clk_rate(const char *id)
|
||||
-{
|
||||
- struct clk *clk;
|
||||
- unsigned long rate;
|
||||
-
|
||||
- clk = clk_get(NULL, id);
|
||||
- if (IS_ERR(clk))
|
||||
- panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
|
||||
-
|
||||
- rate = clk_get_rate(clk);
|
||||
- clk_put(clk);
|
||||
-
|
||||
- return rate;
|
||||
-}
|
||||
-
|
||||
-#ifdef CONFIG_OF
|
||||
static void __init ath79_clocks_init_dt(struct device_node *np)
|
||||
{
|
||||
struct clk *ref_clk;
|
||||
@@ -727,5 +673,3 @@ CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-p
|
||||
CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt);
|
||||
CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt);
|
||||
CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt);
|
||||
-
|
||||
-#endif
|
||||
--- a/arch/mips/ath79/common.h
|
||||
+++ b/arch/mips/ath79/common.h
|
||||
@@ -19,9 +19,6 @@
|
||||
#define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024)
|
||||
#define ATH79_MEM_SIZE_MAX (256 * 1024 * 1024)
|
||||
|
||||
-void ath79_clocks_init(void);
|
||||
-unsigned long ath79_get_sys_clk_rate(const char *id);
|
||||
-
|
||||
void ath79_ddr_ctrl_init(void);
|
||||
|
||||
#endif /* __ATH79_COMMON_H */
|
||||
@ -0,0 +1,73 @@
|
||||
From c4e197bbcecc7233aa9e553e7047fa50e4e1fe77 Mon Sep 17 00:00:00 2001
|
||||
From: John Crispin <john@phrozen.org>
|
||||
Date: Mon, 25 Jun 2018 15:52:34 +0200
|
||||
Subject: [PATCH 33/33] spi: ath79: drop pdata support
|
||||
|
||||
The target is being converted to pure OF. We can therefore drop all of the
|
||||
platform data code from the driver.
|
||||
|
||||
Cc: linux-spi@vger.kernel.org
|
||||
Acked-by: Mark Brown <broonie@kernel.org>
|
||||
Signed-off-by: John Crispin <john@phrozen.org>
|
||||
---
|
||||
arch/mips/include/asm/mach-ath79/ath79_spi_platform.h | 19 -------------------
|
||||
drivers/spi/spi-ath79.c | 8 --------
|
||||
2 files changed, 27 deletions(-)
|
||||
delete mode 100644 arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
|
||||
|
||||
--- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
|
||||
+++ /dev/null
|
||||
@@ -1,19 +0,0 @@
|
||||
-/*
|
||||
- * Platform data definition for Atheros AR71XX/AR724X/AR913X SPI controller
|
||||
- *
|
||||
- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
|
||||
- *
|
||||
- * This program is free software; you can redistribute it and/or modify it
|
||||
- * under the terms of the GNU General Public License version 2 as published
|
||||
- * by the Free Software Foundation.
|
||||
- */
|
||||
-
|
||||
-#ifndef _ATH79_SPI_PLATFORM_H
|
||||
-#define _ATH79_SPI_PLATFORM_H
|
||||
-
|
||||
-struct ath79_spi_platform_data {
|
||||
- unsigned bus_num;
|
||||
- unsigned num_chipselect;
|
||||
-};
|
||||
-
|
||||
-#endif /* _ATH79_SPI_PLATFORM_H */
|
||||
--- a/drivers/spi/spi-ath79.c
|
||||
+++ b/drivers/spi/spi-ath79.c
|
||||
@@ -26,7 +26,6 @@
|
||||
#include <linux/err.h>
|
||||
|
||||
#include <asm/mach-ath79/ar71xx_regs.h>
|
||||
-#include <asm/mach-ath79/ath79_spi_platform.h>
|
||||
|
||||
#define DRV_NAME "ath79-spi"
|
||||
|
||||
@@ -208,7 +207,6 @@ static int ath79_spi_probe(struct platfo
|
||||
{
|
||||
struct spi_master *master;
|
||||
struct ath79_spi *sp;
|
||||
- struct ath79_spi_platform_data *pdata;
|
||||
struct resource *r;
|
||||
unsigned long rate;
|
||||
int ret;
|
||||
@@ -223,15 +221,9 @@ static int ath79_spi_probe(struct platfo
|
||||
master->dev.of_node = pdev->dev.of_node;
|
||||
platform_set_drvdata(pdev, sp);
|
||||
|
||||
- pdata = dev_get_platdata(&pdev->dev);
|
||||
-
|
||||
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
|
||||
master->setup = ath79_spi_setup;
|
||||
master->cleanup = ath79_spi_cleanup;
|
||||
- if (pdata) {
|
||||
- master->bus_num = pdata->bus_num;
|
||||
- master->num_chipselect = pdata->num_chipselect;
|
||||
- }
|
||||
|
||||
sp->bitbang.master = master;
|
||||
sp->bitbang.chipselect = ath79_spi_chipselect;
|
||||
@ -1,17 +0,0 @@
|
||||
--- a/arch/mips/ath79/clock.c
|
||||
+++ b/arch/mips/ath79/clock.c
|
||||
@@ -525,6 +525,14 @@ static void __init qca956x_clocks_init(v
|
||||
u32 cpu_pll, ddr_pll;
|
||||
u32 bootstrap;
|
||||
|
||||
+ /* QCA956x timer init workaround has to be applied right before setting
|
||||
+ * up the clock. Else, there will be no jiffies */
|
||||
+ u32 misc;
|
||||
+
|
||||
+ misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
|
||||
+ misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
|
||||
+ ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
|
||||
+
|
||||
bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
|
||||
if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
|
||||
ref_rate = 40 * 1000 * 1000;
|
||||
@ -0,0 +1,23 @@
|
||||
commit f3ffac90bc7266b7d917616f3233f58e8c08a196
|
||||
Author: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Fri Aug 10 23:24:47 2018 +0200
|
||||
|
||||
ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for AR9344
|
||||
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
|
||||
Index: linux-4.14.65/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||
===================================================================
|
||||
--- linux-4.14.65.orig/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||
+++ linux-4.14.65/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||
@@ -1229,6 +1229,10 @@
|
||||
#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
|
||||
#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
|
||||
#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
|
||||
+#define AR934X_ETH_CFG_TXD_DELAY_MASK 0x3
|
||||
+#define AR934X_ETH_CFG_TXD_DELAY_SHIFT 18
|
||||
+#define AR934X_ETH_CFG_TXE_DELAY_MASK 0x3
|
||||
+#define AR934X_ETH_CFG_TXE_DELAY_SHIFT 20
|
||||
|
||||
/*
|
||||
* QCA953X GMAC Interface
|
||||
Loading…
Reference in New Issue