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411 lines
12 KiB
Diff
411 lines
12 KiB
Diff
From 6aeb24b9508bbe91f89cd4eb21d0d7582d971146 Mon Sep 17 00:00:00 2001
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From: Weijie Gao <hackpascal@gmail.com>
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Date: Tue, 6 Mar 2018 08:48:31 +0100
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Subject: [PATCH 17/27] MIPS: ath79: add support for qca956x soc
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This patch adds soc support for QCA9561 and TP9343.
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TP9343 is a reduced version of QCA9561, which can be found in TP-LINK routers in China.
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The qca956x_wmac has not yet been supported by ath9k.
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tested on TL-WDR6500 and TL-WR882N v1 (Chinese version)
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Signed-off-by: Weijie Gao <hackpascal@gmail.com>
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---
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arch/mips/ath79/Kconfig | 2 +-
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arch/mips/ath79/clock.c | 96 ++++++++++++++++++++++++++++++++
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arch/mips/ath79/common.c | 4 ++
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arch/mips/ath79/dev-common.c | 7 ++-
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arch/mips/ath79/early_printk.c | 2 +
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arch/mips/ath79/irq.c | 87 ++++++++++++++++++++++++++++-
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arch/mips/ath79/pci.c | 12 ++++
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arch/mips/ath79/setup.c | 17 +++++-
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arch/mips/include/asm/mach-ath79/ath79.h | 22 ++++++++
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9 files changed, 245 insertions(+), 4 deletions(-)
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--- a/arch/mips/ath79/Kconfig
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+++ b/arch/mips/ath79/Kconfig
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@@ -119,7 +119,7 @@ config ATH79_DEV_USB
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def_bool n
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config ATH79_DEV_WMAC
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- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
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+ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X)
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def_bool n
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endif
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -525,6 +525,100 @@ static void __init qca955x_clocks_init(v
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clk_add_alias("uart", NULL, "ref", NULL);
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}
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+static void __init qca956x_clocks_init(void)
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+{
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+ unsigned long ref_rate;
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+ unsigned long cpu_rate;
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+ unsigned long ddr_rate;
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+ unsigned long ahb_rate;
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+ u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
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+ u32 cpu_pll, ddr_pll;
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+ u32 bootstrap;
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+
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+ bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
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+ if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
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+ ref_rate = 40 * 1000 * 1000;
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+ else
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+ ref_rate = 25 * 1000 * 1000;
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+
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+ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
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+ out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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+ QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
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+ ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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+ QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
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+
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+ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
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+ nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
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+ QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
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+ hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
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+ QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
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+ lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
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+ QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
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+
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+ cpu_pll = nint * ref_rate / ref_div;
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+ cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
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+ cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
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+ cpu_pll /= (1 << out_div);
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+
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+ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
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+ out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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+ QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
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+ ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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+ QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
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+ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
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+ nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
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+ QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
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+ hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
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+ QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
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+ lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
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+ QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
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+
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+ ddr_pll = nint * ref_rate / ref_div;
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+ ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
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+ ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
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+ ddr_pll /= (1 << out_div);
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+
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+ clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
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+
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+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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+ QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
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+ cpu_rate = ref_rate;
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+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
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+ cpu_rate = ddr_pll / (postdiv + 1);
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+ else
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+ cpu_rate = cpu_pll / (postdiv + 1);
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+
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+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
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+ QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
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+ ddr_rate = ref_rate;
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+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
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+ ddr_rate = cpu_pll / (postdiv + 1);
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+ else
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+ ddr_rate = ddr_pll / (postdiv + 1);
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+
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+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
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+ QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
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+ ahb_rate = ref_rate;
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+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
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+ ahb_rate = ddr_pll / (postdiv + 1);
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+ else
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+ ahb_rate = cpu_pll / (postdiv + 1);
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+
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+ ath79_add_sys_clkdev("ref", ref_rate);
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+ ath79_add_sys_clkdev("cpu", cpu_rate);
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+ ath79_add_sys_clkdev("ddr", ddr_rate);
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+ ath79_add_sys_clkdev("ahb", ahb_rate);
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+
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+ clk_add_alias("wdt", NULL, "ref", NULL);
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+ clk_add_alias("uart", NULL, "ref", NULL);
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+}
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+
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void __init ath79_clocks_init(void)
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{
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if (soc_is_ar71xx())
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@@ -539,6 +633,8 @@ void __init ath79_clocks_init(void)
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qca953x_clocks_init();
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else if (soc_is_qca955x())
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qca955x_clocks_init();
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+ else if (soc_is_qca956x() || soc_is_tp9343())
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+ qca956x_clocks_init();
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else
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BUG();
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}
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--- a/arch/mips/ath79/common.c
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+++ b/arch/mips/ath79/common.c
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@@ -107,6 +107,8 @@ void ath79_device_reset_set(u32 mask)
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reg = QCA953X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_RESET_MODULE;
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+ else if (soc_is_qca956x() || soc_is_tp9343())
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+ reg = QCA956X_RESET_REG_RESET_MODULE;
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else
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panic("Reset register not defined for this SOC");
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@@ -137,6 +139,8 @@ void ath79_device_reset_clear(u32 mask)
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reg = QCA953X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_RESET_MODULE;
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+ else if (soc_is_qca956x() || soc_is_tp9343())
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+ reg = QCA956X_RESET_REG_RESET_MODULE;
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else
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panic("Reset register not defined for this SOC");
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--- a/arch/mips/ath79/dev-common.c
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+++ b/arch/mips/ath79/dev-common.c
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@@ -86,7 +86,9 @@ void __init ath79_register_uart(void)
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soc_is_ar913x() ||
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soc_is_ar934x() ||
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soc_is_qca953x() ||
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- soc_is_qca955x()) {
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+ soc_is_qca955x() ||
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+ soc_is_qca956x() ||
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+ soc_is_tp9343()) {
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ath79_uart_data[0].uartclk = uart_clk_rate;
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platform_device_register(&ath79_uart_device);
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} else if (soc_is_ar933x()) {
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@@ -155,6 +157,9 @@ void __init ath79_gpio_init(void)
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} else if (soc_is_qca955x()) {
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ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
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ath79_gpio_pdata.oe_inverted = 1;
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+ } else if (soc_is_qca956x() || soc_is_tp9343()) {
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+ ath79_gpio_pdata.ngpios = QCA956X_GPIO_COUNT;
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+ ath79_gpio_pdata.oe_inverted = 1;
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} else {
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BUG();
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}
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--- a/arch/mips/ath79/early_printk.c
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+++ b/arch/mips/ath79/early_printk.c
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@@ -120,6 +120,8 @@ static void prom_putchar_init(void)
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case REV_ID_MAJOR_QCA9533_V2:
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case REV_ID_MAJOR_QCA9556:
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case REV_ID_MAJOR_QCA9558:
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+ case REV_ID_MAJOR_TP9343:
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+ case REV_ID_MAJOR_QCA956X:
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_prom_putchar = prom_putchar_ar71xx;
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break;
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--- a/arch/mips/ath79/irq.c
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+++ b/arch/mips/ath79/irq.c
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@@ -156,6 +156,87 @@ static void qca955x_irq_init(void)
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irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
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}
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+static void qca956x_ip2_irq_dispatch(struct irq_desc *desc)
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+{
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+ u32 status;
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+
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+ status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
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+ status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL;
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+
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+ if (status == 0) {
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+ spurious_interrupt();
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+ return;
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+ }
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+
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+ if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) {
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+ /* TODO: flush DDR? */
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+ generic_handle_irq(ATH79_IP2_IRQ(0));
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+ }
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+
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+ if (status & QCA956X_EXT_INT_WMAC_ALL) {
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+ /* TODO: flsuh DDR? */
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+ generic_handle_irq(ATH79_IP2_IRQ(1));
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+ }
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+}
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+
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+static void qca956x_ip3_irq_dispatch(struct irq_desc *desc)
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+{
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+ u32 status;
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+
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+ status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
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+ status &= QCA956X_EXT_INT_PCIE_RC2_ALL |
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+ QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2;
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+
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+ if (status == 0) {
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+ spurious_interrupt();
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+ return;
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+ }
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+
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+ if (status & QCA956X_EXT_INT_USB1) {
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+ /* TODO: flush DDR? */
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+ generic_handle_irq(ATH79_IP3_IRQ(0));
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+ }
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+
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+ if (status & QCA956X_EXT_INT_USB2) {
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+ /* TODO: flush DDR? */
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+ generic_handle_irq(ATH79_IP3_IRQ(1));
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+ }
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+
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+ if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) {
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+ /* TODO: flush DDR? */
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+ generic_handle_irq(ATH79_IP3_IRQ(2));
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+ }
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+}
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+
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+static void qca956x_enable_timer_cb(void) {
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+ u32 misc;
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+
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+ misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
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+ misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
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+ ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
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+}
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+
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+static void qca956x_irq_init(void)
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+{
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+ int i;
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+
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+ for (i = ATH79_IP2_IRQ_BASE;
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+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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+ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
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+
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+ irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
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+
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+ for (i = ATH79_IP3_IRQ_BASE;
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+ i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
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+ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
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+
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+ irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
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+
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+ /* QCA956x timer init workaround has to be applied right before setting
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+ * up the clock. Else, there will be no jiffies */
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+ late_time_init = &qca956x_enable_timer_cb;
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+}
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+
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void __init arch_init_irq(void)
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{
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unsigned irq_wb_chan2 = -1;
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@@ -183,7 +264,9 @@ void __init arch_init_irq(void)
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soc_is_ar933x() ||
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soc_is_ar934x() ||
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soc_is_qca953x() ||
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- soc_is_qca955x())
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+ soc_is_qca955x() ||
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+ soc_is_qca956x() ||
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+ soc_is_tp9343())
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misc_is_ar71xx = false;
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else
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BUG();
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@@ -197,4 +280,6 @@ void __init arch_init_irq(void)
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qca953x_irq_init();
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else if (soc_is_qca955x())
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qca955x_irq_init();
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+ else if (soc_is_qca956x() || soc_is_tp9343())
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+ qca956x_irq_init();
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}
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--- a/arch/mips/ath79/pci.c
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+++ b/arch/mips/ath79/pci.c
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@@ -82,6 +82,9 @@ int pcibios_map_irq(const struct pci_dev
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} else if (soc_is_qca955x()) {
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ath79_pci_irq_map = qca955x_pci_irq_map;
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ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
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+ } else if (soc_is_qca956x()) {
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+ ath79_pci_irq_map = qca956x_pci_irq_map;
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+ ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map);
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} else {
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pr_crit("pci %s: invalid irq map\n",
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pci_name((struct pci_dev *) dev));
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@@ -261,6 +264,15 @@ int __init ath79_register_pci(void)
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QCA955X_PCI_MEM_SIZE,
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1,
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ATH79_IP3_IRQ(2));
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+ } else if (soc_is_qca956x()) {
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+ pdev = ath79_register_pci_ar724x(0,
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+ QCA956X_PCI_CFG_BASE1,
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+ QCA956X_PCI_CTRL_BASE1,
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+ QCA956X_PCI_CRP_BASE1,
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+ QCA956X_PCI_MEM_BASE1,
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+ QCA956X_PCI_MEM_SIZE,
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+ 1,
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+ ATH79_IP3_IRQ(2));
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} else {
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/* No PCI support */
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return -ENODEV;
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--- a/arch/mips/ath79/setup.c
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+++ b/arch/mips/ath79/setup.c
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@@ -176,6 +176,18 @@ static void __init ath79_detect_sys_type
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rev = id & QCA955X_REV_ID_REVISION_MASK;
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break;
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+ case REV_ID_MAJOR_QCA956X:
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+ ath79_soc = ATH79_SOC_QCA956X;
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+ chip = "956X";
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+ rev = id & QCA956X_REV_ID_REVISION_MASK;
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+ break;
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+
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+ case REV_ID_MAJOR_TP9343:
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+ ath79_soc = ATH79_SOC_TP9343;
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+ chip = "9343";
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+ rev = id & QCA956X_REV_ID_REVISION_MASK;
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+ break;
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+
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default:
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panic("ath79: unknown SoC, id:0x%08x", id);
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}
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@@ -183,9 +195,12 @@ static void __init ath79_detect_sys_type
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if (ver == 1)
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ath79_soc_rev = rev;
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- if (soc_is_qca953x() || soc_is_qca955x())
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+ if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
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sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
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chip, ver, rev);
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+ else if (soc_is_tp9343())
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+ sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
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+ chip, rev);
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else
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sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
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pr_info("SoC: %s\n", ath79_sys_type);
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--- a/arch/mips/include/asm/mach-ath79/ath79.h
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+++ b/arch/mips/include/asm/mach-ath79/ath79.h
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@@ -35,6 +35,8 @@ enum ath79_soc_type {
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ATH79_SOC_QCA9533,
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ATH79_SOC_QCA9556,
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ATH79_SOC_QCA9558,
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+ ATH79_SOC_TP9343,
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+ ATH79_SOC_QCA956X,
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};
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extern enum ath79_soc_type ath79_soc;
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@@ -126,6 +128,26 @@ static inline int soc_is_qca955x(void)
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return soc_is_qca9556() || soc_is_qca9558();
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}
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+static inline int soc_is_tp9343(void)
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+{
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+ return ath79_soc == ATH79_SOC_TP9343;
|
|
+}
|
|
+
|
|
+static inline int soc_is_qca9561(void)
|
|
+{
|
|
+ return ath79_soc == ATH79_SOC_QCA956X;
|
|
+}
|
|
+
|
|
+static inline int soc_is_qca9563(void)
|
|
+{
|
|
+ return ath79_soc == ATH79_SOC_QCA956X;
|
|
+}
|
|
+
|
|
+static inline int soc_is_qca956x(void)
|
|
+{
|
|
+ return soc_is_qca9561() || soc_is_qca9563();
|
|
+}
|
|
+
|
|
void ath79_ddr_wb_flush(unsigned int reg);
|
|
void ath79_ddr_set_pci_windows(void);
|
|
|