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332 lines
9.9 KiB
Diff
332 lines
9.9 KiB
Diff
From cff23ba486e3c5d17c4d7e446f5eddead855c101 Mon Sep 17 00:00:00 2001
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From: John Crispin <john@phrozen.org>
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Date: Tue, 6 Mar 2018 08:45:55 +0100
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Subject: [PATCH 16/27] MIPS: ath79: add support for QCA953x SoC
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Note that the clock calculation looks very similar to the QCA955x, but the
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meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
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---
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arch/mips/ath79/Kconfig | 6 ++-
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arch/mips/ath79/clock.c | 87 ++++++++++++++++++++++++++++++++
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arch/mips/ath79/common.c | 4 ++
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arch/mips/ath79/dev-common.c | 4 ++
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arch/mips/ath79/early_printk.c | 2 +
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arch/mips/ath79/irq.c | 33 +++++++++++-
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arch/mips/ath79/setup.c | 21 ++++++--
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arch/mips/include/asm/mach-ath79/ath79.h | 11 ++++
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8 files changed, 162 insertions(+), 6 deletions(-)
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--- a/arch/mips/ath79/Kconfig
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+++ b/arch/mips/ath79/Kconfig
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@@ -94,6 +94,10 @@ config SOC_AR934X
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select PCI_AR724X if PCI
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def_bool n
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+config SOC_QCA953X
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+ select USB_ARCH_HAS_EHCI
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+ def_bool n
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+
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config SOC_QCA955X
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select HW_HAS_PCI
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select PCI_AR724X if PCI
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@@ -115,7 +119,7 @@ config ATH79_DEV_USB
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def_bool n
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config ATH79_DEV_WMAC
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- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
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+ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
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def_bool n
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endif
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -355,6 +355,91 @@ static void __init ar934x_clocks_init(vo
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iounmap(dpll_base);
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}
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+static void __init qca953x_clocks_init(void)
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+{
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+ unsigned long ref_rate;
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+ unsigned long cpu_rate;
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+ unsigned long ddr_rate;
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+ unsigned long ahb_rate;
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+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
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+ u32 cpu_pll, ddr_pll;
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+ u32 bootstrap;
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+
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+ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
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+ if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
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+ ref_rate = 40 * 1000 * 1000;
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+ else
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+ ref_rate = 25 * 1000 * 1000;
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+
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+ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
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+ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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+ QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
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+ ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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+ QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
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+ nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
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+ QCA953X_PLL_CPU_CONFIG_NINT_MASK;
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+ frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
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+ QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
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+
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+ cpu_pll = nint * ref_rate / ref_div;
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+ cpu_pll += frac * (ref_rate >> 6) / ref_div;
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+ cpu_pll /= (1 << out_div);
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+
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+ pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
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+ out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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+ QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
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+ ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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+ QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
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+ nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
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+ QCA953X_PLL_DDR_CONFIG_NINT_MASK;
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+ frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
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+ QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
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+
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+ ddr_pll = nint * ref_rate / ref_div;
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+ ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
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+ ddr_pll /= (1 << out_div);
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+
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+ clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
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+
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+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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+ QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
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+ cpu_rate = ref_rate;
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+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
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+ cpu_rate = cpu_pll / (postdiv + 1);
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+ else
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+ cpu_rate = ddr_pll / (postdiv + 1);
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+
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+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
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+ QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
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+ ddr_rate = ref_rate;
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+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
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+ ddr_rate = ddr_pll / (postdiv + 1);
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+ else
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+ ddr_rate = cpu_pll / (postdiv + 1);
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+
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+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
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+ QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
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+ ahb_rate = ref_rate;
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+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
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+ ahb_rate = ddr_pll / (postdiv + 1);
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+ else
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+ ahb_rate = cpu_pll / (postdiv + 1);
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+
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+ ath79_add_sys_clkdev("ref", ref_rate);
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+ ath79_add_sys_clkdev("cpu", cpu_rate);
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+ ath79_add_sys_clkdev("ddr", ddr_rate);
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+ ath79_add_sys_clkdev("ahb", ahb_rate);
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+
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+ clk_add_alias("wdt", NULL, "ref", NULL);
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+ clk_add_alias("uart", NULL, "ref", NULL);
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+}
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+
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static void __init qca955x_clocks_init(void)
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{
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unsigned long ref_rate;
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@@ -450,6 +535,8 @@ void __init ath79_clocks_init(void)
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ar933x_clocks_init();
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else if (soc_is_ar934x())
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ar934x_clocks_init();
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+ else if (soc_is_qca953x())
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+ qca953x_clocks_init();
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else if (soc_is_qca955x())
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qca955x_clocks_init();
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else
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--- a/arch/mips/ath79/common.c
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+++ b/arch/mips/ath79/common.c
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@@ -103,6 +103,8 @@ void ath79_device_reset_set(u32 mask)
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reg = AR933X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar934x())
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reg = AR934X_RESET_REG_RESET_MODULE;
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+ else if (soc_is_qca953x())
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+ reg = QCA953X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_RESET_MODULE;
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else
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@@ -131,6 +133,8 @@ void ath79_device_reset_clear(u32 mask)
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reg = AR933X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar934x())
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reg = AR934X_RESET_REG_RESET_MODULE;
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+ else if (soc_is_qca953x())
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+ reg = QCA953X_RESET_REG_RESET_MODULE;
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_RESET_MODULE;
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else
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--- a/arch/mips/ath79/dev-common.c
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+++ b/arch/mips/ath79/dev-common.c
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@@ -85,6 +85,7 @@ void __init ath79_register_uart(void)
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soc_is_ar724x() ||
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soc_is_ar913x() ||
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soc_is_ar934x() ||
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+ soc_is_qca953x() ||
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soc_is_qca955x()) {
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ath79_uart_data[0].uartclk = uart_clk_rate;
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platform_device_register(&ath79_uart_device);
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@@ -148,6 +149,9 @@ void __init ath79_gpio_init(void)
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} else if (soc_is_ar934x()) {
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ath79_gpio_pdata.ngpios = AR934X_GPIO_COUNT;
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ath79_gpio_pdata.oe_inverted = 1;
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+ } else if (soc_is_qca953x()) {
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+ ath79_gpio_pdata.ngpios = QCA953X_GPIO_COUNT;
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+ ath79_gpio_pdata.oe_inverted = 1;
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} else if (soc_is_qca955x()) {
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ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
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ath79_gpio_pdata.oe_inverted = 1;
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--- a/arch/mips/ath79/early_printk.c
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+++ b/arch/mips/ath79/early_printk.c
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@@ -116,6 +116,8 @@ static void prom_putchar_init(void)
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case REV_ID_MAJOR_AR9341:
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case REV_ID_MAJOR_AR9342:
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case REV_ID_MAJOR_AR9344:
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+ case REV_ID_MAJOR_QCA9533:
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+ case REV_ID_MAJOR_QCA9533_V2:
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case REV_ID_MAJOR_QCA9556:
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case REV_ID_MAJOR_QCA9558:
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_prom_putchar = prom_putchar_ar71xx;
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--- a/arch/mips/ath79/irq.c
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+++ b/arch/mips/ath79/irq.c
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@@ -56,6 +56,34 @@ static void ar934x_ip2_irq_init(void)
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irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
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}
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+static void qca953x_ip2_irq_dispatch(struct irq_desc *desc)
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+{
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+ u32 status;
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+
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+ status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
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+
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+ if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
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+ ath79_ddr_wb_flush(3);
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+ generic_handle_irq(ATH79_IP2_IRQ(0));
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+ } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
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+ ath79_ddr_wb_flush(4);
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+ generic_handle_irq(ATH79_IP2_IRQ(1));
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+ } else {
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+ spurious_interrupt();
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+ }
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+}
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+
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+static void qca953x_irq_init(void)
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+{
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+ int i;
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+
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+ for (i = ATH79_IP2_IRQ_BASE;
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+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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+ irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
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+
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+ irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
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+}
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+
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static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
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{
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u32 status;
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@@ -143,7 +171,7 @@ void __init arch_init_irq(void)
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soc_is_ar913x() || soc_is_ar933x()) {
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irq_wb_chan2 = 3;
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irq_wb_chan3 = 2;
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- } else if (soc_is_ar934x()) {
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+ } else if (soc_is_ar934x() || soc_is_qca953x()) {
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irq_wb_chan3 = 2;
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}
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@@ -154,6 +182,7 @@ void __init arch_init_irq(void)
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else if (soc_is_ar724x() ||
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soc_is_ar933x() ||
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soc_is_ar934x() ||
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+ soc_is_qca953x() ||
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soc_is_qca955x())
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misc_is_ar71xx = false;
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else
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@@ -164,6 +193,8 @@ void __init arch_init_irq(void)
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if (soc_is_ar934x())
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ar934x_ip2_irq_init();
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+ else if (soc_is_qca953x())
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+ qca953x_irq_init();
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else if (soc_is_qca955x())
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qca955x_irq_init();
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}
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--- a/arch/mips/ath79/setup.c
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+++ b/arch/mips/ath79/setup.c
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@@ -60,6 +60,7 @@ static void __init ath79_detect_sys_type
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u32 major;
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u32 minor;
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u32 rev = 0;
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+ u32 ver = 1;
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id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
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major = id & REV_ID_MAJOR_MASK;
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@@ -152,6 +153,17 @@ static void __init ath79_detect_sys_type
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rev = id & AR934X_REV_ID_REVISION_MASK;
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break;
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+ case REV_ID_MAJOR_QCA9533_V2:
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+ ver = 2;
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+ ath79_soc_rev = 2;
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+ /* drop through */
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+
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+ case REV_ID_MAJOR_QCA9533:
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+ ath79_soc = ATH79_SOC_QCA9533;
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+ chip = "9533";
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+ rev = id & QCA953X_REV_ID_REVISION_MASK;
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+ break;
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+
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case REV_ID_MAJOR_QCA9556:
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ath79_soc = ATH79_SOC_QCA9556;
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chip = "9556";
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@@ -168,11 +180,12 @@ static void __init ath79_detect_sys_type
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panic("ath79: unknown SoC, id:0x%08x", id);
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}
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- ath79_soc_rev = rev;
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+ if (ver == 1)
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+ ath79_soc_rev = rev;
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- if (soc_is_qca955x())
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- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
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- chip, rev);
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+ if (soc_is_qca953x() || soc_is_qca955x())
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+ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
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+ chip, ver, rev);
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else
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sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
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pr_info("SoC: %s\n", ath79_sys_type);
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--- a/arch/mips/include/asm/mach-ath79/ath79.h
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+++ b/arch/mips/include/asm/mach-ath79/ath79.h
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@@ -32,6 +32,7 @@ enum ath79_soc_type {
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ATH79_SOC_AR9341,
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ATH79_SOC_AR9342,
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ATH79_SOC_AR9344,
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+ ATH79_SOC_QCA9533,
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ATH79_SOC_QCA9556,
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ATH79_SOC_QCA9558,
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};
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@@ -100,6 +101,16 @@ static inline int soc_is_ar934x(void)
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return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
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}
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+static inline int soc_is_qca9533(void)
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+{
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+ return ath79_soc == ATH79_SOC_QCA9533;
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+}
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+
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+static inline int soc_is_qca953x(void)
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+{
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+ return soc_is_qca9533();
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+}
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+
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static inline int soc_is_qca9556(void)
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{
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return ath79_soc == ATH79_SOC_QCA9556;
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