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233 lines
6.6 KiB
C
233 lines
6.6 KiB
C
/******************************************************************************
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**
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** FILE NAME : ifxmips_deu.h
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** DESCRIPTION : Data Encryption Unit Driver
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** COPYRIGHT : Copyright (c) 2009
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** Infineon Technologies AG
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** Am Campeon 1-12, 85579 Neubiberg, Germany
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**
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** This program is free software; you can redistribute it and/or modify
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** it under the terms of the GNU General Public License as published by
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** the Free Software Foundation; either version 2 of the License, or
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** (at your option) any later version.
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**
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** HISTORY
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** $Date $Author $Comment
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** 08,Sept 2009 Mohammad Firdaus Initial UEIP release
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*******************************************************************************/
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/*!
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\defgroup IFX_DEU IFX_DEU_DRIVERS
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\ingroup API
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\brief ifx deu driver module
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*/
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/*!
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\file ifxmips_deu.h
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\brief main deu driver header file
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*/
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/*!
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\defgroup IFX_DEU_DEFINITIONS IFX_DEU_DEFINITIONS
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\ingroup IFX_DEU
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\brief ifx deu definitions
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*/
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#ifndef IFXMIPS_DEU_H
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#define IFXMIPS_DEU_H
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#include <crypto/algapi.h>
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#include <linux/interrupt.h>
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#define IFXDEU_ALIGNMENT 16
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#define IFX_DEU_BASE_ADDR (KSEG1 | 0x1E103100)
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#define IFX_DEU_CLK ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0000))
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#define IFX_DES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0010))
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#define IFX_AES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050))
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#define IFX_HASH_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B0))
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#define IFX_ARC4_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0100))
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#define PFX "ifxdeu: "
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#define CLC_START IFX_DEU_CLK
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#define IFXDEU_CRA_PRIORITY 300
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#define IFXDEU_COMPOSITE_PRIORITY 400
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//#define KSEG1 0xA0000000
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#define IFX_PMU_ENABLE 1
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#define IFX_PMU_DISABLE 0
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#define CRYPTO_DIR_ENCRYPT 1
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#define CRYPTO_DIR_DECRYPT 0
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#define AES_IDLE 0
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#define AES_BUSY 1
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#define AES_STARTED 2
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#define AES_COMPLETED 3
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#define DES_IDLE 0
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#define DES_BUSY 1
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#define DES_STARTED 2
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#define DES_COMPLETED 3
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#define PROCESS_SCATTER 1
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#define PROCESS_NEW_PACKET 2
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#define PMU_DEU BIT(20)
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#define START_DEU_POWER \
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do { \
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volatile struct clc_controlr_t *clc = (struct clc_controlr_t *) CLC_START; \
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ltq_pmu_enable(PMU_DEU); \
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clc->FSOE = 0; \
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clc->SBWE = 0; \
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clc->SPEN = 0; \
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clc->SBWE = 0; \
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clc->DISS = 0; \
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clc->DISR = 0; \
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} while(0)
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#define STOP_DEU_POWER \
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do { \
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volatile struct clc_controlr_t *clc = (struct clc_controlr_t *) CLC_START; \
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ltq_pmu_disable(PMU_DEU); \
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clc->FSOE = 1; \
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clc->SBWE = 1; \
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clc->SPEN = 1; \
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clc->SBWE = 1; \
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clc->DISS = 1; \
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clc->DISR = 1; \
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} while (0)
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/*
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* Not used anymore in UEIP (use IFX_DES_CON, IFX_AES_CON, etc instead)
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* #define DEU_BASE (KSEG1+0x1E103100)
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* #define DES_CON (DEU_BASE+0x10)
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* #define AES_CON (DEU_BASE+0x50)
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* #define HASH_CON (DEU_BASE+0xB0)
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* #define DMA_CON (DEU_BASE+0xEC)
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* #define INT_CON (DEU_BASE+0xF4)
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* #define ARC4_CON (DEU_BASE+0x100)
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*/
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int ifxdeu_init_des (void);
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int ifxdeu_init_aes (void);
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int ifxdeu_init_arc4 (void);
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int ifxdeu_init_sha1 (void);
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int ifxdeu_init_md5 (void);
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int ifxdeu_init_sha1_hmac (void);
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int ifxdeu_init_md5_hmac (void);
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int __init lqdeu_async_aes_init(void);
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int __init lqdeu_async_des_init(void);
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void ifxdeu_fini_des (void);
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void ifxdeu_fini_aes (void);
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void ifxdeu_fini_arc4 (void);
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void ifxdeu_fini_sha1 (void);
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void ifxdeu_fini_md5 (void);
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void ifxdeu_fini_sha1_hmac (void);
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void ifxdeu_fini_md5_hmac (void);
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void __exit ifxdeu_fini_dma(void);
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void __exit lqdeu_fini_async_aes(void);
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void __exit lqdeu_fini_async_des(void);
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void __exit deu_fini (void);
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int deu_dma_init (void);
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#define DEU_WAKELIST_INIT(queue) \
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init_waitqueue_head(&queue)
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#define DEU_WAIT_EVENT_TIMEOUT(queue, event, flags, timeout) \
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do { \
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wait_event_interruptible_timeout((queue), \
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test_bit((event), &(flags)), (timeout)); \
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clear_bit((event), &(flags)); \
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}while (0)
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#define DEU_WAKEUP_EVENT(queue, event, flags) \
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do { \
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set_bit((event), &(flags)); \
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wake_up_interruptible(&(queue)); \
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}while (0)
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#define DEU_WAIT_EVENT(queue, event, flags) \
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do { \
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wait_event_interruptible(queue, \
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test_bit((event), &(flags))); \
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clear_bit((event), &(flags)); \
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}while (0)
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typedef struct deu_drv_priv {
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wait_queue_head_t deu_thread_wait;
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#define DEU_EVENT 1
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#define DES_ASYNC_EVENT 2
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#define AES_ASYNC_EVENT 3
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volatile long des_event_flags;
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volatile long aes_event_flags;
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volatile long deu_event_flags;
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int event_src;
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u32 *deu_rx_buf;
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u32 *outcopy;
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u32 deu_rx_len;
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struct aes_priv *aes_dataptr;
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struct des_priv *des_dataptr;
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}deu_drv_priv_t;
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/**
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* struct aes_priv_t - ASYNC AES
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* @lock: spinlock lock
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* @lock_flag: flag for spinlock activities
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* @list: crypto queue API list
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* @hw_status: DEU hw status flag
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* @aes_wait_flag: flag for sleep queue
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* @aes_wait_queue: queue attributes for aes
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* @bytes_processed: number of bytes to process by DEU
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* @aes_pid: pid number for AES thread
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* @aes_sync: atomic wait sync for AES
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*
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*/
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typedef struct {
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spinlock_t lock;
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struct crypto_queue list;
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unsigned int hw_status;
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volatile long aes_wait_flag;
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wait_queue_head_t aes_wait_queue;
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pid_t aes_pid;
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struct tasklet_struct aes_task;
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} aes_priv_t;
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/**
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* struct des_priv_t - ASYNC DES
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* @lock: spinlock lock
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* @list: crypto queue API list
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* @hw_status: DEU hw status flag
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* @des_wait_flag: flag for sleep queue
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* @des_wait_queue: queue attributes for des
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* @des_pid: pid number for DES thread
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* @des_sync: atomic wait sync for DES
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*
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*/
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typedef struct {
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spinlock_t lock;
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struct crypto_queue list;
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unsigned int hw_status;
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volatile long des_wait_flag;
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wait_queue_head_t des_wait_queue;
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pid_t des_pid;
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struct tasklet_struct des_task;
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} des_priv_t;
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#endif /* IFXMIPS_DEU_H */
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