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54 lines
1.9 KiB
Diff
54 lines
1.9 KiB
Diff
From 940e9a5828480e4185c9a276ad7f35a4069a2393 Mon Sep 17 00:00:00 2001
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From: Pawel Dembicki <paweldembicki@gmail.com>
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Date: Thu, 23 Jan 2020 22:04:15 +0100
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Subject: [PATCH 1/2] phy: mv88e61xx: add support for RGMII TX/RX delay
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Clock delay in RGMII is required for some boards.
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This patch introduce CONFIG_MV88E61XX_CPU_PORT_TX_DELAY and
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CONFIG_MV88E61XX_CPU_PORT_RX_DELAY defines, which are setting
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proper bits in PORT_REG_PHYS_CTRL register.
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Cc: Chris Packham <judge.packham@gmail.com>
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Cc: Joe Hershberger <joe.hershberger@ni.com>
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Cc: Anatolij Gustschin <agust@denx.de>
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Cc: Tim Harvey <tharvey@gateworks.com>
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Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
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---
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drivers/net/phy/mv88e61xx.c | 11 ++++++++++-
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1 file changed, 10 insertions(+), 1 deletion(-)
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diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c
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index 5aff7ed397..889327639d 100644
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--- a/drivers/net/phy/mv88e61xx.c
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+++ b/drivers/net/phy/mv88e61xx.c
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@@ -94,6 +94,8 @@
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#define PORT_REG_STATUS_CMODE_1000BASE_X 0x9
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#define PORT_REG_STATUS_CMODE_SGMII 0xa
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+#define PORT_REG_PHYS_CTRL_RGMII_RX_DELAY BIT(15)
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+#define PORT_REG_PHYS_CTRL_RGMII_TX_DELAY BIT(14)
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#define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10)
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#define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9)
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#define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7)
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@@ -747,9 +749,16 @@ static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port)
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PORT_REG_PHYS_CTRL_SPD1000;
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}
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- if (port == CONFIG_MV88E61XX_CPU_PORT)
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+ if (port == CONFIG_MV88E61XX_CPU_PORT) {
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val |= PORT_REG_PHYS_CTRL_LINK_VALUE |
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PORT_REG_PHYS_CTRL_LINK_FORCE;
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+#if defined(CONFIG_MV88E61XX_CPU_PORT_RX_DELAY)
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+ val |= PORT_REG_PHYS_CTRL_RGMII_RX_DELAY;
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+#endif
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+#if defined(CONFIG_MV88E61XX_CPU_PORT_TX_DELAY)
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+ val |= PORT_REG_PHYS_CTRL_RGMII_TX_DELAY;
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+#endif
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+ }
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return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
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val);
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--
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2.20.1
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