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663 lines
19 KiB
Diff
663 lines
19 KiB
Diff
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arm: kirkwood: add ZyXEL NSA310 device
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This patch add ZyXEL NSA310 1-Bay Media Server
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The ZyXEL NSA310 device is a Kirkwood based NAS:
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- SoC: Marvell 88F6702 1200Mhz
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- SDRAM memory: 256MB DDR2 400Mhz
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- Gigabit ethernet: PHY Realtek
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- Flash memory: 128MB
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- 1 Power button
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- 1 Power LED (blue)
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- 5 Status LED (green/red)
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- 1 Copy/Sync button
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- 1 Reset button
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- 2 SATA II port (1 internal and 1 external eSata)
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- 2 USB 2.0 ports (1 front and 1 back)
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- Smart fan
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Signed-off-by: Alberto Bursi <alberto.bursi@outlook.it>
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NOTE: this patch is ready for upstream, LEDE-specific parts are in
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another patch
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--- a/arch/arm/mach-kirkwood/Kconfig
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+++ b/arch/arm/mach-kirkwood/Kconfig
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@@ -53,6 +53,9 @@ config TARGET_GOFLEXHOME
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config TARGET_NAS220
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bool "BlackArmor NAS220"
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+config TARGET_NSA310
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+ bool "Zyxel NSA310 Board"
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+
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config TARGET_NSA310S
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bool "Zyxel NSA310S"
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@@ -86,6 +89,7 @@ source "board/raidsonic/ib62x0/Kconfig"
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source "board/Seagate/dockstar/Kconfig"
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source "board/Seagate/goflexhome/Kconfig"
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source "board/Seagate/nas220/Kconfig"
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+source "board/zyxel/nsa310/Kconfig"
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source "board/zyxel/nsa310s/Kconfig"
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source "board/alliedtelesis/SBx81LIFKW/Kconfig"
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source "board/alliedtelesis/SBx81LIFXCAT/Kconfig"
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--- /dev/null
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+++ b/board/zyxel/nsa310/Kconfig
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@@ -0,0 +1,12 @@
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+if TARGET_NSA310
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+
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+config SYS_BOARD
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+ default "nsa310"
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+
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+config SYS_VENDOR
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+ default "zyxel"
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+
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+config SYS_CONFIG_NAME
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+ default "nsa310"
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+
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+endif
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--- /dev/null
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+++ b/board/zyxel/nsa310/MAINTAINERS
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@@ -0,0 +1,6 @@
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+NSA310 BOARD
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+M: Alberto Bursi <alberto.bursi@outlook.it>
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+S: Maintained
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+F: board/zyxel/nsa310/
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+F: include/configs/nsa310.h
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+F: configs/nsa310_defconfig
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--- /dev/null
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+++ b/board/zyxel/nsa310/Makefile
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@@ -0,0 +1,12 @@
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+#
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+# (C) Copyright 2015 bodhi <mibodhi@gmail.com>
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+#
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+# Based on
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+# (C) Copyright 2009
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+# Marvell Semiconductor <www.marvell.com>
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+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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+#
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+# SPDX-License-Identifier: GPL-2.0+
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+#
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+
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+obj-y := nsa310.o
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--- /dev/null
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+++ b/board/zyxel/nsa310/kwbimage.cfg
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@@ -0,0 +1,166 @@
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+#
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+# Copyright (C) 2013 Rafal Kazmierowski
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+#
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+# Based on guruplug.c originally written by
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+# Siddarth Gore <gores@marvell.com>
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+# (C) Copyright 2009
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+# Marvell Semiconductor <www.marvell.com>
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+#
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+# See file CREDITS for list of people who contributed to this
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+# project.
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+#
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+# This program is free software; you can redistribute it and/or
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+# modify it under the terms of the GNU General Public License as
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+# published by the Free Software Foundation; either version 2 of
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+# the License, or (at your option) any later version.
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+#
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+# This program is distributed in the hope that it will be useful,
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+# but WITHOUT ANY WARRANTY; without even the implied warranty of
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+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+# GNU General Public License for more details.
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+#
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+# You should have received a copy of the GNU General Public License
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+# along with this program; if not, write to the Free Software
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+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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+# MA 02110-1301 USA
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+#
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+# Refer docs/README.kwimage for more details about how-to configure
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+# and create kirkwood boot image
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+#
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+
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+# Boot Media configurations
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+BOOT_FROM nand
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+#BOOT_FROM uart
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+NAND_ECC_MODE default
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+NAND_PAGE_SIZE 0x0800
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+
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+# SOC registers configuration using bootrom header extension
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+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
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+
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+# Configure RGMII-0 interface pad voltage to 1.8V
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+DATA 0xFFD100e0 0x1b1b1b9b
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+
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+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
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+DATA 0xFFD01400 0x43010c30 # DDR Configuration register
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+# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
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+# bit23-14: zero
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+# bit24: 1= enable exit self refresh mode on DDR access
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+# bit25: 1 required
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+# bit29-26: zero
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+# bit31-30: 01
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+
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+DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
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+# bit 4: 0=addr/cmd in smame cycle
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+# bit 5: 0=clk is driven during self refresh, we don't care for APX
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+# bit 6: 0=use recommended falling edge of clk for addr/cmd
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+# bit14: 0=input buffer always powered up
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+# bit18: 1=cpu lock transaction enabled
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+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
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+# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
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+# bit30-28: 3 required
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+# bit31: 0=no additional STARTBURST delay
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+
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+DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
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+# bit3-0: TRAS lsbs
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+# bit7-4: TRCD
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+# bit11- 8: TRP
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+# bit15-12: TWR
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+# bit19-16: TWTR
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+# bit20: TRAS msb
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+# bit23-21: 0x0
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+# bit27-24: TRRD
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+# bit31-28: TRTP
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+
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+DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
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+# bit6-0: TRFC
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+# bit8-7: TR2R
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+# bit10-9: TR2W
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+# bit12-11: TW2W
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+# bit31-13: zero required
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+
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+DATA 0xFFD01410 0x0000000c # DDR Address Control
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+# bit1-0: 01, Cs0width=x8
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+# bit3-2: 10, Cs0size=1Gb
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+# bit5-4: 01, Cs1width=x8
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+# bit7-6: 10, Cs1size=1Gb
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+# bit9-8: 00, Cs2width=nonexistent
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+# bit11-10: 00, Cs2size =nonexistent
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+# bit13-12: 00, Cs3width=nonexistent
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+# bit15-14: 00, Cs3size =nonexistent
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+# bit16: 0, Cs0AddrSel
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+# bit17: 0, Cs1AddrSel
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+# bit18: 0, Cs2AddrSel
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+# bit19: 0, Cs3AddrSel
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+# bit31-20: 0 required
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+
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+DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
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+# bit0: 0, OpenPage enabled
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+# bit31-1: 0 required
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+
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+DATA 0xFFD01418 0x00000000 # DDR Operation
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+# bit3-0: 0x0, DDR cmd
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+# bit31-4: 0 required
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+
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+DATA 0xFFD0141C 0x00000652 # DDR Mode
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+# bit2-0: 2, BurstLen=2 required
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+# bit3: 0, BurstType=0 required
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+# bit6-4: 4, CL=5
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+# bit7: 0, TestMode=0 normal
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+# bit8: 0, DLL reset=0 normal
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+# bit11-9: 6, auto-precharge write recovery ????????????
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+# bit12: 0, PD must be zero
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+# bit31-13: 0 required
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+
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+DATA 0xFFD01420 0x00000004 # DDR Extended Mode
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+# bit0: 0, DDR DLL enabled
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+# bit1: 0, DDR drive strenght normal
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+# bit2: 0, DDR ODT control lsd (disabled)
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+# bit5-3: 000, required
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+# bit6: 1, DDR ODT control msb, (disabled)
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+# bit9-7: 000, required
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+# bit10: 0, differential DQS enabled
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+# bit11: 0, required
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+# bit12: 0, DDR output buffer enabled
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+# bit31-13: 0 required
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+
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+DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
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+# bit2-0: 111, required
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+# bit3 : 1 , MBUS Burst Chop disabled
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+# bit6-4: 111, required
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+# bit7 : 0
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+# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
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+# bit9 : 0 , no half clock cycle addition to dataout
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+# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
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+# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
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+# bit15-12: 1111 required
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+# bit31-16: 0 required
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+
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+DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
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+DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
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+
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+
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+DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
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+#DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
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+# bit0: 1, Window enabled
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+# bit1: 0, Write Protect disabled
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+# bit3-2: 00, CS0 hit selected
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+# bit23-4: ones, required
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+# bit31-24: 0x0F, Size (i.e. 256MB)
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+
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+DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
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+DATA 0xFFD0150C 0x00000000 # CS[2]n Size, window disabled KAZ z 400db
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+DATA 0xFFD01514 0x00000000 # CS[3]n Size, window disabled
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+
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+DATA 0xFFD0151C 0x00000000 # DDR ODT Control (Low)
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+DATA 0xFFD01494 0x00120012 # DDR ODT Control (High) KAZ z nowy STATIC_SDRAM_ODT_CTRL_LOW
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+# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
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+# bit3-2: 01, ODT1 active NEVER!
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+# bit31-4: zero, required
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+
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+DATA 0xFFD01498 0x00000000 # CPU ODT Control KAZ STATIC_SDRAM_ODT_CTRL_HI
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+DATA 0xFFD0149C 0x0000E403 # DDR Initialization Control KAZ STATIC_SDRAM_DUNIT_ODT_CTRL
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+DATA 0xFFD01480 0x00000001 # DDR Initialization Control
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+#bit0=1, enable DDR init upon this register write
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+
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+# End of Header extension
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+DATA 0x0 0x0
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--- /dev/null
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+++ b/board/zyxel/nsa310/nsa310.c
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@@ -0,0 +1,190 @@
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+/*
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+ * Copyright (C) 2013 Rafal Kazmierowski
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+ *
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+ * Based on NSA320.c Peter Schildmann <linux@schildmann.info>
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+ * originally written by
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+ * Marvell Semiconductor <www.marvell.com>
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+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
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+ *
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+ * See file CREDITS for list of people who contributed to this
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+ * project.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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+ * MA 02110-1301 USA
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+ */
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+
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+#include <common.h>
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+#include <miiphy.h>
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+#include <asm/arch/cpu.h>
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+#include <asm/arch/soc.h>
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+#include <asm/arch/mpp.h>
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+#include <asm/io.h>
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+#include "nsa310.h"
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+int board_early_init_f(void)
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+{
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+ /*
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+ * default gpio configuration
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+ * There are maximum 64 gpios controlled through 2 sets of registers
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+ * the below configuration configures mainly initial LED status
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+ */
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+ mvebu_config_gpio(NSA310_VAL_LOW, NSA310_VAL_HIGH,
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+ NSA310_OE_LOW, NSA310_OE_HIGH);
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+
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+ /* Multi-Purpose Pins Functionality configuration */
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+ /* (all LEDs & power off active high) */
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+ static const u32 kwmpp_config[] = {
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+ MPP0_NF_IO2,
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+ MPP1_NF_IO3,
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+ MPP2_NF_IO4,
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+ MPP3_NF_IO5,
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+ MPP4_NF_IO6,
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+ MPP5_NF_IO7,
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+ MPP6_SYSRST_OUTn,
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+ MPP7_GPO,
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+ MPP8_TW_SDA, /* PCF8563 RTC chip */
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+ MPP9_TW_SCK, /* connected to TWSI */
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+ MPP10_UART0_TXD,
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+ MPP11_UART0_RXD,
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+ MPP12_GPO, /* SATA2 LED (green) */
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+ MPP13_GPIO, /* SATA2 LED (red) */
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+ MPP14_GPIO, /* MCU DATA pin (in) */
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+ MPP15_GPIO, /* USB LED (green) */
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+ MPP16_GPIO, /* MCU CLK pin (out) */
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+ MPP17_GPIO, /* MCU ACT pin (out) */
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+ MPP18_NF_IO0,
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+ MPP19_NF_IO1,
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+ MPP20_GPIO,
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+ MPP21_GPIO, /* USB LED (red)-Power*/
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+ MPP22_GPIO,
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+ MPP23_GPIO,
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+ MPP24_GPIO,
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+ MPP25_GPIO,
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+ MPP26_GPIO,
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+ MPP27_GPIO,
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+ MPP28_GPIO, /* SYS LED (green) */
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+ MPP29_GPIO, /* SYS LED (red) */
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+ MPP30_GPIO,
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+ MPP31_GPIO,
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+ MPP32_GPIO,
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+ MPP33_GPIO,
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+ MPP34_GPIO,
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+ MPP35_GPIO,
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+ MPP36_GPIO, /* Reset button */
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+ MPP37_GPIO, /* Copy button */
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+ MPP38_GPIO, /* VID B0 */
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+ MPP39_GPIO, /* COPY LED (green) */
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+ MPP40_GPIO, /* COPY LED (red) */
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+ MPP41_GPIO, /* SATA1 LED (green) */
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+ MPP42_GPIO, /* SATA1 LED (red) */
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+ MPP43_GPIO, /* HTP pin */
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+ MPP44_GPIO, /* Buzzer */
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+ MPP45_GPIO, /* VID B1 */
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+ MPP46_GPIO, /* Power button */
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+ MPP47_GPIO, /* Power resume data */
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+ MPP48_GPIO, /* Power off */
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+ MPP49_GPIO, /* Power resume clock */
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+ 0
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+ };
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+ kirkwood_mpp_conf(kwmpp_config,NULL);
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+ return 0;
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+}
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+
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+int board_init(void)
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+{
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+ /* address of boot parameters */
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+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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+
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+ return 0;
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+}
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+
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+#ifdef CONFIG_RESET_PHY_R
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+/* Configure and enable MV88E1318 PHY */
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+void reset_phy(void)
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+{
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+ u16 reg;
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+ u16 devadr;
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+ char *name = "egiga0";
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+
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+ if (miiphy_set_current_dev(name))
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+ return;
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+
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+ /* command to read PHY dev address */
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+ if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
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+ printf("Err..%s could not read PHY dev address\n",
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+ __FUNCTION__);
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+ return;
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+ }
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+
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+ /* Set RGMII delay */
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+ miiphy_write(name, devadr, MV88E1318_PGADR_REG, 2);
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+ miiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, ®);
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+ reg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL);
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+ miiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg);
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+ miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);
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+
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+ /* reset the phy */
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+ miiphy_reset(name, devadr);
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+
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+ printf("MV88E1318 PHY initialized on %s\n", name);
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+}
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+#endif /* CONFIG_RESET_PHY_R */
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+
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+#ifdef CONFIG_SHOW_BOOT_PROGRESS
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+void show_boot_progress(int val)
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+{
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+ struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
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+ u32 dout0 = readl(&gpio0->dout);
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+ u32 blen0 = readl(&gpio0->blink_en);
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+
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+ struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
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+ u32 dout1 = readl(&gpio1->dout);
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+ u32 blen1 = readl(&gpio1->blink_en);
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+
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+ switch (val) {
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+ case BOOTSTAGE_ID_DECOMP_IMAGE:
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+ writel(blen0 & ~(SYS_GREEN_LED | SYS_RED_LED), &gpio0->blink_en);
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+ writel((dout0 & ~SYS_GREEN_LED) | SYS_RED_LED, &gpio0->dout);
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+ break;
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+ case BOOTSTAGE_ID_RUN_OS:
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+ writel(dout0 & ~SYS_RED_LED, &gpio0->dout);
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+ writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en);
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+ break;
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+ case BOOTSTAGE_ID_NET_START:
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+ writel(dout1 & ~COPY_RED_LED, &gpio1->dout);
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+ writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en);
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+ break;
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+ case BOOTSTAGE_ID_NET_LOADED:
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+ writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en);
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+ writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout);
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+ break;
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|
+ case -BOOTSTAGE_ID_NET_NETLOOP_OK:
|
|
+ case -BOOTSTAGE_ID_NET_LOADED:
|
|
+ writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout);
|
|
+ writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en);
|
|
+ break;
|
|
+ default:
|
|
+ if (val < 0) {
|
|
+ /* error */
|
|
+ printf("Error occured, error code = %d\n", -val);
|
|
+ writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout);
|
|
+ writel(blen0 | SYS_RED_LED, &gpio0->blink_en);
|
|
+ }
|
|
+ break;
|
|
+ }
|
|
+}
|
|
+#endif
|
|
--- /dev/null
|
|
+++ b/board/zyxel/nsa310/nsa310.h
|
|
@@ -0,0 +1,56 @@
|
|
+/*
|
|
+ * Copyright (C) 2013 Rafal Kazmierowski
|
|
+ *
|
|
+ * Based on Peter Schildmann <linux@schildmann.info>
|
|
+ * and guruplug.h originally written by
|
|
+ * Siddarth Gore <gores@marvell.com>
|
|
+ * (C) Copyright 2009
|
|
+ * Marvell Semiconductor <www.marvell.com>
|
|
+ *
|
|
+ * See file CREDITS for list of people who contributed to this
|
|
+ * project.
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or
|
|
+ * modify it under the terms of the GNU General Public License as
|
|
+ * published by the Free Software Foundation; either version 2 of
|
|
+ * the License, or (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program; if not, write to the Free Software
|
|
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
|
+ * MA 02110-1301 USA
|
|
+ */
|
|
+
|
|
+#ifndef __NSA310_H
|
|
+#define __NSA310_H
|
|
+
|
|
+/* GPIO's */
|
|
+#define SYS_GREEN_LED (1 << 28)
|
|
+#define SYS_RED_LED (1 << 29)
|
|
+#define SATA1_GREEN_LED (1ULL << 41)
|
|
+#define SATA1_RED_LED (1ULL << 42)
|
|
+#define SATA2_GREEN_LED (1 << 12)
|
|
+#define SATA2_RED_LED (1 << 13)
|
|
+#define USB_GREEN_LED (1 << 15)
|
|
+#define USB_RED_LED (1 << 21)
|
|
+#define COPY_GREEN_LED (1ULL << 39)
|
|
+#define COPY_RED_LED (1ULL << 40)
|
|
+
|
|
+#define NSA310_OE_LOW (0)
|
|
+#define NSA310_VAL_LOW (SYS_GREEN_LED)
|
|
+#define NSA310_OE_HIGH (((COPY_GREEN_LED | COPY_RED_LED | \
|
|
+ SATA1_GREEN_LED | SATA1_RED_LED)) >> 32UL)
|
|
+#define NSA310_VAL_HIGH (0)
|
|
+
|
|
+/* PHY related */
|
|
+#define MV88E1318_MAC_CTRL_REG 21
|
|
+#define MV88E1318_PGADR_REG 22
|
|
+#define MV88E1318_RGMII_TXTM_CTRL (1 << 4)
|
|
+#define MV88E1318_RGMII_RXTM_CTRL (1 << 5)
|
|
+
|
|
+#endif /* __NSA310_H */
|
|
--- /dev/null
|
|
+++ b/configs/nsa310_defconfig
|
|
@@ -0,0 +1,48 @@
|
|
+CONFIG_ARM=y
|
|
+CONFIG_SYS_DCACHE_OFF=y
|
|
+CONFIG_ARCH_CPU_INIT=y
|
|
+CONFIG_KIRKWOOD=y
|
|
+CONFIG_SYS_TEXT_BASE=0x600000
|
|
+CONFIG_TARGET_NSA310=y
|
|
+CONFIG_IDENT_STRING="\nZyXEL NSA310 1-Bay Power Media Server"
|
|
+CONFIG_NR_DRAM_BANKS=2
|
|
+CONFIG_BOOTDELAY=3
|
|
+CONFIG_SYS_PROMPT="NSA310> "
|
|
+# CONFIG_CMD_IMLS is not set
|
|
+# CONFIG_CMD_FLASH is not set
|
|
+CONFIG_MVGBE=y
|
|
+CONFIG_MII=y
|
|
+CONFIG_SYS_NS16550=y
|
|
+CONFIG_CMD_FDT=y
|
|
+CONFIG_OF_LIBFDT=y
|
|
+CONFIG_CMD_SETEXPR=y
|
|
+CONFIG_CMD_DHCP=y
|
|
+CONFIG_CMD_MII=y
|
|
+CONFIG_CMD_PING=y
|
|
+CONFIG_CMD_DNS=y
|
|
+CONFIG_CMD_SNTP=y
|
|
+CONFIG_CMD_USB=y
|
|
+CONFIG_CMD_DATE=y
|
|
+CONFIG_CMD_EXT2=y
|
|
+CONFIG_CMD_EXT4=y
|
|
+CONFIG_CMD_FAT=y
|
|
+CONFIG_CMD_JFFS2=y
|
|
+CONFIG_MTD=y
|
|
+CONFIG_MTD_RAW_NAND=y
|
|
+CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x0c0000(uboot),0x80000(uboot_env),0x7ec0000(ubi)"
|
|
+CONFIG_CMD_MTDPARTS=y
|
|
+CONFIG_CMD_ENV=y
|
|
+CONFIG_CMD_NAND=y
|
|
+CONFIG_EFI_PARTITION=y
|
|
+CONFIG_ENV_IS_IN_NAND=y
|
|
+CONFIG_ENV_SIZE=0x20000
|
|
+CONFIG_ENV_OFFSET=0xC0000
|
|
+CONFIG_ENV_SECT_SIZE=0x20000
|
|
+CONFIG_ENV_ADDR=0xC0000
|
|
+CONFIG_CMD_UBI=y
|
|
+CONFIG_USB=y
|
|
+CONFIG_USB_EHCI_HCD=y
|
|
+CONFIG_USB_STORAGE=y
|
|
+CONFIG_LZMA=y
|
|
+CONFIG_LZO=y
|
|
+CONFIG_SYS_LONGHELP=y
|
|
--- /dev/null
|
|
+++ b/include/configs/nsa310.h
|
|
@@ -0,0 +1,103 @@
|
|
+/* Copyright (C) 2015-2016 bodhi <mibodhi@gmail.com>
|
|
+ *
|
|
+ * Based on
|
|
+ * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info>
|
|
+ *
|
|
+ * Based on guruplug.h originally written by
|
|
+ * Siddarth Gore <gores@marvell.com>
|
|
+ * (C) Copyright 2009
|
|
+ * Marvell Semiconductor <www.marvell.com>
|
|
+ *
|
|
+ * See file CREDITS for list of people who contributed to this
|
|
+ * project.
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or
|
|
+ * modify it under the terms of the GNU General Public License as
|
|
+ * published by the Free Software Foundation; either version 2 of
|
|
+ * the License, or (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program; if not, write to the Free Software
|
|
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
|
+ * MA 02110-1301 USA
|
|
+ */
|
|
+
|
|
+#ifndef _CONFIG_NSA310_H
|
|
+#define _CONFIG_NSA310_H
|
|
+
|
|
+/*
|
|
+ * High Level Configuration Options (easy to change)
|
|
+ */
|
|
+#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
|
|
+#define CONFIG_KW88F6281 /* SOC Name */
|
|
+
|
|
+#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
|
|
+
|
|
+/*
|
|
+ * Misc Configuration Options
|
|
+ */
|
|
+#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progess display (LED's) */
|
|
+
|
|
+/*
|
|
+ * Commands configuration
|
|
+ */
|
|
+#define CONFIG_PREBOOT
|
|
+
|
|
+/*
|
|
+ * mv-common.h should be defined after CMD configs since it used them
|
|
+ * to enable certain macros
|
|
+ */
|
|
+#include "mv-common.h"
|
|
+
|
|
+/*
|
|
+ * Default environment variables
|
|
+ */
|
|
+#define CONFIG_BOOTCOMMAND \
|
|
+ "ubi part ubi; " \
|
|
+ "ubi read 0x800000 kernel; " \
|
|
+ "bootm 0x800000"
|
|
+
|
|
+#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
+ "console=console=ttyS0,115200\0" \
|
|
+ "mtdids=nand0=orion_nand\0" \
|
|
+ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
|
|
+ "bootargs_root=\0"
|
|
+
|
|
+/*
|
|
+ * Ethernet Driver configuration
|
|
+ */
|
|
+#ifdef CONFIG_CMD_NET
|
|
+#define CONFIG_NETCONSOLE
|
|
+#define CONFIG_NET_MULTI
|
|
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
|
|
+#define CONFIG_PHY_BASE_ADR 0x1
|
|
+#define CONFIG_RESET_PHY_R
|
|
+#endif /* CONFIG_CMD_NET */
|
|
+
|
|
+/*
|
|
+ * SATA Driver configuration
|
|
+ */
|
|
+#ifdef CONFIG_MVSATA_IDE
|
|
+#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
|
|
+#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
|
|
+#endif /* CONFIG_MVSATA_IDE */
|
|
+
|
|
+/*
|
|
+ * File system
|
|
+ */
|
|
+#define CONFIG_JFFS2_NAND
|
|
+#define CONFIG_JFFS2_LZO
|
|
+
|
|
+/*
|
|
+ * Date Time
|
|
+ */
|
|
+#ifdef CONFIG_CMD_DATE
|
|
+#define CONFIG_RTC_MV
|
|
+#endif /* CONFIG_CMD_DATE */
|
|
+
|
|
+#endif /* _CONFIG_NSA310_H */
|