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@ -98,8 +98,6 @@ struct reg_range reg_range[] = {
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{ 0x1b00, 0x900, "3D Unit", 0 }, */
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};
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static struct glamo_core *glamo_handle;
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static inline void __reg_write(struct glamo_core *glamo,
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u_int16_t reg, u_int16_t val)
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{
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@ -220,32 +218,36 @@ static struct mfd_cell glamo_cells[] = {
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static void glamo_ack_irq(unsigned int irq)
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{
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struct glamo_core *glamo = (struct glamo_core*)get_irq_chip_data(irq);
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/* clear interrupt source */
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__reg_write(glamo_handle, GLAMO_REG_IRQ_CLEAR,
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__reg_write(glamo, GLAMO_REG_IRQ_CLEAR,
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1 << irq2glamo(irq));
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}
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static void glamo_mask_irq(unsigned int irq)
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{
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struct glamo_core *glamo = (struct glamo_core*)get_irq_chip_data(irq);
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u_int16_t tmp;
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/* clear bit in enable register */
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tmp = __reg_read(glamo_handle, GLAMO_REG_IRQ_ENABLE);
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tmp = __reg_read(glamo, GLAMO_REG_IRQ_ENABLE);
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tmp &= ~(1 << irq2glamo(irq));
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__reg_write(glamo_handle, GLAMO_REG_IRQ_ENABLE, tmp);
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__reg_write(glamo, GLAMO_REG_IRQ_ENABLE, tmp);
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}
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static void glamo_unmask_irq(unsigned int irq)
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{
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struct glamo_core *glamo = (struct glamo_core*)get_irq_chip_data(irq);
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u_int16_t tmp;
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/* set bit in enable register */
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tmp = __reg_read(glamo_handle, GLAMO_REG_IRQ_ENABLE);
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tmp = __reg_read(glamo, GLAMO_REG_IRQ_ENABLE);
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tmp |= (1 << irq2glamo(irq));
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__reg_write(glamo_handle, GLAMO_REG_IRQ_ENABLE, tmp);
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__reg_write(glamo, GLAMO_REG_IRQ_ENABLE, tmp);
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}
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static struct irq_chip glamo_irq_chip = {
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.name = "glamo",
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.ack = glamo_ack_irq,
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.mask = glamo_mask_irq,
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.unmask = glamo_unmask_irq,
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@ -253,6 +255,7 @@ static struct irq_chip glamo_irq_chip = {
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static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct glamo_core *glamo = get_irq_desc_chip_data(desc);
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desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
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if (unlikely(desc->status & IRQ_INPROGRESS)) {
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@ -281,7 +284,7 @@ static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
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desc->status &= ~IRQ_PENDING;
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/* read IRQ status register */
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irqstatus = __reg_read(glamo_handle, GLAMO_REG_IRQ_STATUS);
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irqstatus = __reg_read(glamo, GLAMO_REG_IRQ_STATUS);
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for (i = 0; i < 9; i++)
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if (irqstatus & (1 << i))
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desc_handle_irq(IRQ_GLAMO(i),
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@ -596,14 +599,14 @@ void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine)
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}
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EXPORT_SYMBOL_GPL(glamo_engine_reset);
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void glamo_lcm_reset(int level)
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void glamo_lcm_reset(struct platform_device *pdev, int level)
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{
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if (!glamo_handle)
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struct glamo_core *glamo = dev_get_drvdata(&pdev->dev);
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if (!glamo)
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return;
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glamo_gpio_setpin(glamo_handle, GLAMO_GPIO4, level);
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glamo_gpio_cfgpin(glamo_handle, GLAMO_GPIO4_OUTPUT);
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glamo_gpio_setpin(glamo, GLAMO_GPIO4, level);
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glamo_gpio_cfgpin(glamo, GLAMO_GPIO4_OUTPUT);
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}
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EXPORT_SYMBOL_GPL(glamo_lcm_reset);
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@ -1107,18 +1110,11 @@ static int __init glamo_probe(struct platform_device *pdev)
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int rc = 0, irq;
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struct glamo_core *glamo;
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if (glamo_handle) {
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dev_err(&pdev->dev,
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"This driver supports only one instance\n");
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return -EBUSY;
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}
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glamo = kmalloc(GFP_KERNEL, sizeof(*glamo));
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if (!glamo)
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return -ENOMEM;
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spin_lock_init(&glamo->lock);
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glamo_handle = glamo;
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glamo->pdev = pdev;
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glamo->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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glamo->irq = platform_get_irq(pdev, 0);
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@ -1152,15 +1148,16 @@ static int __init glamo_probe(struct platform_device *pdev)
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*/
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for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
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set_irq_chip(irq, &glamo_irq_chip);
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set_irq_handler(irq, handle_level_irq);
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set_irq_chip_and_handler(irq, &glamo_irq_chip, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID);
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set_irq_chip_data(irq, glamo);
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}
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if (glamo->pdata->glamo_irq_is_wired &&
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!glamo->pdata->glamo_irq_is_wired()) {
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set_irq_chained_handler(glamo->irq, glamo_irq_demux_handler);
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set_irq_type(glamo->irq, IRQ_TYPE_EDGE_FALLING);
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set_irq_chip_data(glamo->irq, glamo);
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dev_info(&pdev->dev, "Glamo interrupt registered\n");
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glamo->irq_works = 1;
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} else {
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@ -1231,16 +1228,17 @@ static int __init glamo_probe(struct platform_device *pdev)
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bail_irq:
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disable_irq(glamo->irq);
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set_irq_chained_handler(glamo->irq, NULL);
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set_irq_chip_data(glamo->irq, NULL);
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for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
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set_irq_flags(irq, 0);
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set_irq_chip(irq, NULL);
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set_irq_chip_data(irq, NULL);
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}
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iounmap(glamo->base);
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bail_free:
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platform_set_drvdata(pdev, NULL);
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glamo_handle = NULL;
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kfree(glamo);
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return rc;
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@ -1253,17 +1251,18 @@ static int glamo_remove(struct platform_device *pdev)
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disable_irq(glamo->irq);
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set_irq_chained_handler(glamo->irq, NULL);
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set_irq_chip_data(glamo->irq, NULL);
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for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
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set_irq_flags(irq, 0);
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set_irq_chip(irq, NULL);
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set_irq_chip_data(irq, NULL);
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}
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platform_set_drvdata(pdev, NULL);
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mfd_remove_devices(&pdev->dev);
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iounmap(glamo->base);
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release_mem_region(glamo->mem->start, GLAMO_REGOFS_VIDCAP);
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glamo_handle = NULL;
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kfree(glamo);
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return 0;
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@ -1273,16 +1272,18 @@ static int glamo_remove(struct platform_device *pdev)
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static int glamo_suspend(struct platform_device *pdev, pm_message_t state)
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{
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glamo_handle->suspending = 1;
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glamo_power(glamo_handle, GLAMO_POWER_SUSPEND);
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struct glamo_core *glamo = dev_get_drvdata(&pdev->dev);
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glamo->suspending = 1;
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glamo_power(glamo, GLAMO_POWER_SUSPEND);
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return 0;
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}
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static int glamo_resume(struct platform_device *pdev)
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{
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glamo_power(glamo_handle, GLAMO_POWER_ON);
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glamo_handle->suspending = 0;
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struct glamo_core *glamo = dev_get_drvdata(&pdev->dev);
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glamo_power(glamo, GLAMO_POWER_ON);
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glamo->suspending = 0;
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return 0;
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}
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