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@ -794,8 +794,8 @@
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#define SPI_BCM_6358_SPI_MSG_DATA 0x02
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#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
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#define SPI_BCM_6358_SPI_RX_FIFO 0x400
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#define SPI_BCM_6358_SPI_RX_FIFO_SIZE 0x220
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#define SPI_BCM_6358_SPI_RX_DATA 0x400
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#define SPI_BCM_6358_SPI_RX_DATA_SIZE 0x220
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#define SPI_BCM_6358_SPI_CMD 0x700 /* 16-bits register */
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@ -815,17 +815,17 @@
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/* Shared SPI definitions */
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/* Message configuration */
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#define SPI_FD_RW 0
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#define SPI_HD_W 1
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#define SPI_HD_R 2
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#define SPI_FD_RW 0x00
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#define SPI_HD_W 0x01
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#define SPI_HD_R 0x02
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#define SPI_BYTE_CNT_SHIFT 0
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#define SPI_MSG_TYPE_SHIFT 14
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/* Command */
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#define SPI_CMD_NOOP 0
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#define SPI_CMD_SOFT_RESET 1
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#define SPI_CMD_HARD_RESET 2
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#define SPI_CMD_START_IMMEDIATE 3
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#define SPI_CMD_NOOP 0x01
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#define SPI_CMD_SOFT_RESET 0x02
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#define SPI_CMD_HARD_RESET 0x04
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#define SPI_CMD_START_IMMEDIATE 0x08
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#define SPI_CMD_COMMAND_SHIFT 0
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#define SPI_CMD_COMMAND_MASK 0x000f
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#define SPI_CMD_DEVICE_ID_SHIFT 4
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@ -851,12 +851,14 @@
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#define SPI_SERIAL_BUSY 0x08
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/* Clock configuration */
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#define SPI_CLK_0_391MHZ 1
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#define SPI_CLK_0_781MHZ 2 /* default */
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#define SPI_CLK_1_563MHZ 3
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#define SPI_CLK_3_125MHZ 4
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#define SPI_CLK_6_250MHZ 5
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#define SPI_CLK_12_50MHZ 6
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#define SPI_CLK_20MHZ 0x00
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#define SPI_CLK_0_391MHZ 0x01
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#define SPI_CLK_0_781MHZ 0x02 /* default */
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#define SPI_CLK_1_563MHZ 0x03
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#define SPI_CLK_3_125MHZ 0x04
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#define SPI_CLK_6_250MHZ 0x05
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#define SPI_CLK_12_50MHZ 0x06
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#define SPI_CLK_25MHZ 0x07
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#define SPI_CLK_MASK 0x07
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#define SPI_SSOFFTIME_MASK 0x38
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#define SPI_SSOFFTIME_SHIFT 3
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