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ipq806x: use new usb3 implementation

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Use new usb3 implementation and refresh dts to the new dwc3 structure

Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
[proper authorship of the patch]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
master
Christian Lamparter 5 years ago committed by Petr Štetiar
parent 96a509eeeb
commit afcb78f103
16 changed files with 64 additions and 290 deletions
Show Stats Download Patch File Download Diff File

20
target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@ -137,27 +137,11 @@
status = "okay"; status = "okay";
}; };
phy@100f8800 { /* USB3 port 1 HS phy */ usb3_0: usb3@110f8800 {
status = "okay"; status = "okay";
}; };
phy@100f8830 { /* USB3 port 1 SS phy */ usb3_1: usb3@100f8800 {
status = "okay";
};
phy@110f8800 { /* USB3 port 0 HS phy */
status = "okay";
};
phy@110f8830 { /* USB3 port 0 SS phy */
status = "okay";
};
usb30@0 {
status = "okay";
};
usb30@1 {
status = "okay"; status = "okay";
}; };

20
target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-ap161.dts
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@ -140,27 +140,11 @@
status = "okay"; status = "okay";
}; };
phy@100f8800 { /* USB3 port 1 HS phy */ usb3_0: usb3@110f8800 {
status = "okay"; status = "okay";
}; };
phy@100f8830 { /* USB3 port 1 SS phy */ usb3_1: usb3@100f8800 {
status = "okay";
};
phy@110f8800 { /* USB3 port 0 HS phy */
status = "okay";
};
phy@110f8830 { /* USB3 port 0 SS phy */
status = "okay";
};
usb30@0 {
status = "okay";
};
usb30@1 {
status = "okay"; status = "okay";
}; };

20
target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-c2600.dts
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@ -315,30 +315,14 @@
}; };
}; };
phy@100f8800 { /* USB3 port 1 HS phy */ usb3_0: usb3@110f8800 {
status = "okay";
};
phy@100f8830 { /* USB3 port 1 SS phy */
status = "okay";
};
phy@110f8800 { /* USB3 port 0 HS phy */
status = "okay";
};
phy@110f8830 { /* USB3 port 0 SS phy */
status = "okay";
};
usb30@0 {
status = "okay"; status = "okay";
pinctrl-0 = <&usb0_pwr_en_pin>; pinctrl-0 = <&usb0_pwr_en_pin>;
pinctrl-names = "default"; pinctrl-names = "default";
}; };
usb30@1 { usb3_1: usb3@100f8800 {
status = "okay"; status = "okay";
pinctrl-0 = <&usb1_pwr_en_pin>; pinctrl-0 = <&usb1_pwr_en_pin>;

20
target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-d7800.dts
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@ -152,30 +152,14 @@
status = "okay"; status = "okay";
}; };
phy@100f8800 { /* USB3 port 1 HS phy */ usb3_0: usb3@110f8800 {
status = "okay";
};
phy@100f8830 { /* USB3 port 1 SS phy */
status = "okay";
};
phy@110f8800 { /* USB3 port 0 HS phy */
status = "okay";
};
phy@110f8830 { /* USB3 port 0 SS phy */
status = "okay";
};
usb30@0 {
status = "okay"; status = "okay";
pinctrl-0 = <&usb0_pwr_en_pins>; pinctrl-0 = <&usb0_pwr_en_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
}; };
usb30@1 { usb3_1: usb3@100f8800 {
status = "okay"; status = "okay";
pinctrl-0 = <&usb1_pwr_en_pins>; pinctrl-0 = <&usb1_pwr_en_pins>;

20
target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-db149.dts
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@ -123,27 +123,11 @@
status = "okay"; status = "okay";
}; };
phy@100f8800 { /* USB3 port 1 HS phy */ usb3_0: usb3@110f8800 {
status = "okay"; status = "okay";
}; };
phy@100f8830 { /* USB3 port 1 SS phy */ usb3_1: usb3@100f8800 {
status = "okay";
};
phy@110f8800 { /* USB3 port 0 HS phy */
status = "okay";
};
phy@110f8830 { /* USB3 port 0 SS phy */
status = "okay";
};
usb30@0 {
status = "okay";
};
usb30@1 {
status = "okay"; status = "okay";
}; };

20
target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts
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@ -131,27 +131,11 @@
status = "okay"; status = "okay";
}; };
phy@100f8800 { /* USB3 port 1 HS phy */ usb3_0: usb3@110f8800 {
status = "okay"; status = "okay";
}; };
phy@100f8830 { /* USB3 port 1 SS phy */ usb3_1: usb3@100f8800 {
status = "okay";
};
phy@110f8800 { /* USB3 port 0 HS phy */
status = "okay";
};
phy@110f8830 { /* USB3 port 0 SS phy */
status = "okay";
};
usb30@0 {
status = "okay";
};
usb30@1 {
status = "okay"; status = "okay";
}; };

24
target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-r7500.dts
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@ -132,32 +132,12 @@
status = "okay"; status = "okay";
}; };
phy@100f8800 { /* USB3 port 1 HS phy */ usb3_0: usb3@110f8800 {
clocks = <&gcc USB30_0_UTMI_CLK>;
status = "okay";
};
phy@100f8830 { /* USB3 port 1 SS phy */
clocks = <&gcc USB30_0_MASTER_CLK>;
status = "okay";
};
phy@110f8800 { /* USB3 port 0 HS phy */
clocks = <&gcc USB30_1_UTMI_CLK>;
status = "okay";
};
phy@110f8830 { /* USB3 port 0 SS phy */
clocks = <&gcc USB30_1_MASTER_CLK>;
status = "okay";
};
usb30@0 {
clocks = <&gcc USB30_1_MASTER_CLK>; clocks = <&gcc USB30_1_MASTER_CLK>;
status = "okay"; status = "okay";
}; };
usb30@1 { usb3_1: usb3@100f8800 {
clocks = <&gcc USB30_0_MASTER_CLK>; clocks = <&gcc USB30_0_MASTER_CLK>;
status = "okay"; status = "okay";
}; };

20
target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts
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@ -156,30 +156,14 @@
status = "okay"; status = "okay";
}; };
phy@100f8800 { /* USB3 port 1 HS phy */ usb3_0: usb3@110f8800 {
status = "okay";
};
phy@100f8830 { /* USB3 port 1 SS phy */
status = "okay";
};
phy@110f8800 { /* USB3 port 0 HS phy */
status = "okay";
};
phy@110f8830 { /* USB3 port 0 SS phy */
status = "okay";
};
usb30@0 {
status = "okay"; status = "okay";
pinctrl-0 = <&usb0_pwr_en_pins>; pinctrl-0 = <&usb0_pwr_en_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
}; };
usb30@1 { usb3_1: usb3@100f8800 {
status = "okay"; status = "okay";
pinctrl-0 = <&usb1_pwr_en_pins>; pinctrl-0 = <&usb1_pwr_en_pins>;

24
target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
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@ -3,18 +3,6 @@
/ { / {
soc: soc { soc: soc {
ss_phy_0: phy@110f8830 {
rx_eq = <2>;
tx_deamp_3_5db = <32>;
mpll = <0xa0>;
};
ss_phy_1: phy@100f8830 {
rx_eq = <2>;
tx_deamp_3_5db = <32>;
mpll = <0xa0>;
};
pcie0: pci@1b500000 { pcie0: pci@1b500000 {
phy-tx0-term-offset = <0>; phy-tx0-term-offset = <0>;
}; };
@ -28,3 +16,15 @@
}; };
}; };
}; };
&ss_phy_0 {
rx_eq = <2>;
tx_deamp_3_5db = <32>;
mpll = <0xa0>;
};
&ss_phy_1 {
rx_eq = <2>;
tx_deamp_3_5db = <32>;
mpll = <0xa0>;
};

20
target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts
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@ -233,27 +233,11 @@
}; };
}; };
phy@100f8800 { /* USB3 port 1 HS phy */ usb3_0: usb3@110f8800 {
status = "okay"; status = "okay";
}; };
phy@100f8830 { /* USB3 port 1 SS phy */ usb3_1: usb3@100f8800 {
status = "okay";
};
phy@110f8800 { /* USB3 port 0 HS phy */
status = "okay";
};
phy@110f8830 { /* USB3 port 0 SS phy */
status = "okay";
};
usb30@0 {
status = "okay";
};
usb30@1 {
status = "okay"; status = "okay";
}; };

16
target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts
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@ -321,22 +321,6 @@
}; };
}; };
&hs_phy_0 { /* USB3 port 0 HS phy */
status = "okay";
};
&ss_phy_0 { /* USB3 port 0 SS phy */
status = "okay";
};
&hs_phy_1 { /* USB3 port 1 HS phy */
status = "okay";
};
&ss_phy_1 { /* USB3 port 1 SS phy */
status = "okay";
};
&usb3_0 { &usb3_0 {
status = "okay"; status = "okay";

8
target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts
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@ -383,14 +383,6 @@
}; };
}; };
&hs_phy_0 { /* USB3 port 0 HS phy */
status = "okay";
};
&hs_phy_1 { /* USB3 port 1 HS phy */
status = "okay";
};
&ss_phy_0 { /* USB3 port 0 SS phy */ &ss_phy_0 { /* USB3 port 0 SS phy */
status = "okay"; status = "okay";

16
target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts
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@ -369,22 +369,6 @@
}; };
}; };
&hs_phy_0 { /* USB3 port 0 HS phy */
status = "okay";
};
&ss_phy_0 { /* USB3 port 0 SS phy */
status = "okay";
};
&hs_phy_1 { /* USB3 port 1 HS phy */
status = "okay";
};
&ss_phy_1 { /* USB3 port 1 SS phy */
status = "okay";
};
&usb3_0 { &usb3_0 {
status = "okay"; status = "okay";

66
target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@ -920,64 +920,41 @@
reg = <0x01200600 0x100>; reg = <0x01200600 0x100>;
}; };
hs_phy_1: phy@100f8800 { hs_phy_0: hs_phy_0 {
compatible = "qcom,dwc3-hs-usb-phy"; compatible = "qcom,dwc3-hs-usb-phy";
reg = <0x100f8800 0x30>; regmap = <&usb3_0>;
clocks = <&gcc USB30_1_UTMI_CLK>;
clock-names = "ref";
#phy-cells = <0>;
status = "disabled";
};
ss_phy_1: phy@100f8830 {
compatible = "qcom,dwc3-ss-usb-phy";
reg = <0x100f8830 0x30>;
clocks = <&gcc USB30_1_MASTER_CLK>;
clock-names = "ref";
#phy-cells = <0>;
status = "disabled";
};
hs_phy_0: phy@110f8800 {
compatible = "qcom,dwc3-hs-usb-phy";
reg = <0x110f8800 0x30>;
clocks = <&gcc USB30_0_UTMI_CLK>; clocks = <&gcc USB30_0_UTMI_CLK>;
clock-names = "ref"; clock-names = "ref";
#phy-cells = <0>; #phy-cells = <0>;
status = "disabled";
}; };
ss_phy_0: phy@110f8830 { ss_phy_0: ss_phy_0 {
compatible = "qcom,dwc3-ss-usb-phy"; compatible = "qcom,dwc3-ss-usb-phy";
reg = <0x110f8830 0x30>; regmap = <&usb3_0>;
clocks = <&gcc USB30_0_MASTER_CLK>; clocks = <&gcc USB30_0_MASTER_CLK>;
clock-names = "ref"; clock-names = "ref";
#phy-cells = <0>; #phy-cells = <0>;
status = "disabled";
}; };
usb3_0: usb30@0 { usb3_0: usb3@110f8800 {
compatible = "qcom,dwc3"; compatible = "qcom,dwc3", "syscon";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
reg = <0x110f8800 0x8000>;
clocks = <&gcc USB30_0_MASTER_CLK>; clocks = <&gcc USB30_0_MASTER_CLK>;
clock-names = "core"; clock-names = "core";
ranges; ranges;
resets = <&gcc USB30_0_MASTER_RESET>; resets = <&gcc USB30_0_MASTER_RESET>;
reset-names = "usb30_0_mstr_rst"; reset-names = "master";
status = "disabled"; status = "disabled";
dwc3_0: dwc3@11000000 { dwc3_0: dwc3@11000000 {
compatible = "snps,dwc3"; compatible = "snps,dwc3";
reg = <0x11000000 0xcd00>; reg = <0x11000000 0xcd00>;
interrupts = <0 110 0x4>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hs_phy_0>, <&ss_phy_0>; phys = <&hs_phy_0>, <&ss_phy_0>;
phy-names = "usb2-phy", "usb3-phy"; phy-names = "usb2-phy", "usb3-phy";
dr_mode = "host"; dr_mode = "host";
@ -985,24 +962,41 @@
}; };
}; };
usb3_1: usb30@1 { hs_phy_1: hs_phy_1 {
compatible = "qcom,dwc3"; compatible = "qcom,dwc3-hs-usb-phy";
regmap = <&usb3_1>;
clocks = <&gcc USB30_1_UTMI_CLK>;
clock-names = "ref";
#phy-cells = <0>;
};
ss_phy_1: ss_phy_1 {
compatible = "qcom,dwc3-ss-usb-phy";
regmap = <&usb3_1>;
clocks = <&gcc USB30_1_MASTER_CLK>;
clock-names = "ref";
#phy-cells = <0>;
};
usb3_1: usb3@100f8800 {
compatible = "qcom,dwc3", "syscon";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
reg = <0x100f8800 0x8000>;
clocks = <&gcc USB30_1_MASTER_CLK>; clocks = <&gcc USB30_1_MASTER_CLK>;
clock-names = "core"; clock-names = "core";
ranges; ranges;
resets = <&gcc USB30_1_MASTER_RESET>; resets = <&gcc USB30_1_MASTER_RESET>;
reset-names = "usb30_1_mstr_rst"; reset-names = "master";
status = "disabled"; status = "disabled";
dwc3_1: dwc3@10000000 { dwc3_1: dwc3@10000000 {
compatible = "snps,dwc3"; compatible = "snps,dwc3";
reg = <0x10000000 0xcd00>; reg = <0x10000000 0xcd00>;
interrupts = <0 205 0x4>; interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hs_phy_1>, <&ss_phy_1>; phys = <&hs_phy_1>, <&ss_phy_1>;
phy-names = "usb2-phy", "usb3-phy"; phy-names = "usb2-phy", "usb3-phy";
dr_mode = "host"; dr_mode = "host";

20
target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts
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@ -189,30 +189,14 @@
}; };
}; };
phy@100f8800 { /* USB3 port 1 HS phy */ usb3_0: usb3@110f8800 {
status = "okay";
};
phy@100f8830 { /* USB3 port 1 SS phy */
status = "okay";
};
phy@110f8800 { /* USB3 port 0 HS phy */
status = "okay";
};
phy@110f8830 { /* USB3 port 0 SS phy */
status = "okay";
};
usb30@0 {
status = "okay"; status = "okay";
pinctrl-0 = <&usb0_pwr_en_pins>; pinctrl-0 = <&usb0_pwr_en_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
}; };
usb30@1 { usb3_1: usb3@100f8800 {
status = "okay"; status = "okay";
pinctrl-0 = <&usb1_pwr_en_pins>; pinctrl-0 = <&usb1_pwr_en_pins>;

20
target/linux/ipq806x/files-4.19/arch/arm/boot/dts/qcom-ipq8065-r7800.dts
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@ -225,30 +225,14 @@
status = "okay"; status = "okay";
}; };
phy@100f8800 { /* USB3 port 1 HS phy */ usb3_0: usb3@110f8800 {
status = "okay";
};
phy@100f8830 { /* USB3 port 1 SS phy */
status = "okay";
};
phy@110f8800 { /* USB3 port 0 HS phy */
status = "okay";
};
phy@110f8830 { /* USB3 port 0 SS phy */
status = "okay";
};
usb30@0 {
status = "okay"; status = "okay";
pinctrl-0 = <&usb0_pwr_en_pins>; pinctrl-0 = <&usb0_pwr_en_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
}; };
usb30@1 { usb3_1: usb3@100f8800 {
status = "okay"; status = "okay";
pinctrl-0 = <&usb1_pwr_en_pins>; pinctrl-0 = <&usb1_pwr_en_pins>;

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