ramips: add support for Ubiquiti EdgeRouter X-SFP
This patch adds support for the Ubiquiti EdgeRouter X-SFP and improves support for the EdgeRouter X (PoE-passthrough). Specification: - SoC: MediaTek MT7621AT - Flash: 256 MiB - RAM: 265 MiB - Ethernet: 5 x LAN (1000 Mbps) - UART: 1 x UART on PCB (3.3V, RX, TX, GND) - 57600 8N1 - EdgeRouter X: - 1 x PoE-Passtrough (Eth4) - powered by Wallwart or passive PoE - EdgeRouter X-SFP: - 5 x PoE-Out (24V, passive) - 1 x SFP (unknown status) - powered by Wallwart (24V) Doesn't work: * SoC has crypto engine but no open driver. * SoC has nat acceleration, but no open driver. * This router has 2MB spi flash soldered in but MT nand/spi drivers do not support pin sharing, so it is not accessable and disabled. Stock firmware could read it and it was empty. Installation via vendor firmware: - build an Initrd-image (> 3MiB) and upload the factory-image - initrd can have luci-mod-failsafe - flash final firmware via LuCI / sysupgrade on rebooted system via TFTP: - stop uboot into tftp-load into option "1" - upload factory.bin image Signed-off-by: Sven Roederer <devel-sven@geroedel.de>v19.07.3_mercusys_ac12_duma
Sven Roederer
7 years ago
committed by
John Crispin
parent
e178d51a04
commit
9715beb04c
@ -0,0 +1,25 @@
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#!/bin/sh
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. /lib/functions/uci-defaults.sh
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. /lib/ramips.sh
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board_config_update
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board=$(ramips_board_name)
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case "$board" in
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ubnt-erx)
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ucidef_add_gpio_switch "poe_passthrough" "PoE Passthrough" "0"
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;;
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ubnt-erx-sfp)
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ucidef_add_gpio_switch "poe_power_port0" "PoE Power Port0" "496"
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ucidef_add_gpio_switch "poe_power_port1" "PoE Power Port1" "497"
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ucidef_add_gpio_switch "poe_power_port2" "PoE Power Port2" "498"
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ucidef_add_gpio_switch "poe_power_port3" "PoE Power Port3" "499"
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ucidef_add_gpio_switch "poe_power_port4" "PoE Power Port4" "500"
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;;
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esac
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board_config_flush
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exit 0
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@ -0,0 +1,106 @@
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#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "ubiquiti,edgerouterx";
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x10000000>;
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};
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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gpio-keys-polled {
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compatible = "gpio-keys-polled";
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#address-cells = <1>;
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#size-cells = <0>;
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poll-interval = <20>;
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reset {
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label = "reset";
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gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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ðernet {
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mtd-mac-address = <&factory 0x22>;
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};
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&nand {
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status = "okay";
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x80000>;
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read-only;
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};
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partition@80000 {
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label = "u-boot-env";
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reg = <0x80000 0x60000>;
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read-only;
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};
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factory: partition@e0000 {
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label = "factory";
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reg = <0xe0000 0x60000>;
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};
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partition@140000 {
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label = "kernel1";
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reg = <0x140000 0x300000>;
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};
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partition@440000 {
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label = "kernel2";
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reg = <0x440000 0x300000>;
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};
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partition@740000 {
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label = "ubi";
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reg = <0x740000 0xf7c0000>;
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};
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};
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&pinctrl {
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state_default: pinctrl0 {
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gpio {
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ralink,group = "uart2", "uart3", "i2c", "pcie", "rgmii2", "jtag";
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ralink,function = "gpio";
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};
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};
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};
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&spi0 {
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/* This board has 2Mb spi flash soldered in and visible
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from manufacturer's firmware.
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But this SoC shares spi and nand pins,
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and current driver does't handle this sharing well */
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status = "disabled";
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m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <1>;
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spi-max-frequency = <10000000>;
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m25p,chunked-io = <32>;
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partition@0 {
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label = "spi";
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reg = <0x0 0x200000>;
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read-only;
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};
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};
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};
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&xhci {
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status = "disabled";
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};
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@ -0,0 +1,24 @@
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/dts-v1/;
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#include "UBNT-ER-e50.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "UBNT-ERX-SFP";
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compatible = "ubiquiti,edgerouterx-sfp";
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i2c-gpio {
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compatible = "i2c-gpio";
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gpios = <&gpio0 3 GPIO_ACTIVE_HIGH /* sda */
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&gpio0 4 GPIO_ACTIVE_HIGH /* scl */
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>;
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#address-cells = <1>;
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#size-cells = <0>;
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pca9555@25 {
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compatible = "pca9555";
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reg = <0x25>;
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};
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};
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};
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@ -1,108 +1,7 @@
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/dts-v1/;
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#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include "UBNT-ER-e50.dtsi"
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/ {
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model = "UBNT-ERX";
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x10000000>;
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};
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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gpio-keys-polled {
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compatible = "gpio-keys-polled";
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#address-cells = <1>;
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#size-cells = <0>;
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poll-interval = <20>;
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reset {
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label = "reset";
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gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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ðernet {
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mtd-mac-address = <&factory 0x22>;
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};
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&nand {
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status = "okay";
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x80000>;
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read-only;
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};
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partition@80000 {
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label = "u-boot-env";
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reg = <0x80000 0x60000>;
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read-only;
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};
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factory: partition@e0000 {
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label = "factory";
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reg = <0xe0000 0x60000>;
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};
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partition@140000 {
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label = "kernel1";
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reg = <0x140000 0x300000>;
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};
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partition@440000 {
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label = "kernel2";
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reg = <0x440000 0x300000>;
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};
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partition@740000 {
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label = "ubi";
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reg = <0x740000 0xf7c0000>;
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};
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};
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&pinctrl {
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state_default: pinctrl0 {
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gpio {
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ralink,group = "uart2", "uart3", "i2c", "pcie", "rgmii2", "jtag";
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ralink,function = "gpio";
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};
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};
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};
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&spi0 {
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/* This board has 2Mb spi flash soldered in and visible
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from manufacturer's firmware.
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But this SoC shares spi and nand pins,
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and current driver does't handle this sharing well */
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status = "disabled";
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m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <1>;
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spi-max-frequency = <10000000>;
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m25p,chunked-io = <32>;
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partition@0 {
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label = "spi";
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reg = <0x0 0x200000>;
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read-only;
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};
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};
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};
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&xhci {
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status = "disabled";
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};
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