bcm63xx: smp: add NAND support
NAND controller is present on BCM6328, BCM6362, BCM6368 and BCM63268. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>master
Álvaro Fernández Rojas
4 years ago
parent
dcee4eaa42
commit
86583384ff
@ -0,0 +1,35 @@
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#
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# BCM63XX NAND Profiles
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#
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DEVICE_VARS += CFE_RAM_FILE
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DEVICE_VARS += CFE_RAM_JFFS2_NAME CFE_RAM_JFFS2_PAD
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DEVICE_VARS += CFE_WFI_CHIP_ID CFE_WFI_FLASH_TYPE
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DEVICE_VARS += CFE_WFI_FLAGS CFE_WFI_VERSION
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# CFE expects a single JFFS2 partition with cferam and kernel. However,
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# it's possible to fool CFE into properly loading both cferam and kernel
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# from two different JFFS2 partitions by adding dummy files (see
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# cfe-jffs2-cferam and cfe-jffs2-kernel).
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# Separate JFFS2 partitions allow upgrading openwrt without reflashing cferam
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# JFFS2 partition, which is much safer in case anything goes wrong.
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define Device/bcm63xx-nand
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FILESYSTEMS := squashfs ubifs
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KERNEL := kernel-bin | append-dtb | relocate-kernel | lzma | cfe-jffs2-kernel
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KERNEL_INITRAMFS := kernel-bin | append-dtb | lzma | loader-lzma elf
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IMAGES := cfe.bin sysupgrade.bin
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IMAGE/cfe.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | cfe-jffs2-cferam | append-ubi | cfe-wfi-tag
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IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
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KERNEL_SIZE := 5120k
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CFE_CHIP_ID :=
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CFE_RAM_FILE :=
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CFE_RAM_JFFS2_NAME :=
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CFE_RAM_JFFS2_PAD :=
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CFE_WFI_VERSION := 0x5731
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CFE_WFI_CHIP_ID = 0x$$(CFE_CHIP_ID)
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CFE_WFI_FLASH_TYPE :=
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CFE_WFI_FLAGS :=
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UBINIZE_OPTS := -E 5
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DEVICE_PACKAGES += nand-utils
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SUPPORTED_DEVICES := $(subst _,$(comma),$(1))
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endef
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@ -0,0 +1,50 @@
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--- a/arch/mips/bcm63xx/clk.c
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+++ b/arch/mips/bcm63xx/clk.c
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@@ -430,6 +430,23 @@ static struct clk clk_pcie = {
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};
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/*
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+ * NAND clock
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+ */
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+static void nand_set(struct clk *clk, int enable)
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+{
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+ if (BCMCPU_IS_6362())
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+ bcm_hwclock_set(CKCTL_6362_NAND_EN, enable);
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+ else if (BCMCPU_IS_6368())
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+ bcm_hwclock_set(CKCTL_6368_NAND_EN, enable);
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+ else if (BCMCPU_IS_63268())
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+ bcm_hwclock_set(CKCTL_63268_NAND_EN, enable);
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+}
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+
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+static struct clk clk_nand = {
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+ .set = nand_set,
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+};
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+
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+/*
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* Internal peripheral clock
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*/
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static struct clk clk_periph = {
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@@ -612,6 +629,7 @@ static struct clk_lookup bcm6362_clks[]
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CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
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CLKDEV_INIT("10001000.spi", "pll", &clk_hsspi_pll),
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/* gated clocks */
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+ CLKDEV_INIT(NULL, "nand", &clk_nand),
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CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
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CLKDEV_INIT(NULL, "usbh", &clk_usbh),
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CLKDEV_INIT(NULL, "usbd", &clk_usbd),
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@@ -629,6 +647,7 @@ static struct clk_lookup bcm6368_clks[]
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CLKDEV_INIT("10000100.serial", "refclk", &clk_periph),
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CLKDEV_INIT("10000120.serial", "refclk", &clk_periph),
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/* gated clocks */
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+ CLKDEV_INIT(NULL, "nand", &clk_nand),
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CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
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CLKDEV_INIT(NULL, "usbh", &clk_usbh),
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CLKDEV_INIT(NULL, "usbd", &clk_usbd),
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@@ -647,6 +666,7 @@ static struct clk_lookup bcm63268_clks[]
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CLKDEV_INIT("bcm63xx-hsspi.0", "pll", &clk_hsspi_pll),
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CLKDEV_INIT("10001000.spi", "pll", &clk_hsspi_pll),
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/* gated clocks */
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+ CLKDEV_INIT(NULL, "nand", &clk_nand),
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CLKDEV_INIT(NULL, "enetsw", &clk_enetsw),
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CLKDEV_INIT(NULL, "usbh", &clk_usbh),
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CLKDEV_INIT(NULL, "usbd", &clk_usbd),
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@ -0,0 +1,145 @@
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@@ -181,7 +181,8 @@ enum bcm63xx_regs_set {
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RSET_PCMDMAC,
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RSET_PCMDMAS,
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RSET_RNG,
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- RSET_MISC
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+ RSET_MISC,
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+ RSET_NAND
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};
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#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
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@@ -259,6 +260,7 @@ enum bcm63xx_regs_set {
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#define BCM_3368_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_3368_RNG_BASE (0xdeadbeef)
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#define BCM_3368_MISC_BASE (0xdeadbeef)
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+#define BCM_3368_NAND_BASE (0xdeadbeef)
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/*
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* 6318 register sets base address
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@@ -306,6 +308,7 @@ enum bcm63xx_regs_set {
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#define BCM_6318_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6318_RNG_BASE (0xdeadbeef)
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#define BCM_6318_MISC_BASE (0xb0000280)
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+#define BCM_6318_NAND_BASE (0xdeadbeef)
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#define BCM_6318_OTP_BASE (0xdeadbeef)
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#define BCM_6318_STRAP_BASE (0xb0000900)
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@@ -356,6 +359,7 @@ enum bcm63xx_regs_set {
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#define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6328_RNG_BASE (0xdeadbeef)
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#define BCM_6328_MISC_BASE (0xb0001800)
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+#define BCM_6328_NAND_BASE (0xb0000200)
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#define BCM_6328_OTP_BASE (0xb0000600)
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/*
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@@ -405,6 +409,7 @@ enum bcm63xx_regs_set {
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#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6338_RNG_BASE (0xdeadbeef)
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#define BCM_6338_MISC_BASE (0xdeadbeef)
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+#define BCM_6338_NAND_BASE (0xdeadbeef)
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/*
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* 6345 register sets base address
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@@ -453,6 +458,7 @@ enum bcm63xx_regs_set {
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#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6345_RNG_BASE (0xdeadbeef)
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#define BCM_6345_MISC_BASE (0xdeadbeef)
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+#define BCM_6345_NAND_BASE (0xdeadbeef)
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/*
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* 6348 register sets base address
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@@ -499,6 +505,7 @@ enum bcm63xx_regs_set {
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#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6348_RNG_BASE (0xdeadbeef)
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#define BCM_6348_MISC_BASE (0xdeadbeef)
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+#define BCM_6348_NAND_BASE (0xdeadbeef)
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/*
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* 6358 register sets base address
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@@ -545,7 +552,7 @@ enum bcm63xx_regs_set {
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#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
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#define BCM_6358_RNG_BASE (0xdeadbeef)
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#define BCM_6358_MISC_BASE (0xdeadbeef)
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-
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+#define BCM_6358_NAND_BASE (0xdeadbeef)
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/*
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* 6362 register sets base address
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@@ -593,6 +600,7 @@ enum bcm63xx_regs_set {
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#define BCM_6362_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6362_RNG_BASE (0xdeadbeef)
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#define BCM_6362_MISC_BASE (0xb0001800)
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+#define BCM_6362_NAND_BASE (0xb0000200)
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#define BCM_6362_NAND_REG_BASE (0xb0000200)
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#define BCM_6362_NAND_CACHE_BASE (0xb0000600)
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@@ -648,6 +656,7 @@ enum bcm63xx_regs_set {
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#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
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#define BCM_6368_RNG_BASE (0xb0004180)
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#define BCM_6368_MISC_BASE (0xdeadbeef)
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+#define BCM_6368_NAND_BASE (0xb0000200)
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/*
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* 63268 register sets base address
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@@ -695,6 +704,7 @@ enum bcm63xx_regs_set {
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#define BCM_63268_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_63268_RNG_BASE (0xdeadbeef)
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#define BCM_63268_MISC_BASE (0xb0001800)
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+#define BCM_63268_NAND_BASE (0xb0000200)
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extern const unsigned long *bcm63xx_regs_base;
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@@ -740,6 +750,7 @@ extern const unsigned long *bcm63xx_regs
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[RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
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[RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \
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[RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \
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+ [RSET_NAND] = BCM_## __cpu ##_NAND_BASE, \
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static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
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@@ -111,5 +111,7 @@
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#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o))
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#define bcm_misc_readl(o) bcm_rset_readl(RSET_MISC, (o))
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#define bcm_misc_writel(v, o) bcm_rset_writel(RSET_MISC, (v), (o))
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+#define bcm_nand_readl(o) bcm_rset_readl(RSET_NAND, (o))
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+#define bcm_nand_writel(v, o) bcm_rset_writel(RSET_NAND, (v), (o))
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#endif /* ! BCM63XX_IO_H_ */
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -1688,4 +1688,31 @@
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#define OTP_USER_BITS_6328_REG(i) (0x20 + (i) * 4)
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#define OTP_6328_REG3_TP1_DISABLED BIT(9)
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+/*************************************************************************
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+ * _REG relative to RSET_NAND
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+ *************************************************************************/
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+
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+#define NAND_CS_SEL_REG 0x14
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+#define NAND_CS_SEL_EBC_CS0_SEL (1 << 0)
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+#define NAND_CS_SEL_EBC_CS1_SEL (1 << 1)
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+#define NAND_CS_SEL_EBC_CS2_SEL (1 << 2)
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+#define NAND_CS_SEL_EBC_CS3_SEL (1 << 3)
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+#define NAND_CS_SEL_EBC_CS4_SEL (1 << 4)
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+#define NAND_CS_SEL_EBC_CS5_SEL (1 << 5)
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+#define NAND_CS_SEL_EBC_CS6_SEL (1 << 6)
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+#define NAND_CS_SEL_EBC_CS7_SEL (1 << 7)
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+#define NAND_CS_SEL_EBI_CS0_USES_NAND (1 << 8)
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+#define NAND_CS_SEL_EBI_CS1_USES_NAND (1 << 9)
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+#define NAND_CS_SEL_EBI_CS2_USES_NAND (1 << 10)
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+#define NAND_CS_SEL_EBI_CS3_USES_NAND (1 << 11)
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+#define NAND_CS_SEL_EBI_CS4_USES_NAND (1 << 12)
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+#define NAND_CS_SEL_EBI_CS5_USES_NAND (1 << 13)
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+#define NAND_CS_SEL_EBI_CS6_USES_NAND (1 << 14)
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+#define NAND_CS_SEL_EBI_CS7_USES_NAND (1 << 15)
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+#define NAND_CS_SEL_WR_PROT_BLK0 (1 << 28)
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+#define NAND_CS_SEL_AUTO_DEV_ID (1 << 30)
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+#define NAND_CS_SEL_CS_LOCK (1 << 31)
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+
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+#define NAND_CS_XOR_REG 0x18
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+
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#endif /* BCM63XX_REGS_H_ */
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@ -0,0 +1,17 @@
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--- a/arch/mips/bcm63xx/dev-flash.c
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+++ b/arch/mips/bcm63xx/dev-flash.c
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@@ -229,6 +229,14 @@ void __init bcm63xx_flash_detect(void)
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}
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bcm_rset_writel(RSET_HSSPI, val, HSSPI_FLASH_CTRL_REG);
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+ } else if (flash_type == BCM63XX_FLASH_TYPE_NAND &&
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+ (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() ||
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+ BCMCPU_IS_63268())) {
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+ bcm_nand_writel(NAND_CS_SEL_AUTO_DEV_ID
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+ | NAND_CS_SEL_EBI_CS0_USES_NAND
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+ | NAND_CS_SEL_EBC_CS0_SEL,
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+ NAND_CS_SEL_REG);
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+ bcm_nand_writel(1, NAND_CS_XOR_REG);
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}
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}
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@ -0,0 +1,17 @@
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--- a/arch/mips/bcm63xx/dev-flash.c
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+++ b/arch/mips/bcm63xx/dev-flash.c
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@@ -271,8 +271,12 @@ int __init bcm63xx_flash_register(void)
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return -ENODEV;
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}
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case BCM63XX_FLASH_TYPE_NAND:
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- pr_warn("unsupported NAND flash detected\n");
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- return -ENODEV;
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+ if (board_of_device_present("nflash")) {
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+ return 0;
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+ } else {
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+ pr_warn("unsupported NAND flash detected\n");
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+ return -ENODEV;
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+ }
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default:
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pr_err("flash detection failed for BCM%x: %d\n",
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bcm63xx_get_cpu_id(), flash_type);
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@ -0,0 +1,11 @@
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--- a/drivers/mtd/nand/raw/nand_base.c
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+++ b/drivers/mtd/nand/raw/nand_base.c
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@@ -488,7 +488,7 @@ static int nand_do_write_oob(struct nand
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nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
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- if (ops->mode == MTD_OPS_RAW)
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+ if (ops->mode == MTD_OPS_AUTO_OOB || ops->mode == MTD_OPS_RAW)
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status = chip->ecc.write_oob_raw(chip, page & chip->pagemask);
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else
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status = chip->ecc.write_oob(chip, page & chip->pagemask);
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@ -0,0 +1,42 @@
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--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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@@ -1787,28 +1787,31 @@ static int brcmnand_read_by_pio(struct m
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static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd,
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struct nand_chip *chip, void *buf, u64 addr)
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{
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- int i, sas;
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- void *oob = chip->oob_poi;
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+ struct mtd_oob_region ecc;
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+ int i;
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int bitflips = 0;
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int page = addr >> chip->page_shift;
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int ret;
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+ void *ecc_bytes;
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void *ecc_chunk;
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if (!buf)
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buf = nand_get_data_buf(chip);
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- sas = mtd->oobsize / chip->ecc.steps;
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-
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/* read without ecc for verification */
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ret = chip->ecc.read_page_raw(chip, buf, true, page);
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if (ret)
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return ret;
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- for (i = 0; i < chip->ecc.steps; i++, oob += sas) {
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+ for (i = 0; i < chip->ecc.steps; i++) {
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ecc_chunk = buf + chip->ecc.size * i;
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- ret = nand_check_erased_ecc_chunk(ecc_chunk,
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- chip->ecc.size,
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- oob, sas, NULL, 0,
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+
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+ mtd_ooblayout_ecc(mtd, i, &ecc);
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+ ecc_bytes = chip->oob_poi + ecc.offset;
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+
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+ ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size,
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+ ecc_bytes, ecc.length,
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+ NULL, 0,
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chip->ecc.strength);
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if (ret < 0)
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return ret;
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@ -0,0 +1,21 @@
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--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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@@ -1019,11 +1019,14 @@ static int brcmnand_hamming_ooblayout_fr
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if (!section) {
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/*
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* Small-page NAND use byte 6 for BBI while large-page
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- * NAND use byte 0.
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+ * NAND use bytes 0 and 1.
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*/
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- if (cfg->page_size > 512)
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- oobregion->offset++;
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- oobregion->length--;
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+ if (cfg->page_size > 512) {
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+ oobregion->offset += 2;
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+ oobregion->length -= 2;
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+ } else {
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+ oobregion->length--;
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+ }
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}
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}
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@ -0,0 +1,52 @@
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--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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@@ -1003,33 +1003,30 @@ static int brcmnand_hamming_ooblayout_fr
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struct brcmnand_cfg *cfg = &host->hwcfg;
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int sas = cfg->spare_area_size << cfg->sector_size_1k;
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int sectors = cfg->page_size / (512 << cfg->sector_size_1k);
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+ u32 next;
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|
||||
- if (section >= sectors * 2)
|
||||
+ if (section > sectors)
|
||||
return -ERANGE;
|
||||
|
||||
- oobregion->offset = (section / 2) * sas;
|
||||
+ next = (section * sas);
|
||||
+ if (section < sectors)
|
||||
+ next += 6;
|
||||
|
||||
- if (section & 1) {
|
||||
- oobregion->offset += 9;
|
||||
- oobregion->length = 7;
|
||||
+ if (section) {
|
||||
+ oobregion->offset = ((section - 1) * sas) + 9;
|
||||
} else {
|
||||
- oobregion->length = 6;
|
||||
-
|
||||
- /* First sector of each page may have BBI */
|
||||
- if (!section) {
|
||||
- /*
|
||||
- * Small-page NAND use byte 6 for BBI while large-page
|
||||
- * NAND use bytes 0 and 1.
|
||||
- */
|
||||
- if (cfg->page_size > 512) {
|
||||
- oobregion->offset += 2;
|
||||
- oobregion->length -= 2;
|
||||
- } else {
|
||||
- oobregion->length--;
|
||||
- }
|
||||
+ if (cfg->page_size > 512) {
|
||||
+ /* Large page NAND uses first 2 bytes for BBI */
|
||||
+ oobregion->offset = 2;
|
||||
+ } else {
|
||||
+ /* Small page NAND uses last byte before ECC for BBI */
|
||||
+ oobregion->offset = 0;
|
||||
+ next--;
|
||||
}
|
||||
}
|
||||
|
||||
+ oobregion->length = next - oobregion->offset;
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -0,0 +1,24 @@
|
||||
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||
@@ -269,8 +269,8 @@ enum brcmnand_reg {
|
||||
BRCMNAND_FC_BASE,
|
||||
};
|
||||
|
||||
-/* BRCMNAND v4.0 */
|
||||
-static const u16 brcmnand_regs_v40[] = {
|
||||
+/* BRCMNAND v3.3-v4.0 */
|
||||
+static const u16 brcmnand_regs_v33[] = {
|
||||
[BRCMNAND_CMD_START] = 0x04,
|
||||
[BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
|
||||
[BRCMNAND_CMD_ADDRESS] = 0x0c,
|
||||
@@ -522,8 +522,8 @@ static int brcmnand_revision_init(struct
|
||||
ctrl->reg_offsets = brcmnand_regs_v60;
|
||||
else if (ctrl->nand_version >= 0x0500)
|
||||
ctrl->reg_offsets = brcmnand_regs_v50;
|
||||
- else if (ctrl->nand_version >= 0x0400)
|
||||
- ctrl->reg_offsets = brcmnand_regs_v40;
|
||||
+ else if (ctrl->nand_version >= 0x0303)
|
||||
+ ctrl->reg_offsets = brcmnand_regs_v33;
|
||||
|
||||
/* Chip-select stride */
|
||||
if (ctrl->nand_version >= 0x0701)
|
||||
@ -0,0 +1,14 @@
|
||||
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||
@@ -537,8 +537,9 @@ static int brcmnand_revision_init(struct
|
||||
} else {
|
||||
ctrl->cs_offsets = brcmnand_cs_offsets;
|
||||
|
||||
- /* v5.0 and earlier has a different CS0 offset layout */
|
||||
- if (ctrl->nand_version <= 0x0500)
|
||||
+ /* v3.3-5.0 have a different CS0 offset layout */
|
||||
+ if (ctrl->nand_version >= 0x0303 &&
|
||||
+ ctrl->nand_version <= 0x0500)
|
||||
ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
|
||||
}
|
||||
|
||||
@ -0,0 +1,20 @@
|
||||
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||
@@ -502,7 +502,7 @@ static int brcmnand_revision_init(struct
|
||||
{
|
||||
static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
|
||||
static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
|
||||
- static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
|
||||
+ static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 };
|
||||
|
||||
ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
|
||||
|
||||
@@ -549,7 +549,7 @@ static int brcmnand_revision_init(struct
|
||||
ctrl->max_page_size = 16 * 1024;
|
||||
ctrl->max_block_size = 2 * 1024 * 1024;
|
||||
} else {
|
||||
- ctrl->page_sizes = page_sizes;
|
||||
+ ctrl->page_sizes = page_sizes_v3_4;
|
||||
if (ctrl->nand_version >= 0x0600)
|
||||
ctrl->block_sizes = block_sizes_v6;
|
||||
else
|
||||
@ -0,0 +1,143 @@
|
||||
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||
+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
|
||||
@@ -269,6 +269,36 @@ enum brcmnand_reg {
|
||||
BRCMNAND_FC_BASE,
|
||||
};
|
||||
|
||||
+/* BRCMNAND v2.1-v2.2 */
|
||||
+static const u16 brcmnand_regs_v21[] = {
|
||||
+ [BRCMNAND_CMD_START] = 0x04,
|
||||
+ [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
|
||||
+ [BRCMNAND_CMD_ADDRESS] = 0x0c,
|
||||
+ [BRCMNAND_INTFC_STATUS] = 0x5c,
|
||||
+ [BRCMNAND_CS_SELECT] = 0x14,
|
||||
+ [BRCMNAND_CS_XOR] = 0x18,
|
||||
+ [BRCMNAND_LL_OP] = 0,
|
||||
+ [BRCMNAND_CS0_BASE] = 0x40,
|
||||
+ [BRCMNAND_CS1_BASE] = 0,
|
||||
+ [BRCMNAND_CORR_THRESHOLD] = 0,
|
||||
+ [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
|
||||
+ [BRCMNAND_UNCORR_COUNT] = 0,
|
||||
+ [BRCMNAND_CORR_COUNT] = 0,
|
||||
+ [BRCMNAND_CORR_EXT_ADDR] = 0x60,
|
||||
+ [BRCMNAND_CORR_ADDR] = 0x64,
|
||||
+ [BRCMNAND_UNCORR_EXT_ADDR] = 0x68,
|
||||
+ [BRCMNAND_UNCORR_ADDR] = 0x6c,
|
||||
+ [BRCMNAND_SEMAPHORE] = 0x50,
|
||||
+ [BRCMNAND_ID] = 0x54,
|
||||
+ [BRCMNAND_ID_EXT] = 0,
|
||||
+ [BRCMNAND_LL_RDATA] = 0,
|
||||
+ [BRCMNAND_OOB_READ_BASE] = 0x20,
|
||||
+ [BRCMNAND_OOB_READ_10_BASE] = 0,
|
||||
+ [BRCMNAND_OOB_WRITE_BASE] = 0x30,
|
||||
+ [BRCMNAND_OOB_WRITE_10_BASE] = 0,
|
||||
+ [BRCMNAND_FC_BASE] = 0x200,
|
||||
+};
|
||||
+
|
||||
/* BRCMNAND v3.3-v4.0 */
|
||||
static const u16 brcmnand_regs_v33[] = {
|
||||
[BRCMNAND_CMD_START] = 0x04,
|
||||
@@ -502,12 +532,16 @@ static int brcmnand_revision_init(struct
|
||||
{
|
||||
static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
|
||||
static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
|
||||
+ static const unsigned int block_sizes_v2_2[] = { 16, 128, 8, 512, 256, 0 };
|
||||
+ static const unsigned int block_sizes_v2_1[] = { 16, 128, 8, 512, 0 };
|
||||
static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 };
|
||||
+ static const unsigned int page_sizes_v2_2[] = { 512, 2048, 4096, 0 };
|
||||
+ static const unsigned int page_sizes_v2_1[] = { 512, 2048, 0 };
|
||||
|
||||
ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
|
||||
|
||||
- /* Only support v4.0+? */
|
||||
- if (ctrl->nand_version < 0x0400) {
|
||||
+ /* Only support v2.1+ */
|
||||
+ if (ctrl->nand_version < 0x0201) {
|
||||
dev_err(ctrl->dev, "version %#x not supported\n",
|
||||
ctrl->nand_version);
|
||||
return -ENODEV;
|
||||
@@ -524,6 +558,8 @@ static int brcmnand_revision_init(struct
|
||||
ctrl->reg_offsets = brcmnand_regs_v50;
|
||||
else if (ctrl->nand_version >= 0x0303)
|
||||
ctrl->reg_offsets = brcmnand_regs_v33;
|
||||
+ else if (ctrl->nand_version >= 0x0201)
|
||||
+ ctrl->reg_offsets = brcmnand_regs_v21;
|
||||
|
||||
/* Chip-select stride */
|
||||
if (ctrl->nand_version >= 0x0701)
|
||||
@@ -549,14 +585,27 @@ static int brcmnand_revision_init(struct
|
||||
ctrl->max_page_size = 16 * 1024;
|
||||
ctrl->max_block_size = 2 * 1024 * 1024;
|
||||
} else {
|
||||
- ctrl->page_sizes = page_sizes_v3_4;
|
||||
+ if (ctrl->nand_version >= 0x0304)
|
||||
+ ctrl->page_sizes = page_sizes_v3_4;
|
||||
+ else if (ctrl->nand_version >= 0x0202)
|
||||
+ ctrl->page_sizes = page_sizes_v2_2;
|
||||
+ else
|
||||
+ ctrl->page_sizes = page_sizes_v2_1;
|
||||
+
|
||||
if (ctrl->nand_version >= 0x0600)
|
||||
ctrl->block_sizes = block_sizes_v6;
|
||||
- else
|
||||
+ else if (ctrl->nand_version >= 0x0400)
|
||||
ctrl->block_sizes = block_sizes_v4;
|
||||
+ else if (ctrl->nand_version >= 0x0202)
|
||||
+ ctrl->block_sizes = block_sizes_v2_2;
|
||||
+ else
|
||||
+ ctrl->block_sizes = block_sizes_v2_1;
|
||||
|
||||
if (ctrl->nand_version < 0x0400) {
|
||||
- ctrl->max_page_size = 4096;
|
||||
+ if (ctrl->nand_version < 0x0202)
|
||||
+ ctrl->max_page_size = 2048;
|
||||
+ else
|
||||
+ ctrl->max_page_size = 4096;
|
||||
ctrl->max_block_size = 512 * 1024;
|
||||
}
|
||||
}
|
||||
@@ -724,6 +773,9 @@ static void brcmnand_wr_corr_thresh(stru
|
||||
enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
|
||||
int cs = host->cs;
|
||||
|
||||
+ if (!ctrl->reg_offsets[reg])
|
||||
+ return;
|
||||
+
|
||||
if (ctrl->nand_version == 0x0702)
|
||||
bits = 7;
|
||||
else if (ctrl->nand_version >= 0x0600)
|
||||
@@ -782,8 +834,10 @@ static inline u32 brcmnand_spare_area_ma
|
||||
return GENMASK(7, 0);
|
||||
else if (ctrl->nand_version >= 0x0600)
|
||||
return GENMASK(6, 0);
|
||||
- else
|
||||
+ else if (ctrl->nand_version >= 0x0303)
|
||||
return GENMASK(5, 0);
|
||||
+ else
|
||||
+ return GENMASK(4, 0);
|
||||
}
|
||||
|
||||
#define NAND_ACC_CONTROL_ECC_SHIFT 16
|
||||
@@ -2158,9 +2212,11 @@ static int brcmnand_set_cfg(struct brcmn
|
||||
|
||||
tmp = nand_readreg(ctrl, acc_control_offs);
|
||||
tmp &= ~brcmnand_ecc_level_mask(ctrl);
|
||||
- tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
|
||||
tmp &= ~brcmnand_spare_area_mask(ctrl);
|
||||
- tmp |= cfg->spare_area_size;
|
||||
+ if (ctrl->nand_version >= 0x0302) {
|
||||
+ tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
|
||||
+ tmp |= cfg->spare_area_size;
|
||||
+ }
|
||||
nand_writereg(ctrl, acc_control_offs, tmp);
|
||||
|
||||
brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
|
||||
@@ -2524,6 +2580,8 @@ const struct dev_pm_ops brcmnand_pm_ops
|
||||
EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
|
||||
|
||||
static const struct of_device_id brcmnand_of_match[] = {
|
||||
+ { .compatible = "brcm,brcmnand-v2.1" },
|
||||
+ { .compatible = "brcm,brcmnand-v2.2" },
|
||||
{ .compatible = "brcm,brcmnand-v4.0" },
|
||||
{ .compatible = "brcm,brcmnand-v5.0" },
|
||||
{ .compatible = "brcm,brcmnand-v6.0" },
|
||||
@ -1,17 +1,48 @@
|
||||
CONFIG_CPU_RMAP=y
|
||||
CONFIG_CRC16=y
|
||||
CONFIG_CRYPTO_ACOMP2=y
|
||||
CONFIG_CRYPTO_AEAD=y
|
||||
CONFIG_CRYPTO_AEAD2=y
|
||||
CONFIG_CRYPTO_DEFLATE=y
|
||||
CONFIG_CRYPTO_HASH_INFO=y
|
||||
CONFIG_CRYPTO_HASH2=y
|
||||
CONFIG_CRYPTO_LZO=y
|
||||
CONFIG_CRYPTO_MANAGER=y
|
||||
CONFIG_CRYPTO_MANAGER2=y
|
||||
CONFIG_CRYPTO_NULL2=y
|
||||
CONFIG_CRYPTO_ZSTD=y
|
||||
CONFIG_JFFS2_FS_NAND=y
|
||||
CONFIG_LZO_COMPRESS=y
|
||||
CONFIG_LZO_DECOMPRESS=y
|
||||
CONFIG_MTD_NAND_BRCMNAND=y
|
||||
CONFIG_MTD_NAND_CORE=y
|
||||
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_MTD_SPLIT_BCM_WFI_FW=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_BEB_LIMIT=20
|
||||
CONFIG_MTD_UBI_BLOCK=y
|
||||
# CONFIG_MTD_UBI_FASTMAP is not set
|
||||
# CONFIG_MTD_UBI_GLUEBI is not set
|
||||
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NR_CPUS=2
|
||||
CONFIG_PADATA=y
|
||||
CONFIG_RCU_STALL_COMMON=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_SGL_ALLOC=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SMP_UP=y
|
||||
CONFIG_TREE_RCU=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
|
||||
CONFIG_UBIFS_FS_LZO=y
|
||||
CONFIG_UBIFS_FS_ZLIB=y
|
||||
CONFIG_UBIFS_FS_ZSTD=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XXHASH=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZSTD_COMPRESS=y
|
||||
CONFIG_ZSTD_DECOMPRESS=y
|
||||
|
||||
Loading…
Reference in New Issue