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144 lines
4.7 KiB
Diff
144 lines
4.7 KiB
Diff
--- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
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@@ -269,6 +269,36 @@ enum brcmnand_reg {
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BRCMNAND_FC_BASE,
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};
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+/* BRCMNAND v2.1-v2.2 */
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+static const u16 brcmnand_regs_v21[] = {
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+ [BRCMNAND_CMD_START] = 0x04,
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+ [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
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+ [BRCMNAND_CMD_ADDRESS] = 0x0c,
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+ [BRCMNAND_INTFC_STATUS] = 0x5c,
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+ [BRCMNAND_CS_SELECT] = 0x14,
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+ [BRCMNAND_CS_XOR] = 0x18,
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+ [BRCMNAND_LL_OP] = 0,
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+ [BRCMNAND_CS0_BASE] = 0x40,
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+ [BRCMNAND_CS1_BASE] = 0,
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+ [BRCMNAND_CORR_THRESHOLD] = 0,
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+ [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
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+ [BRCMNAND_UNCORR_COUNT] = 0,
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+ [BRCMNAND_CORR_COUNT] = 0,
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+ [BRCMNAND_CORR_EXT_ADDR] = 0x60,
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+ [BRCMNAND_CORR_ADDR] = 0x64,
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+ [BRCMNAND_UNCORR_EXT_ADDR] = 0x68,
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+ [BRCMNAND_UNCORR_ADDR] = 0x6c,
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+ [BRCMNAND_SEMAPHORE] = 0x50,
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+ [BRCMNAND_ID] = 0x54,
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+ [BRCMNAND_ID_EXT] = 0,
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+ [BRCMNAND_LL_RDATA] = 0,
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+ [BRCMNAND_OOB_READ_BASE] = 0x20,
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+ [BRCMNAND_OOB_READ_10_BASE] = 0,
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+ [BRCMNAND_OOB_WRITE_BASE] = 0x30,
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+ [BRCMNAND_OOB_WRITE_10_BASE] = 0,
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+ [BRCMNAND_FC_BASE] = 0x200,
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+};
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+
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/* BRCMNAND v3.3-v4.0 */
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static const u16 brcmnand_regs_v33[] = {
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[BRCMNAND_CMD_START] = 0x04,
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@@ -502,12 +532,16 @@ static int brcmnand_revision_init(struct
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{
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static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
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static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
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+ static const unsigned int block_sizes_v2_2[] = { 16, 128, 8, 512, 256, 0 };
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+ static const unsigned int block_sizes_v2_1[] = { 16, 128, 8, 512, 0 };
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static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 };
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+ static const unsigned int page_sizes_v2_2[] = { 512, 2048, 4096, 0 };
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+ static const unsigned int page_sizes_v2_1[] = { 512, 2048, 0 };
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ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
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- /* Only support v4.0+? */
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- if (ctrl->nand_version < 0x0400) {
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+ /* Only support v2.1+ */
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+ if (ctrl->nand_version < 0x0201) {
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dev_err(ctrl->dev, "version %#x not supported\n",
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ctrl->nand_version);
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return -ENODEV;
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@@ -524,6 +558,8 @@ static int brcmnand_revision_init(struct
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ctrl->reg_offsets = brcmnand_regs_v50;
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else if (ctrl->nand_version >= 0x0303)
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ctrl->reg_offsets = brcmnand_regs_v33;
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+ else if (ctrl->nand_version >= 0x0201)
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+ ctrl->reg_offsets = brcmnand_regs_v21;
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/* Chip-select stride */
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if (ctrl->nand_version >= 0x0701)
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@@ -549,14 +585,27 @@ static int brcmnand_revision_init(struct
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ctrl->max_page_size = 16 * 1024;
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ctrl->max_block_size = 2 * 1024 * 1024;
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} else {
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- ctrl->page_sizes = page_sizes_v3_4;
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+ if (ctrl->nand_version >= 0x0304)
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+ ctrl->page_sizes = page_sizes_v3_4;
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+ else if (ctrl->nand_version >= 0x0202)
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+ ctrl->page_sizes = page_sizes_v2_2;
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+ else
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+ ctrl->page_sizes = page_sizes_v2_1;
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+
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if (ctrl->nand_version >= 0x0600)
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ctrl->block_sizes = block_sizes_v6;
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- else
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+ else if (ctrl->nand_version >= 0x0400)
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ctrl->block_sizes = block_sizes_v4;
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+ else if (ctrl->nand_version >= 0x0202)
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+ ctrl->block_sizes = block_sizes_v2_2;
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+ else
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+ ctrl->block_sizes = block_sizes_v2_1;
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if (ctrl->nand_version < 0x0400) {
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- ctrl->max_page_size = 4096;
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+ if (ctrl->nand_version < 0x0202)
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+ ctrl->max_page_size = 2048;
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+ else
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+ ctrl->max_page_size = 4096;
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ctrl->max_block_size = 512 * 1024;
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}
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}
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@@ -724,6 +773,9 @@ static void brcmnand_wr_corr_thresh(stru
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enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
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int cs = host->cs;
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+ if (!ctrl->reg_offsets[reg])
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+ return;
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+
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if (ctrl->nand_version == 0x0702)
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bits = 7;
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else if (ctrl->nand_version >= 0x0600)
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@@ -782,8 +834,10 @@ static inline u32 brcmnand_spare_area_ma
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return GENMASK(7, 0);
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else if (ctrl->nand_version >= 0x0600)
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return GENMASK(6, 0);
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- else
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+ else if (ctrl->nand_version >= 0x0303)
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return GENMASK(5, 0);
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+ else
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+ return GENMASK(4, 0);
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}
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#define NAND_ACC_CONTROL_ECC_SHIFT 16
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@@ -2158,9 +2212,11 @@ static int brcmnand_set_cfg(struct brcmn
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tmp = nand_readreg(ctrl, acc_control_offs);
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tmp &= ~brcmnand_ecc_level_mask(ctrl);
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- tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
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tmp &= ~brcmnand_spare_area_mask(ctrl);
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- tmp |= cfg->spare_area_size;
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+ if (ctrl->nand_version >= 0x0302) {
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+ tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
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+ tmp |= cfg->spare_area_size;
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+ }
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nand_writereg(ctrl, acc_control_offs, tmp);
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brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
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@@ -2524,6 +2580,8 @@ const struct dev_pm_ops brcmnand_pm_ops
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EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
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static const struct of_device_id brcmnand_of_match[] = {
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+ { .compatible = "brcm,brcmnand-v2.1" },
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+ { .compatible = "brcm,brcmnand-v2.2" },
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{ .compatible = "brcm,brcmnand-v4.0" },
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{ .compatible = "brcm,brcmnand-v5.0" },
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{ .compatible = "brcm,brcmnand-v6.0" },
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