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@ -72,12 +72,12 @@
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reg = <0x18000000 0x100>;
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};
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sbs2@1D000000 {
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sbs2@1d000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,sysb2", "simple-bus";
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reg = <0x1D000000 0x1000000>;
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ranges = <0x0 0x1D000000 0x1000000>;
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reg = <0x1d000000 0x1000000>;
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ranges = <0x0 0x1d000000 0x1000000>;
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clock_sysgpe: clock-controller@700000 {
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compatible = "lantiq,sysgpe-falcon";
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@ -117,38 +117,38 @@
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clocks = <&clock_syseth 17>;
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};
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clock_syseth: clock-controller@B00000 {
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clock_syseth: clock-controller@b00000 {
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compatible = "lantiq,syseth-falcon";
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reg = <0xB00000 0x100>;
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reg = <0xb00000 0x100>;
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#clock-cells = <1>;
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};
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pad@B01000 {
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pad@b01000 {
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compatible = "lantiq,pad-falcon";
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reg = <0xB01000 0x100>;
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reg = <0xb01000 0x100>;
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lantiq,bank = <0>;
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clocks = <&clock_syseth 20>;
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};
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pad@B02000 {
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pad@b02000 {
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compatible = "lantiq,pad-falcon";
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reg = <0xB02000 0x100>;
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reg = <0xb02000 0x100>;
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lantiq,bank = <2>;
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clocks = <&clock_syseth 21>;
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};
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};
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fpi@1E000000 {
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fpi@1e000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,fpi", "simple-bus";
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reg = <0x1E000000 0x1000000>;
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ranges = <0x0 0x1E000000 0x1000000>;
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reg = <0x1e000000 0x1000000>;
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ranges = <0x0 0x1e000000 0x1000000>;
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serial1: serial@100B00 {
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serial1: serial@100b00 {
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status = "disabled";
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compatible = "lantiq,asc";
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reg = <0x100B00 0x100>;
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reg = <0x100b00 0x100>;
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interrupt-parent = <&icu0>;
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interrupts = <112 113 114>;
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line = <1>;
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@ -157,9 +157,9 @@
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clocks = <&clock_sys1 11>;
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};
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serial0: serial@100C00 {
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serial0: serial@100c00 {
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compatible = "lantiq,asc";
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reg = <0x100C00 0x100>;
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reg = <0x100c00 0x100>;
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interrupt-parent = <&icu0>;
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interrupts = <104 105 106>;
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line = <0>;
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@ -168,23 +168,23 @@
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clocks = <&clock_sys1 12>;
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};
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spi: spi@100D00 {
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spi: spi@100d00 {
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status = "disabled";
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compatible = "lantiq,falcon-spi", "lantiq,xrx100-spi", "lantiq,spi-lantiq-ssc";
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interrupts = <22 23 24 25>;
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interrupt-names = "spi_tx", "spi_rx", "spi_err", "spi_frm";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x100D00 0x100>;
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reg = <0x100d00 0x100>;
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interrupt-parent = <&icu0>;
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clocks = <&clock_sys1 13>;
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base_cs = <1>;
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num_cs = <2>;
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};
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gptc@100E00 {
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gptc@100e00 {
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compatible = "lantiq,gptc-falcon";
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reg = <0x100E00 0x100>;
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reg = <0x100e00 0x100>;
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};
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i2c: i2c@200000 {
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@ -263,35 +263,35 @@
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reg = <0x802000 0x80>;
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};
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clock_sys1: clock-controller@F00000 {
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clock_sys1: clock-controller@f00000 {
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compatible = "lantiq,sys1-falcon";
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reg = <0xF00000 0x100>;
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reg = <0xf00000 0x100>;
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#clock-cells = <1>;
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};
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};
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sbs0@1F000000 {
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sbs0@1f000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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reg = <0x1F000000 0x400000>;
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ranges = <0x0 0x1F000000 0x400000>;
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reg = <0x1f000000 0x400000>;
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ranges = <0x0 0x1f000000 0x400000>;
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mpsmbx: mpsmbx@200000 {
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reg = <0x200000 0x200>;
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};
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};
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sbs1@1F700000 {
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sbs1@1f700000 {
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};
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biu@1F800000 {
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biu@1f800000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "lantiq,biu", "simple-bus";
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reg = <0x1F800000 0x800000>;
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ranges = <0x0 0x1F800000 0x800000>;
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reg = <0x1f800000 0x800000>;
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ranges = <0x0 0x1f800000 0x800000>;
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icu0: icu@80200 {
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#interrupt-cells = <1>;
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@ -304,9 +304,9 @@
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0x802a0 0x28>;
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};
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watchdog@803F0 {
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watchdog@803f0 {
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compatible = "lantiq,wdt";
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reg = <0x803F0 0x10>;
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reg = <0x803f0 0x10>;
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|
|
clocks = <&io_clk>; /* currently no effect */
|
|
|
|
|
};
|
|
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|
|
};
|
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