bcm27xx: update patches from RPi foundation
bcm2708: boot tested on RPi B+ v1.2 bcm2709: boot tested on RPi 3B v1.2 bcm2710: boot tested on RPi 3B v1.2 bcm2711: boot tested on RPi 4B v1.1 4G Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>master
Álvaro Fernández Rojas
4 years ago
parent
9e467a764b
commit
584d4bf1d3
@ -1,23 +0,0 @@
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From a19956ff2941b73204c96127a22edef71b5d0d34 Mon Sep 17 00:00:00 2001
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From: popcornmix <popcornmix@gmail.com>
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Date: Mon, 9 Sep 2019 23:50:44 +0100
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Subject: [PATCH] v3d_drv: Allow clock retrieval by name
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Signed-off-by: Phil Elwell <phil@raspberrypi.org>
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---
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drivers/gpu/drm/v3d/v3d_drv.c | 4 +++-
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1 file changed, 3 insertions(+), 1 deletion(-)
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--- a/drivers/gpu/drm/v3d/v3d_drv.c
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+++ b/drivers/gpu/drm/v3d/v3d_drv.c
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@@ -285,7 +285,9 @@ static int v3d_platform_drm_probe(struct
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}
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}
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- v3d->clk = devm_clk_get(dev, NULL);
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+ v3d->clk = devm_clk_get(dev, "v3d");
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+ if (!v3d->clk)
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+ v3d->clk = devm_clk_get(dev, NULL);
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if (IS_ERR_OR_NULL(v3d->clk)) {
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if (PTR_ERR(v3d->clk) != -EPROBE_DEFER)
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dev_err(dev, "Failed to get clock (%ld)\n", PTR_ERR(v3d->clk));
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@ -1,647 +0,0 @@
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From e2262c8ab4755ab574580611d7da22509f07871c Mon Sep 17 00:00:00 2001
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From: popcornmix <popcornmix@gmail.com>
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Date: Wed, 21 Aug 2019 14:55:56 +0100
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Subject: [PATCH] clk-raspberrypi: Also support v3d clock
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Signed-off-by: popcornmix <popcornmix@gmail.com>
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---
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drivers/clk/bcm/clk-raspberrypi.c | 501 ++++++++++++++++++++++++------
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1 file changed, 412 insertions(+), 89 deletions(-)
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--- a/drivers/clk/bcm/clk-raspberrypi.c
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+++ b/drivers/clk/bcm/clk-raspberrypi.c
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@@ -15,33 +15,103 @@
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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-
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+#include <dt-bindings/clock/bcm2835.h>
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#include <soc/bcm2835/raspberrypi-firmware.h>
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#define RPI_FIRMWARE_ARM_CLK_ID 0x00000003
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+#define RPI_FIRMWARE_V3D_CLK_ID 0x00000005
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#define RPI_FIRMWARE_STATE_ENABLE_BIT BIT(0)
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#define RPI_FIRMWARE_STATE_WAIT_BIT BIT(1)
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-/*
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- * Even though the firmware interface alters 'pllb' the frequencies are
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- * provided as per 'pllb_arm'. We need to scale before passing them trough.
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- */
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-#define RPI_FIRMWARE_PLLB_ARM_DIV_RATE 2
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-
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#define A2W_PLL_FRAC_BITS 20
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+#define SOC_BCM2835 BIT(0)
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+#define SOC_BCM2711 BIT(1)
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+#define SOC_ALL (SOC_BCM2835 | SOC_BCM2711)
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+
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struct raspberrypi_clk {
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struct device *dev;
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struct rpi_firmware *firmware;
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struct platform_device *cpufreq;
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+};
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+
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+typedef int (*raspberrypi_clk_register)(struct raspberrypi_clk *rpi,
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+ const void *data);
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+
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+
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+/* assignment helper macros for different clock types */
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+#define _REGISTER(f, s, ...) { .clk_register = (raspberrypi_clk_register)f, \
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+ .supported = s, \
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+ .data = __VA_ARGS__ }
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+#define REGISTER_PLL(s, ...) _REGISTER(&raspberrypi_register_pll, \
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+ s, \
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+ &(struct raspberrypi_pll_data) \
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+ {__VA_ARGS__})
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+#define REGISTER_PLL_DIV(s, ...) _REGISTER(&raspberrypi_register_pll_divider, \
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+ s, \
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+ &(struct raspberrypi_pll_divider_data) \
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+ {__VA_ARGS__})
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+#define REGISTER_CLK(s, ...) _REGISTER(&raspberrypi_register_clock, \
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+ s, \
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+ &(struct raspberrypi_clock_data) \
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+ {__VA_ARGS__})
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+
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+
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+struct raspberrypi_pll_data {
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+ const char *name;
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+ const char *const *parents;
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+ int num_parents;
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+ u32 clock_id;
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+};
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+
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+struct raspberrypi_clock_data {
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+ const char *name;
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+ const char *const *parents;
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+ int num_parents;
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+ u32 flags;
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+ u32 clock_id;
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+};
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+
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+struct raspberrypi_pll_divider_data {
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+ const char *name;
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+ const char *divider_name;
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+ const char *lookup;
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+ const char *source_pll;
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+
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+ u32 fixed_divider;
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+ u32 flags;
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+ u32 clock_id;
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+};
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- unsigned long min_rate;
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- unsigned long max_rate;
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+struct raspberrypi_clk_desc {
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+ raspberrypi_clk_register clk_register;
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+ unsigned int supported;
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+ const void *data;
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+};
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- struct clk_hw pllb;
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- struct clk_hw *pllb_arm;
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- struct clk_lookup *pllb_arm_lookup;
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+struct raspberrypi_clock {
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+ struct clk_hw hw;
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+ struct raspberrypi_clk *rpi;
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+ u32 min_rate;
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+ u32 max_rate;
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+ const struct raspberrypi_clock_data *data;
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+};
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+
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+struct raspberrypi_pll {
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+ struct clk_hw hw;
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+ struct raspberrypi_clk *rpi;
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+ u32 min_rate;
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+ u32 max_rate;
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+ const struct raspberrypi_pll_data *data;
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+};
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+
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+struct raspberrypi_pll_divider {
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+ struct clk_divider div;
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+ struct raspberrypi_clk *rpi;
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+ u32 min_rate;
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+ u32 max_rate;
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+ const struct raspberrypi_pll_divider_data *data;
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};
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/*
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@@ -83,56 +153,49 @@ static int raspberrypi_clock_property(st
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return 0;
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}
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-static int raspberrypi_fw_pll_is_on(struct clk_hw *hw)
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+static int raspberrypi_fw_is_on(struct raspberrypi_clk *rpi, u32 clock_id, const char *name)
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{
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- struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
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- pllb);
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u32 val = 0;
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int ret;
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ret = raspberrypi_clock_property(rpi->firmware,
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RPI_FIRMWARE_GET_CLOCK_STATE,
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- RPI_FIRMWARE_ARM_CLK_ID, &val);
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+ clock_id, &val);
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if (ret)
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return 0;
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return !!(val & RPI_FIRMWARE_STATE_ENABLE_BIT);
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}
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-
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-static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
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- unsigned long parent_rate)
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+static unsigned long raspberrypi_fw_get_rate(struct raspberrypi_clk *rpi,
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+ u32 clock_id, const char *name, unsigned long parent_rate)
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{
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- struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
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- pllb);
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u32 val = 0;
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int ret;
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ret = raspberrypi_clock_property(rpi->firmware,
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RPI_FIRMWARE_GET_CLOCK_RATE,
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- RPI_FIRMWARE_ARM_CLK_ID,
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+ clock_id,
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&val);
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if (ret)
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- return ret;
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-
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- return val * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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+ dev_err_ratelimited(rpi->dev, "Failed to get %s frequency: %d",
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+ name, ret);
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+ return val;
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}
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-static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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- unsigned long parent_rate)
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+static int raspberrypi_fw_set_rate(struct raspberrypi_clk *rpi,
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+ u32 clock_id, const char *name, u32 rate,
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+ unsigned long parent_rate)
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{
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- struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
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- pllb);
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- u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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int ret;
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ret = raspberrypi_clock_property(rpi->firmware,
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RPI_FIRMWARE_SET_CLOCK_RATE,
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- RPI_FIRMWARE_ARM_CLK_ID,
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- &new_rate);
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+ clock_id,
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+ &rate);
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if (ret)
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dev_err_ratelimited(rpi->dev, "Failed to change %s frequency: %d",
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- clk_hw_get_name(hw), ret);
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+ name, ret);
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return ret;
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}
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@@ -141,16 +204,18 @@ static int raspberrypi_fw_pll_set_rate(s
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* Sadly there is no firmware rate rounding interface. We borrowed it from
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* clk-bcm2835.
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*/
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-static int raspberrypi_pll_determine_rate(struct clk_hw *hw,
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+static int raspberrypi_determine_rate(struct raspberrypi_clk *rpi,
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+ u32 clock_id, const char *name, unsigned long min_rate, unsigned long max_rate,
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struct clk_rate_request *req)
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{
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- struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
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- pllb);
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+#if 1
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+ req->rate = clamp(req->rate, min_rate, max_rate);
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+#else
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u64 div, final_rate;
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u32 ndiv, fdiv;
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/* We can't use req->rate directly as it would overflow */
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- final_rate = clamp(req->rate, rpi->min_rate, rpi->max_rate);
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+ final_rate = clamp(req->rate, min_rate, max_rate);
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div = (u64)final_rate << A2W_PLL_FRAC_BITS;
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do_div(div, req->best_parent_rate);
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@@ -163,9 +228,129 @@ static int raspberrypi_pll_determine_rat
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req->rate = final_rate >> A2W_PLL_FRAC_BITS;
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+#endif
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return 0;
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}
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+static int raspberrypi_fw_clock_is_on(struct clk_hw *hw)
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+{
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+ struct raspberrypi_clock *pll = container_of(hw, struct raspberrypi_clock, hw);
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+ struct raspberrypi_clk *rpi = pll->rpi;
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+ const struct raspberrypi_clock_data *data = pll->data;
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+
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+ return raspberrypi_fw_is_on(rpi, data->clock_id, data->name);
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+}
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+
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+static unsigned long raspberrypi_fw_clock_get_rate(struct clk_hw *hw,
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+ unsigned long parent_rate)
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+{
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+ struct raspberrypi_clock *pll = container_of(hw, struct raspberrypi_clock, hw);
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+ struct raspberrypi_clk *rpi = pll->rpi;
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+ const struct raspberrypi_clock_data *data = pll->data;
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+
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+ return raspberrypi_fw_get_rate(rpi, data->clock_id, data->name, parent_rate);
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+}
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+
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+static int raspberrypi_fw_clock_set_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long parent_rate)
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+{
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+ struct raspberrypi_clock *pll = container_of(hw, struct raspberrypi_clock, hw);
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+ struct raspberrypi_clk *rpi = pll->rpi;
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+ const struct raspberrypi_clock_data *data = pll->data;
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+
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+ return raspberrypi_fw_set_rate(rpi, data->clock_id, data->name, rate, parent_rate);
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+}
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+
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+static int raspberrypi_clock_determine_rate(struct clk_hw *hw,
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+ struct clk_rate_request *req)
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+{
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+ struct raspberrypi_clock *pll = container_of(hw, struct raspberrypi_clock, hw);
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+ struct raspberrypi_clk *rpi = pll->rpi;
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+ const struct raspberrypi_clock_data *data = pll->data;
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+
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+ return raspberrypi_determine_rate(rpi, data->clock_id, data->name, pll->min_rate, pll->max_rate, req);
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+}
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+
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+static int raspberrypi_fw_pll_is_on(struct clk_hw *hw)
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+{
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+ struct raspberrypi_pll *pll = container_of(hw, struct raspberrypi_pll, hw);
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+ struct raspberrypi_clk *rpi = pll->rpi;
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+ const struct raspberrypi_pll_data *data = pll->data;
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+
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+ return raspberrypi_fw_is_on(rpi, data->clock_id, data->name);
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+}
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+
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+static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
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+ unsigned long parent_rate)
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+{
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+ struct raspberrypi_pll *pll = container_of(hw, struct raspberrypi_pll, hw);
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+ struct raspberrypi_clk *rpi = pll->rpi;
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+ const struct raspberrypi_pll_data *data = pll->data;
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+
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+ return raspberrypi_fw_get_rate(rpi, data->clock_id, data->name, parent_rate);
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+}
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+
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+static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long parent_rate)
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+{
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+ struct raspberrypi_pll *pll = container_of(hw, struct raspberrypi_pll, hw);
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+ struct raspberrypi_clk *rpi = pll->rpi;
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+ const struct raspberrypi_pll_data *data = pll->data;
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+
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+ return raspberrypi_fw_set_rate(rpi, data->clock_id, data->name, rate, parent_rate);
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+}
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+
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+static int raspberrypi_pll_determine_rate(struct clk_hw *hw,
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+ struct clk_rate_request *req)
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+{
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+ struct raspberrypi_pll *pll = container_of(hw, struct raspberrypi_pll, hw);
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+ struct raspberrypi_clk *rpi = pll->rpi;
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+ const struct raspberrypi_pll_data *data = pll->data;
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+
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+ return raspberrypi_determine_rate(rpi, data->clock_id, data->name, pll->min_rate, pll->max_rate, req);
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+}
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+
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+
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+static int raspberrypi_fw_pll_div_is_on(struct clk_hw *hw)
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+{
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+ struct raspberrypi_pll_divider *pll = container_of(hw, struct raspberrypi_pll_divider, div.hw);
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+ struct raspberrypi_clk *rpi = pll->rpi;
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+ const struct raspberrypi_pll_divider_data *data = pll->data;
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+
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+ return raspberrypi_fw_is_on(rpi, data->clock_id, data->name);
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+}
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+
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+static unsigned long raspberrypi_fw_pll_div_get_rate(struct clk_hw *hw,
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+ unsigned long parent_rate)
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+{
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+ struct raspberrypi_pll_divider *pll = container_of(hw, struct raspberrypi_pll_divider, div.hw);
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+ struct raspberrypi_clk *rpi = pll->rpi;
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+ const struct raspberrypi_pll_divider_data *data = pll->data;
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+
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+ return raspberrypi_fw_get_rate(rpi, data->clock_id, data->name, parent_rate);
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+}
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+
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+static int raspberrypi_fw_pll_div_set_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long parent_rate)
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+{
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+ struct raspberrypi_pll_divider *pll = container_of(hw, struct raspberrypi_pll_divider, div.hw);
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+ struct raspberrypi_clk *rpi = pll->rpi;
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+ const struct raspberrypi_pll_divider_data *data = pll->data;
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+
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+ return raspberrypi_fw_set_rate(rpi, data->clock_id, data->name, rate, parent_rate);
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+}
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+
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+static int raspberrypi_pll_div_determine_rate(struct clk_hw *hw,
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+ struct clk_rate_request *req)
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+{
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+ struct raspberrypi_pll_divider *pll = container_of(hw, struct raspberrypi_pll_divider, div.hw);
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+ struct raspberrypi_clk *rpi = pll->rpi;
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+ const struct raspberrypi_pll_divider_data *data = pll->data;
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+
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+ return raspberrypi_determine_rate(rpi, data->clock_id, data->name, pll->min_rate, pll->max_rate, req);
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+}
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+
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+
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static const struct clk_ops raspberrypi_firmware_pll_clk_ops = {
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.is_prepared = raspberrypi_fw_pll_is_on,
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.recalc_rate = raspberrypi_fw_pll_get_rate,
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@@ -173,87 +358,225 @@ static const struct clk_ops raspberrypi_
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.determine_rate = raspberrypi_pll_determine_rate,
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};
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-static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
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+static const struct clk_ops raspberrypi_firmware_pll_divider_clk_ops = {
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+ .is_prepared = raspberrypi_fw_pll_div_is_on,
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+ .recalc_rate = raspberrypi_fw_pll_div_get_rate,
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+ .set_rate = raspberrypi_fw_pll_div_set_rate,
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+ .determine_rate = raspberrypi_pll_div_determine_rate,
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+};
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+
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+static const struct clk_ops raspberrypi_firmware_clk_ops = {
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+ .is_prepared = raspberrypi_fw_clock_is_on,
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+ .recalc_rate = raspberrypi_fw_clock_get_rate,
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+ .set_rate = raspberrypi_fw_clock_set_rate,
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+ .determine_rate = raspberrypi_clock_determine_rate,
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+};
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+
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+
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+static int raspberrypi_get_clock_range(struct raspberrypi_clk *rpi, u32 clock_id, u32 *min_rate, u32 *max_rate)
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{
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- u32 min_rate = 0, max_rate = 0;
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+ int ret;
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+
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+ /* Get min & max rates set by the firmware */
|
||||
+ ret = raspberrypi_clock_property(rpi->firmware,
|
||||
+ RPI_FIRMWARE_GET_MIN_CLOCK_RATE,
|
||||
+ clock_id,
|
||||
+ min_rate);
|
||||
+ if (ret) {
|
||||
+ dev_err(rpi->dev, "Failed to get clock %d min freq: %d (%d)\n",
|
||||
+ clock_id, *min_rate, ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ ret = raspberrypi_clock_property(rpi->firmware,
|
||||
+ RPI_FIRMWARE_GET_MAX_CLOCK_RATE,
|
||||
+ clock_id,
|
||||
+ max_rate);
|
||||
+ if (ret) {
|
||||
+ dev_err(rpi->dev, "Failed to get clock %d max freq: %d (%d)\n",
|
||||
+ clock_id, *max_rate, ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+
|
||||
+static int raspberrypi_register_pll(struct raspberrypi_clk *rpi,
|
||||
+ const struct raspberrypi_pll_data *data)
|
||||
+{
|
||||
+ struct raspberrypi_pll *pll;
|
||||
struct clk_init_data init;
|
||||
int ret;
|
||||
|
||||
memset(&init, 0, sizeof(init));
|
||||
|
||||
/* All of the PLLs derive from the external oscillator. */
|
||||
- init.parent_names = (const char *[]){ "osc" };
|
||||
- init.num_parents = 1;
|
||||
- init.name = "pllb";
|
||||
+ init.parent_names = data->parents;
|
||||
+ init.num_parents = data->num_parents;
|
||||
+ init.name = data->name;
|
||||
init.ops = &raspberrypi_firmware_pll_clk_ops;
|
||||
init.flags = CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED;
|
||||
|
||||
- /* Get min & max rates set by the firmware */
|
||||
- ret = raspberrypi_clock_property(rpi->firmware,
|
||||
- RPI_FIRMWARE_GET_MIN_CLOCK_RATE,
|
||||
- RPI_FIRMWARE_ARM_CLK_ID,
|
||||
- &min_rate);
|
||||
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
|
||||
+ if (!pll)
|
||||
+ return -ENOMEM;
|
||||
+ pll->rpi = rpi;
|
||||
+ pll->data = data;
|
||||
+ pll->hw.init = &init;
|
||||
+
|
||||
+ ret = raspberrypi_get_clock_range(rpi, data->clock_id, &pll->min_rate, &pll->max_rate);
|
||||
if (ret) {
|
||||
- dev_err(rpi->dev, "Failed to get %s min freq: %d\n",
|
||||
- init.name, ret);
|
||||
+ dev_err(rpi->dev, "%s: raspberrypi_get_clock_range(%s) failed: %d\n", __func__, init.name, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
- ret = raspberrypi_clock_property(rpi->firmware,
|
||||
- RPI_FIRMWARE_GET_MAX_CLOCK_RATE,
|
||||
- RPI_FIRMWARE_ARM_CLK_ID,
|
||||
- &max_rate);
|
||||
+ ret = devm_clk_hw_register(rpi->dev, &pll->hw);
|
||||
if (ret) {
|
||||
- dev_err(rpi->dev, "Failed to get %s max freq: %d\n",
|
||||
- init.name, ret);
|
||||
+ dev_err(rpi->dev, "%s: devm_clk_hw_register(%s) failed: %d\n", __func__, init.name, ret);
|
||||
return ret;
|
||||
}
|
||||
+ return 0;
|
||||
+}
|
||||
|
||||
- if (!min_rate || !max_rate) {
|
||||
- dev_err(rpi->dev, "Unexpected frequency range: min %u, max %u\n",
|
||||
- min_rate, max_rate);
|
||||
- return -EINVAL;
|
||||
- }
|
||||
+static int
|
||||
+raspberrypi_register_pll_divider(struct raspberrypi_clk *rpi,
|
||||
+ const struct raspberrypi_pll_divider_data *data)
|
||||
+{
|
||||
+ struct raspberrypi_pll_divider *divider;
|
||||
+ struct clk_init_data init;
|
||||
+ int ret;
|
||||
+
|
||||
+ memset(&init, 0, sizeof(init));
|
||||
+
|
||||
+ init.parent_names = &data->source_pll;
|
||||
+ init.num_parents = 1;
|
||||
+ init.name = data->name;
|
||||
+ init.ops = &raspberrypi_firmware_pll_divider_clk_ops;
|
||||
+ init.flags = data->flags | CLK_IGNORE_UNUSED;
|
||||
|
||||
- dev_info(rpi->dev, "CPU frequency range: min %u, max %u\n",
|
||||
- min_rate, max_rate);
|
||||
+ divider = devm_kzalloc(rpi->dev, sizeof(*divider), GFP_KERNEL);
|
||||
+ if (!divider)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ divider->div.hw.init = &init;
|
||||
+ divider->rpi = rpi;
|
||||
+ divider->data = data;
|
||||
+
|
||||
+ ret = raspberrypi_get_clock_range(rpi, data->clock_id, ÷r->min_rate, ÷r->max_rate);
|
||||
+ if (ret) {
|
||||
+ dev_err(rpi->dev, "%s: raspberrypi_get_clock_range(%s) failed: %d\n", __func__, init.name, ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
|
||||
- rpi->min_rate = min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
|
||||
- rpi->max_rate = max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
|
||||
+ ret = devm_clk_hw_register(rpi->dev, ÷r->div.hw);
|
||||
+ if (ret) {
|
||||
+ dev_err(rpi->dev, "%s: devm_clk_hw_register(%s) failed: %d\n", __func__, init.name, ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
|
||||
- rpi->pllb.init = &init;
|
||||
+ /*
|
||||
+ * PLLH's channels have a fixed divide by 10 afterwards, which
|
||||
+ * is what our consumers are actually using.
|
||||
+ */
|
||||
+ if (data->fixed_divider != 0) {
|
||||
+ struct clk_lookup *lookup;
|
||||
+ struct clk_hw *clk = clk_hw_register_fixed_factor(rpi->dev,
|
||||
+ data->divider_name,
|
||||
+ data->name,
|
||||
+ CLK_SET_RATE_PARENT,
|
||||
+ 1,
|
||||
+ data->fixed_divider);
|
||||
+ if (IS_ERR(clk)) {
|
||||
+ dev_err(rpi->dev, "%s: clk_hw_register_fixed_factor(%s) failed: %ld\n", __func__, init.name, PTR_ERR(clk));
|
||||
+ return PTR_ERR(clk);
|
||||
+ }
|
||||
+ if (data->lookup) {
|
||||
+ lookup = clkdev_hw_create(clk, NULL, data->lookup);
|
||||
+ if (IS_ERR(lookup)) {
|
||||
+ dev_err(rpi->dev, "%s: clk_hw_register_fixed_factor(%s) failed: %ld\n", __func__, init.name, PTR_ERR(lookup));
|
||||
+ return PTR_ERR(lookup);
|
||||
+ }
|
||||
+ }
|
||||
+ }
|
||||
|
||||
- return devm_clk_hw_register(rpi->dev, &rpi->pllb);
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
-static int raspberrypi_register_pllb_arm(struct raspberrypi_clk *rpi)
|
||||
+static int raspberrypi_register_clock(struct raspberrypi_clk *rpi,
|
||||
+ const struct raspberrypi_clock_data *data)
|
||||
{
|
||||
- rpi->pllb_arm = clk_hw_register_fixed_factor(rpi->dev,
|
||||
- "pllb_arm", "pllb",
|
||||
- CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
|
||||
- 1, 2);
|
||||
- if (IS_ERR(rpi->pllb_arm)) {
|
||||
- dev_err(rpi->dev, "Failed to initialize pllb_arm\n");
|
||||
- return PTR_ERR(rpi->pllb_arm);
|
||||
- }
|
||||
+ struct raspberrypi_clock *clock;
|
||||
+ struct clk_init_data init;
|
||||
+ struct clk *clk;
|
||||
+ int ret;
|
||||
+
|
||||
+ memset(&init, 0, sizeof(init));
|
||||
+ init.parent_names = data->parents;
|
||||
+ init.num_parents = data->num_parents;
|
||||
+ init.name = data->name;
|
||||
+ init.flags = data->flags | CLK_IGNORE_UNUSED;
|
||||
|
||||
- rpi->pllb_arm_lookup = clkdev_hw_create(rpi->pllb_arm, NULL, "cpu0");
|
||||
- if (!rpi->pllb_arm_lookup) {
|
||||
- dev_err(rpi->dev, "Failed to initialize pllb_arm_lookup\n");
|
||||
- clk_hw_unregister_fixed_factor(rpi->pllb_arm);
|
||||
+ init.ops = &raspberrypi_firmware_clk_ops;
|
||||
+
|
||||
+ clock = devm_kzalloc(rpi->dev, sizeof(*clock), GFP_KERNEL);
|
||||
+ if (!clock)
|
||||
return -ENOMEM;
|
||||
- }
|
||||
|
||||
+ clock->rpi = rpi;
|
||||
+ clock->data = data;
|
||||
+ clock->hw.init = &init;
|
||||
+
|
||||
+ ret = raspberrypi_get_clock_range(rpi, data->clock_id, &clock->min_rate, &clock->max_rate);
|
||||
+ if (ret) {
|
||||
+ dev_err(rpi->dev, "%s: raspberrypi_get_clock_range(%s) failed: %d\n", __func__, init.name, ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+ clk = devm_clk_register(rpi->dev, &clock->hw);
|
||||
+ if (IS_ERR(clk)) {
|
||||
+ dev_err(rpi->dev, "%s: devm_clk_register(%s) failed: %ld\n", __func__, init.name, PTR_ERR(clk));
|
||||
+ return PTR_ERR(clk);
|
||||
+ }
|
||||
+ ret = clk_register_clkdev(clk, init.name, NULL);
|
||||
+ if (ret) {
|
||||
+ dev_err(rpi->dev, "%s: clk_register_clkdev(%s) failed: %d\n", __func__, init.name, ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
return 0;
|
||||
}
|
||||
|
||||
+
|
||||
+/*
|
||||
+ * the real definition of all the pll, pll_dividers and clocks
|
||||
+ * these make use of the above REGISTER_* macros
|
||||
+ */
|
||||
+static const struct raspberrypi_clk_desc clk_desc_array[] = {
|
||||
+ /* the PLL + PLL dividers */
|
||||
+ [BCM2835_CLOCK_V3D] = REGISTER_CLK(
|
||||
+ SOC_ALL,
|
||||
+ .name = "v3d",
|
||||
+ .parents = (const char *[]){ "osc" },
|
||||
+ .num_parents = 1,
|
||||
+ .clock_id = RPI_FIRMWARE_V3D_CLK_ID),
|
||||
+ [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
|
||||
+ SOC_ALL,
|
||||
+ .name = "pllb",
|
||||
+ .source_pll = "osc",
|
||||
+ .divider_name = "pllb_arm",
|
||||
+ .lookup = "cpu0",
|
||||
+ .fixed_divider = 1,
|
||||
+ .clock_id = RPI_FIRMWARE_ARM_CLK_ID,
|
||||
+ .flags = CLK_SET_RATE_PARENT),
|
||||
+};
|
||||
+
|
||||
static int raspberrypi_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *firmware_node;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct rpi_firmware *firmware;
|
||||
struct raspberrypi_clk *rpi;
|
||||
- int ret;
|
||||
+ const struct raspberrypi_clk_desc *desc;
|
||||
+ const size_t asize = ARRAY_SIZE(clk_desc_array);
|
||||
+ int i;
|
||||
|
||||
firmware_node = of_find_compatible_node(NULL, NULL,
|
||||
"raspberrypi,bcm2835-firmware");
|
||||
@@ -275,16 +598,16 @@ static int raspberrypi_clk_probe(struct
|
||||
rpi->firmware = firmware;
|
||||
platform_set_drvdata(pdev, rpi);
|
||||
|
||||
- ret = raspberrypi_register_pllb(rpi);
|
||||
- if (ret) {
|
||||
- dev_err(dev, "Failed to initialize pllb, %d\n", ret);
|
||||
- return ret;
|
||||
+ for (i = 0; i < asize; i++) {
|
||||
+ desc = &clk_desc_array[i];
|
||||
+ if (desc->clk_register && desc->data /*&&
|
||||
+ (desc->supported & pdata->soc)*/) {
|
||||
+ int ret = desc->clk_register(rpi, desc->data);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+ }
|
||||
}
|
||||
|
||||
- ret = raspberrypi_register_pllb_arm(rpi);
|
||||
- if (ret)
|
||||
- return ret;
|
||||
-
|
||||
rpi->cpufreq = platform_device_register_data(dev, "raspberrypi-cpufreq",
|
||||
-1, NULL, 0);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue