* adds stage1 lzma * new boards * fixes settings for PSC ram * lost of cleanups
SVN-Revision: 25694v19.07.3_mercusys_ac12_duma
John Crispin
13 years ago
parent
cf3b7563cf
commit
54734b3d7d
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@ -0,0 +1,48 @@
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/*
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* (C) Copyright 2010 Industrie Dial Face S.p.A.
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* Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
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*
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* (C) Copyright 2007
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* Vlad Lungu vlad.lungu@windriver.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/mipsregs.h>
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#include <asm/io.h>
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phys_size_t bootstrap_initdram(int board_type)
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{
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/* Sdram is setup by assembler code */
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/* If memory could be changed, we should return the true value here */
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return CONFIG_SYS_MAX_RAM;
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}
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int bootstrap_checkboard(void)
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{
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return 0;
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}
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int bootstrap_misc_init_r(void)
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{
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set_io_port_base(0);
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return 0;
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}
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@ -0,0 +1,583 @@
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/*
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* Memory sub-system initialization code for Danube board.
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* Andre Messerschmidt
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* Copyright (c) 2005 Infineon Technologies AG
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*
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* Based on Inca-IP code
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* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* History:
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peng liu May 25, 2006, for PLL setting after reset, 05252006
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/regdef.h>
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#if defined(CONFIG_USE_DDR_PSC_32)
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#include "ddr_settings_psc_32.h"
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#define DDR166
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#elif defined(CONFIG_USE_DDR_PSC_64)
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#include "ddr_settings_psc_64.h"
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#define DDR166
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#else
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#error "missing definition for RAM"
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#endif
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#define EBU_MODUL_BASE 0xBE105300
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#define EBU_CLC(value) 0x0000(value)
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#define EBU_CON(value) 0x0010(value)
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#define EBU_ADDSEL0(value) 0x0020(value)
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#define EBU_ADDSEL1(value) 0x0024(value)
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#define EBU_ADDSEL2(value) 0x0028(value)
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#define EBU_ADDSEL3(value) 0x002C(value)
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#define EBU_BUSCON0(value) 0x0060(value)
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#define EBU_BUSCON1(value) 0x0064(value)
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#define EBU_BUSCON2(value) 0x0068(value)
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#define EBU_BUSCON3(value) 0x006C(value)
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#define MC_MODUL_BASE 0xBF800000
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#define MC_ERRCAUSE(value) 0x0010(value)
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#define MC_ERRADDR(value) 0x0020(value)
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#define MC_CON(value) 0x0060(value)
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#define MC_SRAM_ENABLE 0x00000004
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#define MC_SDRAM_ENABLE 0x00000002
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#define MC_DDRRAM_ENABLE 0x00000001
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#define MC_SDR_MODUL_BASE 0xBF800200
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#define MC_IOGP(value) 0x0000(value)
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#define MC_CTRLENA(value) 0x0010(value)
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#define MC_MRSCODE(value) 0x0020(value)
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#define MC_CFGDW(value) 0x0030(value)
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#define MC_CFGPB0(value) 0x0040(value)
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#define MC_LATENCY(value) 0x0080(value)
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#define MC_TREFRESH(value) 0x0090(value)
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#define MC_SELFRFSH(value) 0x00A0(value)
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#define MC_DDR_MODUL_BASE 0xBF801000
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#define MC_DC00(value) 0x0000(value)
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#define MC_DC01(value) 0x0010(value)
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#define MC_DC02(value) 0x0020(value)
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#define MC_DC03(value) 0x0030(value)
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#define MC_DC04(value) 0x0040(value)
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#define MC_DC05(value) 0x0050(value)
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#define MC_DC06(value) 0x0060(value)
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#define MC_DC07(value) 0x0070(value)
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#define MC_DC08(value) 0x0080(value)
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#define MC_DC09(value) 0x0090(value)
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#define MC_DC10(value) 0x00A0(value)
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#define MC_DC11(value) 0x00B0(value)
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#define MC_DC12(value) 0x00C0(value)
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#define MC_DC13(value) 0x00D0(value)
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#define MC_DC14(value) 0x00E0(value)
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#define MC_DC15(value) 0x00F0(value)
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#define MC_DC16(value) 0x0100(value)
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#define MC_DC17(value) 0x0110(value)
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#define MC_DC18(value) 0x0120(value)
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#define MC_DC19(value) 0x0130(value)
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#define MC_DC20(value) 0x0140(value)
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#define MC_DC21(value) 0x0150(value)
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#define MC_DC22(value) 0x0160(value)
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#define MC_DC23(value) 0x0170(value)
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#define MC_DC24(value) 0x0180(value)
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#define MC_DC25(value) 0x0190(value)
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#define MC_DC26(value) 0x01A0(value)
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#define MC_DC27(value) 0x01B0(value)
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#define MC_DC28(value) 0x01C0(value)
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#define MC_DC29(value) 0x01D0(value)
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#define MC_DC30(value) 0x01E0(value)
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#define MC_DC31(value) 0x01F0(value)
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#define MC_DC32(value) 0x0200(value)
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#define MC_DC33(value) 0x0210(value)
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#define MC_DC34(value) 0x0220(value)
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#define MC_DC35(value) 0x0230(value)
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#define MC_DC36(value) 0x0240(value)
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#define MC_DC37(value) 0x0250(value)
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#define MC_DC38(value) 0x0260(value)
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#define MC_DC39(value) 0x0270(value)
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#define MC_DC40(value) 0x0280(value)
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#define MC_DC41(value) 0x0290(value)
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#define MC_DC42(value) 0x02A0(value)
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#define MC_DC43(value) 0x02B0(value)
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#define MC_DC44(value) 0x02C0(value)
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#define MC_DC45(value) 0x02D0(value)
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#define MC_DC46(value) 0x02E0(value)
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#define RCU_OFFSET 0xBF203000
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#define RCU_RST_REQ (RCU_OFFSET + 0x0010)
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#define RCU_STS (RCU_OFFSET + 0x0014)
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#define CGU_OFFSET 0xBF103000
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#define PLL0_CFG (CGU_OFFSET + 0x0004)
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#define PLL1_CFG (CGU_OFFSET + 0x0008)
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#define PLL2_CFG (CGU_OFFSET + 0x000C)
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#define CGU_SYS (CGU_OFFSET + 0x0010)
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#define CGU_UPDATE (CGU_OFFSET + 0x0014)
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#define IF_CLK (CGU_OFFSET + 0x0018)
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#define CGU_SMD (CGU_OFFSET + 0x0020)
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#define CGU_CT1SR (CGU_OFFSET + 0x0028)
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#define CGU_CT2SR (CGU_OFFSET + 0x002C)
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#define CGU_PCMCR (CGU_OFFSET + 0x0030)
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#define PCI_CR_PCI (CGU_OFFSET + 0x0034)
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#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
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#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
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#define CLK_MEASURE (CGU_OFFSET + 0x003C)
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//05252006
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#define pll0_35MHz_CONFIG 0x9D861059
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#define pll1_35MHz_CONFIG 0x1A260CD9
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#define pll2_35MHz_CONFIG 0x8000f1e5
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#define pll0_36MHz_CONFIG 0x1000125D
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#define pll1_36MHz_CONFIG 0x1B1E0C99
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#define pll2_36MHz_CONFIG 0x8002f2a1
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//05252006
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//06063001-joelin disable the PCI CFRAME mask -start
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/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
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But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
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The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
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The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
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*/
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#define PCI_CR_PR_OFFSET 0xBE105400
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#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030)
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#define PCI_CONFIG_SPACE 0xB7000000
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#define CS_CFM (PCI_CONFIG_SPACE + 0x6C)
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//06063001-joelin disable the PCI CFRAME mask -end
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.set noreorder
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/*
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* void ebu_init(void)
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*/
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.globl ebu_init
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.ent ebu_init
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ebu_init:
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#if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
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defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
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defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
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defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
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li t1, EBU_MODUL_BASE
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#if defined(CONFIG_EBU_ADDSEL0)
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li t2, CONFIG_EBU_ADDSEL0
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sw t2, EBU_ADDSEL0(t1)
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#endif
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#if defined(CONFIG_EBU_ADDSEL1)
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li t2, CONFIG_EBU_ADDSEL1
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sw t2, EBU_ADDSEL1(t1)
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#endif
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#if defined(CONFIG_EBU_ADDSEL2)
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li t2, CONFIG_EBU_ADDSEL2
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sw t2, EBU_ADDSEL2(t1)
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#endif
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#if defined(CONFIG_EBU_ADDSEL3)
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li t2, CONFIG_EBU_ADDSEL3
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sw t2, EBU_ADDSEL3(t1)
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#endif
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#if defined(CONFIG_EBU_BUSCON0)
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li t2, CONFIG_EBU_BUSCON0
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sw t2, EBU_BUSCON0(t1)
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#endif
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#if defined(CONFIG_EBU_BUSCON1)
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li t2, CONFIG_EBU_BUSCON1
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sw t2, EBU_BUSCON1(t1)
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#endif
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#if defined(CONFIG_EBU_BUSCON2)
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li t2, CONFIG_EBU_BUSCON2
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sw t2, EBU_BUSCON2(t1)
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#endif
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#if defined(CONFIG_EBU_BUSCON3)
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li t2, CONFIG_EBU_BUSCON3
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sw t2, EBU_BUSCON3(t1)
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#endif
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#endif
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j ra
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nop
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.end ebu_init
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/*
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* void cgu_init(long)
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*
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* a0 has the clock value
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*/
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.globl cgu_init
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.ent cgu_init
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cgu_init:
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li t2, CGU_SYS
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lw t2,0(t2)
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beq t2,a0,freq_up2date
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nop
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li t2, RCU_STS
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lw t2, 0(t2)
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and t2,0x00020000
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beq t2,0x00020000,boot_36MHZ
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nop
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//05252006
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li t1, PLL0_CFG
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li t2, pll0_35MHz_CONFIG
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sw t2,0(t1)
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li t1, PLL1_CFG
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li t2, pll1_35MHz_CONFIG
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sw t2,0(t1)
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li t1, PLL2_CFG
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li t2, pll2_35MHz_CONFIG
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sw t2,0(t1)
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li t1, CGU_SYS
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sw a0,0(t1)
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li t1, RCU_RST_REQ
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li t2, 0x40000008
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sw t2,0(t1)
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b wait_reset
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nop
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boot_36MHZ:
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li t1, PLL0_CFG
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li t2, pll0_36MHz_CONFIG
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sw t2,0(t1)
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li t1, PLL1_CFG
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li t2, pll1_36MHz_CONFIG
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sw t2,0(t1)
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li t1, PLL2_CFG
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li t2, pll2_36MHz_CONFIG
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sw t2,0(t1)
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li t1, CGU_SYS
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sw a0,0(t1)
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li t1, RCU_RST_REQ
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li t2, 0x40000008
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sw t2,0(t1)
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//05252006
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wait_reset:
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b wait_reset
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nop
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freq_up2date:
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j ra
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nop
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.end cgu_init
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#ifndef CONFIG_USE_DDR_RAM
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/*
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* void sdram_init(long)
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*
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* a0 has the clock value
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*/
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.globl sdram_init
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.ent sdram_init
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sdram_init:
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/* SDRAM Initialization
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*/
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li t1, MC_MODUL_BASE
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/* Clear Error log registers */
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sw zero, MC_ERRCAUSE(t1)
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sw zero, MC_ERRADDR(t1)
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/* Enable SDRAM module in memory controller */
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li t3, MC_SDRAM_ENABLE
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lw t2, MC_CON(t1)
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or t3, t2, t3
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sw t3, MC_CON(t1)
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li t1, MC_SDR_MODUL_BASE
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/* disable the controller */
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li t2, 0
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sw t2, MC_CTRLENA(t1)
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li t2, 0x822
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sw t2, MC_IOGP(t1)
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li t2, 0x2
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sw t2, MC_CFGDW(t1)
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/* Set CAS Latency */
|
||||
li t2, 0x00000020
|
||||
sw t2, MC_MRSCODE(t1)
|
||||
|
||||
/* Set CS0 to SDRAM parameters */
|
||||
li t2, 0x000014d8
|
||||
sw t2, MC_CFGPB0(t1)
|
||||
|
||||
/* Set SDRAM latency parameters */
|
||||
li t2, 0x00036325; /* BC PC100 */
|
||||
sw t2, MC_LATENCY(t1)
|
||||
|
||||
/* Set SDRAM refresh rate */
|
||||
li t2, 0x00000C30
|
||||
sw t2, MC_TREFRESH(t1)
|
||||
|
||||
/* Clear Power-down registers */
|
||||
sw zero, MC_SELFRFSH(t1)
|
||||
|
||||
/* Finally enable the controller */
|
||||
li t2, 1
|
||||
sw t2, MC_CTRLENA(t1)
|
||||
|
||||
j ra
|
||||
nop
|
||||
|
||||
.end sdram_init
|
||||
|
||||
#endif /* !CONFIG_USE_DDR_RAM */
|
||||
|
||||
#ifdef CONFIG_USE_DDR_RAM
|
||||
/*
|
||||
* void ddrram_init(long)
|
||||
*
|
||||
* a0 has the clock value
|
||||
*/
|
||||
.globl ddrram_init
|
||||
.ent ddrram_init
|
||||
ddrram_init:
|
||||
|
||||
/* DDR-DRAM Initialization
|
||||
*/
|
||||
li t1, MC_MODUL_BASE
|
||||
|
||||
/* Clear Error log registers */
|
||||
sw zero, MC_ERRCAUSE(t1)
|
||||
sw zero, MC_ERRADDR(t1)
|
||||
|
||||
/* Enable DDR module in memory controller */
|
||||
li t3, MC_DDRRAM_ENABLE
|
||||
lw t2, MC_CON(t1)
|
||||
or t3, t2, t3
|
||||
sw t3, MC_CON(t1)
|
||||
|
||||
li t1, MC_DDR_MODUL_BASE
|
||||
|
||||
/* Write configuration to DDR controller registers */
|
||||
li t2, MC_DC0_VALUE
|
||||
sw t2, MC_DC00(t1)
|
||||
|
||||
li t2, MC_DC1_VALUE
|
||||
sw t2, MC_DC01(t1)
|
||||
|
||||
li t2, MC_DC2_VALUE
|
||||
sw t2, MC_DC02(t1)
|
||||
|
||||
li t2, MC_DC3_VALUE
|
||||
sw t2, MC_DC03(t1)
|
||||
|
||||
li t2, MC_DC4_VALUE
|
||||
sw t2, MC_DC04(t1)
|
||||
|
||||
li t2, MC_DC5_VALUE
|
||||
sw t2, MC_DC05(t1)
|
||||
|
||||
li t2, MC_DC6_VALUE
|
||||
sw t2, MC_DC06(t1)
|
||||
|
||||
li t2, MC_DC7_VALUE
|
||||
sw t2, MC_DC07(t1)
|
||||
|
||||
li t2, MC_DC8_VALUE
|
||||
sw t2, MC_DC08(t1)
|
||||
|
||||
li t2, MC_DC9_VALUE
|
||||
sw t2, MC_DC09(t1)
|
||||
|
||||
li t2, MC_DC10_VALUE
|
||||
sw t2, MC_DC10(t1)
|
||||
|
||||
li t2, MC_DC11_VALUE
|
||||
sw t2, MC_DC11(t1)
|
||||
|
||||
li t2, MC_DC12_VALUE
|
||||
sw t2, MC_DC12(t1)
|
||||
|
||||
li t2, MC_DC13_VALUE
|
||||
sw t2, MC_DC13(t1)
|
||||
|
||||
li t2, MC_DC14_VALUE
|
||||
sw t2, MC_DC14(t1)
|
||||
|
||||
li t2, MC_DC15_VALUE
|
||||
sw t2, MC_DC15(t1)
|
||||
|
||||
li t2, MC_DC16_VALUE
|
||||
sw t2, MC_DC16(t1)
|
||||
|
||||
li t2, MC_DC17_VALUE
|
||||
sw t2, MC_DC17(t1)
|
||||
|
||||
li t2, MC_DC18_VALUE
|
||||
sw t2, MC_DC18(t1)
|
||||
|
||||
li t2, MC_DC19_VALUE
|
||||
sw t2, MC_DC19(t1)
|
||||
|
||||
li t2, MC_DC20_VALUE
|
||||
sw t2, MC_DC20(t1)
|
||||
|
||||
li t2, MC_DC21_VALUE
|
||||
sw t2, MC_DC21(t1)
|
||||
|
||||
li t2, MC_DC22_VALUE
|
||||
sw t2, MC_DC22(t1)
|
||||
|
||||
li t2, MC_DC23_VALUE
|
||||
sw t2, MC_DC23(t1)
|
||||
|
||||
li t2, MC_DC24_VALUE
|
||||
sw t2, MC_DC24(t1)
|
||||
|
||||
li t2, MC_DC25_VALUE
|
||||
sw t2, MC_DC25(t1)
|
||||
|
||||
li t2, MC_DC26_VALUE
|
||||
sw t2, MC_DC26(t1)
|
||||
|
||||
li t2, MC_DC27_VALUE
|
||||
sw t2, MC_DC27(t1)
|
||||
|
||||
li t2, MC_DC28_VALUE
|
||||
sw t2, MC_DC28(t1)
|
||||
|
||||
li t2, MC_DC29_VALUE
|
||||
sw t2, MC_DC29(t1)
|
||||
|
||||
li t2, MC_DC30_VALUE
|
||||
sw t2, MC_DC30(t1)
|
||||
|
||||
li t2, MC_DC31_VALUE
|
||||
sw t2, MC_DC31(t1)
|
||||
|
||||
li t2, MC_DC32_VALUE
|
||||
sw t2, MC_DC32(t1)
|
||||
|
||||
li t2, MC_DC33_VALUE
|
||||
sw t2, MC_DC33(t1)
|
||||
|
||||
li t2, MC_DC34_VALUE
|
||||
sw t2, MC_DC34(t1)
|
||||
|
||||
li t2, MC_DC35_VALUE
|
||||
sw t2, MC_DC35(t1)
|
||||
|
||||
li t2, MC_DC36_VALUE
|
||||
sw t2, MC_DC36(t1)
|
||||
|
||||
li t2, MC_DC37_VALUE
|
||||
sw t2, MC_DC37(t1)
|
||||
|
||||
li t2, MC_DC38_VALUE
|
||||
sw t2, MC_DC38(t1)
|
||||
|
||||
li t2, MC_DC39_VALUE
|
||||
sw t2, MC_DC39(t1)
|
||||
|
||||
li t2, MC_DC40_VALUE
|
||||
sw t2, MC_DC40(t1)
|
||||
|
||||
li t2, MC_DC41_VALUE
|
||||
sw t2, MC_DC41(t1)
|
||||
|
||||
li t2, MC_DC42_VALUE
|
||||
sw t2, MC_DC42(t1)
|
||||
|
||||
li t2, MC_DC43_VALUE
|
||||
sw t2, MC_DC43(t1)
|
||||
|
||||
li t2, MC_DC44_VALUE
|
||||
sw t2, MC_DC44(t1)
|
||||
|
||||
li t2, MC_DC45_VALUE
|
||||
sw t2, MC_DC45(t1)
|
||||
|
||||
li t2, MC_DC46_VALUE
|
||||
sw t2, MC_DC46(t1)
|
||||
|
||||
li t2, 0x00000100
|
||||
sw t2, MC_DC03(t1)
|
||||
|
||||
j ra
|
||||
nop
|
||||
|
||||
.end ddrram_init
|
||||
#endif /* CONFIG_USE_DDR_RAM */
|
||||
|
||||
.globl lowlevel_init
|
||||
.ent lowlevel_init
|
||||
lowlevel_init:
|
||||
/* EBU, CGU and SDRAM/DDR-RAM Initialization.
|
||||
*/
|
||||
move t0, ra
|
||||
/* We rely on the fact that non of the following ..._init() functions
|
||||
* modify t0
|
||||
*/
|
||||
#if defined(DDR166)
|
||||
/* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
|
||||
li a0,0xe8
|
||||
#elif defined(DDR133)
|
||||
/* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
|
||||
li a0,0xe9
|
||||
#else /* defined(DDR111) */
|
||||
/* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
|
||||
li a0,0xea
|
||||
#endif
|
||||
bal cgu_init
|
||||
nop
|
||||
|
||||
bal ebu_init
|
||||
nop
|
||||
|
||||
//06063001-joelin disable the PCI CFRAME mask-start
|
||||
#ifdef DISABLE_CFRAME
|
||||
li t1, PCI_CR_PCI //mw bf103034 80000000
|
||||
li t2, 0x80000000
|
||||
sw t2,0(t1)
|
||||
|
||||
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
|
||||
li t2, 0x103
|
||||
sw t2,0(t1)
|
||||
|
||||
li t1, CS_CFM //mw b700006c 0
|
||||
li t2, 0x00
|
||||
sw t2, 0(t1)
|
||||
|
||||
li t1, PCI_CR_PCI_MOD_REG //mw be105430 103
|
||||
li t2, 0x1000103
|
||||
sw t2, 0(t1)
|
||||
#endif
|
||||
//06063001-joelin disable the PCI CFRAME mask-end
|
||||
|
||||
#ifdef CONFIG_USE_DDR_RAM
|
||||
bal ddrram_init
|
||||
nop
|
||||
#else
|
||||
bal sdram_init
|
||||
nop
|
||||
#endif
|
||||
move ra, t0
|
||||
j ra
|
||||
nop
|
||||
|
||||
.end lowlevel_init
|
||||
@ -0,0 +1,74 @@
|
||||
/*
|
||||
* (C) Copyright 2010 Industrie Dial Face S.p.A.
|
||||
* Luigi 'Comio' Mantellini, luigi.mantellini@idf-hit.com
|
||||
*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk Engineering, <wd@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
|
||||
*/
|
||||
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
|
||||
OUTPUT_ARCH(mips)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = .;
|
||||
_gp = ALIGN(16) +0x7ff0;
|
||||
|
||||
.got : {
|
||||
__got_start = .;
|
||||
*(.got)
|
||||
__got_end = .;
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.sdata : { *(.sdata) }
|
||||
|
||||
. = .;
|
||||
. = ALIGN(4);
|
||||
.payload : { *(.payload) }
|
||||
. = ALIGN(4);
|
||||
|
||||
uboot_end_data = .;
|
||||
num_got_entries = (__got_end - __got_start) >> 2;
|
||||
|
||||
. = ALIGN(4);
|
||||
.sbss : { *(.sbss) }
|
||||
.bss : { *(.bss) . = ALIGN(4); }
|
||||
uboot_end = .;
|
||||
}
|
||||
|
||||
@ -0,0 +1,67 @@
|
||||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/ar9.h>
|
||||
|
||||
ulong ifx_get_ddr_hz(void)
|
||||
{
|
||||
switch((*AR9_CGU_SYS) & 0x05) {
|
||||
case 0x01:
|
||||
case 0x05:
|
||||
return CLOCK_111M;
|
||||
|
||||
case 0x00:
|
||||
case 0x04:
|
||||
return CLOCK_166M;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
ulong ifx_get_cpuclk(void)
|
||||
{
|
||||
switch((*AR9_CGU_SYS) & 0x05) {
|
||||
case 0x00:
|
||||
case 0x01:
|
||||
return CLOCK_333M;
|
||||
|
||||
case 0x04:
|
||||
return CLOCK_166M;
|
||||
|
||||
case 0x05:
|
||||
return CLOCK_111M;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
ulong get_bus_freq(ulong dummy)
|
||||
{
|
||||
unsigned int ddr_clock=ifx_get_ddr_hz();
|
||||
if((*AR9_CGU_SYS) & 0x40){
|
||||
return ddr_clock/2;
|
||||
} else {
|
||||
return ddr_clock;
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,65 @@
|
||||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/danube.h>
|
||||
|
||||
ulong ifx_get_ddr_hz(void)
|
||||
{
|
||||
static const ulong ddr_freq[] = {166666667,133333333,111111111,83333333};
|
||||
return ddr_freq[((*DANUBE_CGU_SYS) & 0x3)];
|
||||
}
|
||||
|
||||
ulong ifx_get_cpuclk(void)
|
||||
{
|
||||
#ifdef CONFIG_USE_EMULATOR
|
||||
return EMULATOR_CPU_SPEED;
|
||||
#else //NOT CONFIG_USE_EMULATOR
|
||||
unsigned int ddr_clock=ifx_get_ddr_hz();
|
||||
switch((*DANUBE_CGU_SYS) & 0xc){
|
||||
case 0:
|
||||
default:
|
||||
return 323333333;
|
||||
case 4:
|
||||
return ddr_clock;
|
||||
case 8:
|
||||
return ddr_clock << 1;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
ulong get_bus_freq(ulong dummy)
|
||||
{
|
||||
#ifdef CONFIG_USE_EMULATOR
|
||||
unsigned int clkCPU;
|
||||
clkCPU = ifx_get_cpuclk();
|
||||
return clkCPU >> 2;
|
||||
#else //NOT CONFIG_USE_EMULATOR
|
||||
unsigned int ddr_clock=ifx_get_ddr_hz();
|
||||
if ((*DANUBE_CGU_SYS) & 0x40){
|
||||
return ddr_clock >> 1;
|
||||
}
|
||||
return ddr_clock;
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -0,0 +1,218 @@
|
||||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
* (C) Copyright 2009
|
||||
* Infineon Technologies AG, http://www.infineon.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
#include "ifx_asc.h"
|
||||
|
||||
#define SET_BIT(reg, mask) asc_writel(reg, asc_readl(reg) | (mask))
|
||||
#define CLEAR_BIT(reg, mask) asc_writel(reg, asc_readl(reg) & (~mask))
|
||||
#define SET_BITFIELD(reg, mask, off, val) asc_writel(reg, (asc_readl(reg) & (~mask)) | (val << off) )
|
||||
|
||||
#undef DEBUG_ASC_RAW
|
||||
#ifdef DEBUG_ASC_RAW
|
||||
#define DEBUG_ASC_RAW_RX_BUF 0xA0800000
|
||||
#define DEBUG_ASC_RAW_TX_BUF 0xA0900000
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static IfxAsc_t *pAsc = (IfxAsc_t *)CKSEG1ADDR(CONFIG_SYS_IFX_ASC_BASE);
|
||||
|
||||
/*
|
||||
* FDV fASC
|
||||
* BaudRate = ----- * --------------------
|
||||
* 512 16 * (ReloadValue+1)
|
||||
*/
|
||||
|
||||
/*
|
||||
* FDV fASC
|
||||
* ReloadValue = ( ----- * --------------- ) - 1
|
||||
* 512 16 * BaudRate
|
||||
*/
|
||||
static void serial_divs(u32 baudrate, u32 fasc, u32 *pfdv, u32 *preload)
|
||||
{
|
||||
u32 clock = fasc / 16;
|
||||
|
||||
u32 fdv; /* best fdv */
|
||||
u32 reload = 0; /* best reload */
|
||||
u32 diff; /* smallest diff */
|
||||
u32 idiff; /* current diff */
|
||||
u32 ireload; /* current reload */
|
||||
u32 i; /* current fdv */
|
||||
u32 result; /* current resulting baudrate */
|
||||
|
||||
if (clock > 0x7FFFFF)
|
||||
clock /= 512;
|
||||
else
|
||||
baudrate *= 512;
|
||||
|
||||
fdv = 512; /* start with 1:1 fraction */
|
||||
diff = baudrate; /* highest possible */
|
||||
|
||||
/* i is the test fdv value -- start with the largest possible */
|
||||
for (i = 512; i > 0; i--)
|
||||
{
|
||||
ireload = (clock * i) / baudrate;
|
||||
if (ireload < 1)
|
||||
break; /* already invalid */
|
||||
result = (clock * i) / ireload;
|
||||
|
||||
idiff = (result > baudrate) ? (result - baudrate) : (baudrate - result);
|
||||
if (idiff == 0)
|
||||
{
|
||||
fdv = i;
|
||||
reload = ireload;
|
||||
break; /* can't do better */
|
||||
}
|
||||
else if (idiff < diff)
|
||||
{
|
||||
fdv = i; /* best so far */
|
||||
reload = ireload;
|
||||
diff = idiff; /* update lowest diff*/
|
||||
}
|
||||
}
|
||||
|
||||
*pfdv = (fdv == 512) ? 0 : fdv;
|
||||
*preload = reload - 1;
|
||||
}
|
||||
|
||||
|
||||
void serial_setbrg (void)
|
||||
{
|
||||
u32 ReloadValue, fdv;
|
||||
|
||||
serial_divs(gd->baudrate, get_bus_freq(0), &fdv, &ReloadValue);
|
||||
|
||||
/* Disable Baud Rate Generator; BG should only be written when R=0 */
|
||||
CLEAR_BIT(asc_con, ASCCON_R);
|
||||
|
||||
/* Enable Fractional Divider */
|
||||
SET_BIT(asc_con, ASCCON_FDE); /* FDE = 1 */
|
||||
|
||||
/* Set fractional divider value */
|
||||
asc_writel(asc_fdv, fdv & ASCFDV_VALUE_MASK);
|
||||
|
||||
/* Set reload value in BG */
|
||||
asc_writel(asc_bg, ReloadValue);
|
||||
|
||||
/* Enable Baud Rate Generator */
|
||||
SET_BIT(asc_con, ASCCON_R); /* R = 1 */
|
||||
}
|
||||
|
||||
|
||||
int serial_init (void)
|
||||
{
|
||||
|
||||
/* and we have to set CLC register*/
|
||||
CLEAR_BIT(asc_clc, ASCCLC_DISS);
|
||||
SET_BITFIELD(asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001);
|
||||
|
||||
/* initialy we are in async mode */
|
||||
asc_writel(asc_con, ASCCON_M_8ASYNC);
|
||||
|
||||
/* select input port */
|
||||
asc_writel(asc_pisel, CONSOLE_TTY & 0x1);
|
||||
|
||||
/* TXFIFO's filling level */
|
||||
SET_BITFIELD(asc_txfcon, ASCTXFCON_TXFITLMASK,
|
||||
ASCTXFCON_TXFITLOFF, ASC_TXFIFO_FL);
|
||||
/* enable TXFIFO */
|
||||
SET_BIT(asc_txfcon, ASCTXFCON_TXFEN);
|
||||
|
||||
/* RXFIFO's filling level */
|
||||
SET_BITFIELD(asc_txfcon, ASCRXFCON_RXFITLMASK,
|
||||
ASCRXFCON_RXFITLOFF, ASC_RXFIFO_FL);
|
||||
/* enable RXFIFO */
|
||||
SET_BIT(asc_rxfcon, ASCRXFCON_RXFEN);
|
||||
|
||||
/* set baud rate */
|
||||
serial_setbrg();
|
||||
|
||||
/* enable error signals & Receiver enable */
|
||||
SET_BIT(asc_whbstate, ASCWHBSTATE_SETREN|ASCCON_FEN|ASCCON_TOEN|ASCCON_ROEN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void serial_putc (const char c)
|
||||
{
|
||||
u32 txFl = 0;
|
||||
#ifdef DEBUG_ASC_RAW
|
||||
static u8 * debug = (u8 *) DEBUG_ASC_RAW_TX_BUF;
|
||||
*debug++=c;
|
||||
#endif
|
||||
if (c == '\n')
|
||||
serial_putc ('\r');
|
||||
/* check do we have a free space in the TX FIFO */
|
||||
/* get current filling level */
|
||||
do {
|
||||
txFl = ( asc_readl(asc_fstat) & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF;
|
||||
}
|
||||
while ( txFl == ASC_TXFIFO_FULL );
|
||||
|
||||
asc_writel(asc_tbuf, c); /* write char to Transmit Buffer Register */
|
||||
|
||||
/* check for errors */
|
||||
if ( asc_readl(asc_state) & ASCSTATE_TOE ) {
|
||||
SET_BIT(asc_whbstate, ASCWHBSTATE_CLRTOE);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
void serial_puts (const char *s)
|
||||
{
|
||||
while (*s) {
|
||||
serial_putc (*s++);
|
||||
}
|
||||
}
|
||||
|
||||
int serial_getc (void)
|
||||
{
|
||||
char c;
|
||||
while ((asc_readl(asc_fstat) & ASCFSTAT_RXFFLMASK) == 0 );
|
||||
c = (char)(asc_readl(asc_rbuf) & 0xff);
|
||||
|
||||
#ifdef DEBUG_ASC_RAW
|
||||
static u8* debug=(u8*)(DEBUG_ASC_RAW_RX_BUF);
|
||||
*debug++=c;
|
||||
#endif
|
||||
return c;
|
||||
}
|
||||
|
||||
|
||||
int serial_tstc (void)
|
||||
{
|
||||
int res = 1;
|
||||
|
||||
if ( (asc_readl(asc_fstat) & ASCFSTAT_RXFFLMASK) == 0 ) {
|
||||
res = 0;
|
||||
}
|
||||
return res;
|
||||
}
|
||||
@ -0,0 +1,199 @@
|
||||
/*****************************************************************************
|
||||
* DANUBE BootROM
|
||||
* Copyright (c) 2005, Infineon Technologies AG, All rights reserved
|
||||
* IFAP DC COM SD
|
||||
*****************************************************************************/
|
||||
#ifndef __ASC_H
|
||||
#define __ASC_H
|
||||
|
||||
/* channel operating modes */
|
||||
#define ASCOPT_CSIZE 0x00000003
|
||||
#define ASCOPT_CS7 0x00000001
|
||||
#define ASCOPT_CS8 0x00000002
|
||||
#define ASCOPT_PARENB 0x00000004
|
||||
#define ASCOPT_STOPB 0x00000008
|
||||
#define ASCOPT_PARODD 0x00000010
|
||||
#define ASCOPT_CREAD 0x00000020
|
||||
|
||||
#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
|
||||
|
||||
/* ASC input select (0 or 1) */
|
||||
#define CONSOLE_TTY 0
|
||||
|
||||
#define ASC_TXFIFO_FL 1
|
||||
#define ASC_RXFIFO_FL 1
|
||||
#define ASC_TXFIFO_FULL 16
|
||||
|
||||
/* CLC register's bits and bitfields */
|
||||
#define ASCCLC_DISR 0x00000001
|
||||
#define ASCCLC_DISS 0x00000002
|
||||
#define ASCCLC_RMCMASK 0x0000FF00
|
||||
#define ASCCLC_RMCOFFSET 8
|
||||
|
||||
/* CON register's bits and bitfields */
|
||||
#define ASCCON_MODEMASK 0x0000000f
|
||||
#define ASCCON_M_8ASYNC 0x0
|
||||
#define ASCCON_M_8IRDA 0x1
|
||||
#define ASCCON_M_7ASYNC 0x2
|
||||
#define ASCCON_M_7IRDA 0x3
|
||||
#define ASCCON_WLSMASK 0x0000000c
|
||||
#define ASCCON_WLSOFFSET 2
|
||||
#define ASCCON_WLS_8BIT 0x0
|
||||
#define ASCCON_WLS_7BIT 0x1
|
||||
#define ASCCON_PEN 0x00000010
|
||||
#define ASCCON_ODD 0x00000020
|
||||
#define ASCCON_SP 0x00000040
|
||||
#define ASCCON_STP 0x00000080
|
||||
#define ASCCON_BRS 0x00000100
|
||||
#define ASCCON_FDE 0x00000200
|
||||
#define ASCCON_ERRCLK 0x00000400
|
||||
#define ASCCON_EMMASK 0x00001800
|
||||
#define ASCCON_EMOFFSET 11
|
||||
#define ASCCON_EM_ECHO_OFF 0x0
|
||||
#define ASCCON_EM_ECHO_AB 0x1
|
||||
#define ASCCON_EM_ECHO_ON 0x2
|
||||
#define ASCCON_LB 0x00002000
|
||||
#define ASCCON_ACO 0x00004000
|
||||
#define ASCCON_R 0x00008000
|
||||
#define ASCCON_PAL 0x00010000
|
||||
#define ASCCON_FEN 0x00020000
|
||||
#define ASCCON_RUEN 0x00040000
|
||||
#define ASCCON_ROEN 0x00080000
|
||||
#define ASCCON_TOEN 0x00100000
|
||||
#define ASCCON_BEN 0x00200000
|
||||
#define ASCCON_TXINV 0x01000000
|
||||
#define ASCCON_RXINV 0x02000000
|
||||
#define ASCCON_TXMSB 0x04000000
|
||||
#define ASCCON_RXMSB 0x08000000
|
||||
|
||||
/* STATE register's bits and bitfields */
|
||||
#define ASCSTATE_REN 0x00000001
|
||||
#define ASCSTATE_PE 0x00010000
|
||||
#define ASCSTATE_FE 0x00020000
|
||||
#define ASCSTATE_RUE 0x00040000
|
||||
#define ASCSTATE_ROE 0x00080000
|
||||
#define ASCSTATE_TOE 0x00100000
|
||||
#define ASCSTATE_BE 0x00200000
|
||||
#define ASCSTATE_TXBVMASK 0x07000000
|
||||
#define ASCSTATE_TXBVOFFSET 24
|
||||
#define ASCSTATE_TXEOM 0x08000000
|
||||
#define ASCSTATE_RXBVMASK 0x70000000
|
||||
#define ASCSTATE_RXBVOFFSET 28
|
||||
#define ASCSTATE_RXEOM 0x80000000
|
||||
|
||||
/* WHBSTATE register's bits and bitfields */
|
||||
#define ASCWHBSTATE_CLRREN 0x00000001
|
||||
#define ASCWHBSTATE_SETREN 0x00000002
|
||||
#define ASCWHBSTATE_CLRPE 0x00000004
|
||||
#define ASCWHBSTATE_CLRFE 0x00000008
|
||||
#define ASCWHBSTATE_CLRRUE 0x00000010
|
||||
#define ASCWHBSTATE_CLRROE 0x00000020
|
||||
#define ASCWHBSTATE_CLRTOE 0x00000040
|
||||
#define ASCWHBSTATE_CLRBE 0x00000080
|
||||
#define ASCWHBSTATE_SETPE 0x00000100
|
||||
#define ASCWHBSTATE_SETFE 0x00000200
|
||||
#define ASCWHBSTATE_SETRUE 0x00000400
|
||||
#define ASCWHBSTATE_SETROE 0x00000800
|
||||
#define ASCWHBSTATE_SETTOE 0x00001000
|
||||
#define ASCWHBSTATE_SETBE 0x00002000
|
||||
|
||||
/* ABCON register's bits and bitfields */
|
||||
#define ASCABCON_ABEN 0x0001
|
||||
#define ASCABCON_AUREN 0x0002
|
||||
#define ASCABCON_ABSTEN 0x0004
|
||||
#define ASCABCON_ABDETEN 0x0008
|
||||
#define ASCABCON_FCDETEN 0x0010
|
||||
|
||||
/* FDV register mask, offset and bitfields*/
|
||||
#define ASCFDV_VALUE_MASK 0x000001FF
|
||||
|
||||
/* WHBABCON register's bits and bitfields */
|
||||
#define ASCWHBABCON_CLRABEN 0x0001
|
||||
#define ASCWHBABCON_SETABEN 0x0002
|
||||
|
||||
/* ABSTAT register's bits and bitfields */
|
||||
#define ASCABSTAT_FCSDET 0x0001
|
||||
#define ASCABSTAT_FCCDET 0x0002
|
||||
#define ASCABSTAT_SCSDET 0x0004
|
||||
#define ASCABSTAT_SCCDET 0x0008
|
||||
#define ASCABSTAT_DETWAIT 0x0010
|
||||
|
||||
/* WHBABSTAT register's bits and bitfields */
|
||||
#define ASCWHBABSTAT_CLRFCSDET 0x0001
|
||||
#define ASCWHBABSTAT_SETFCSDET 0x0002
|
||||
#define ASCWHBABSTAT_CLRFCCDET 0x0004
|
||||
#define ASCWHBABSTAT_SETFCCDET 0x0008
|
||||
#define ASCWHBABSTAT_CLRSCSDET 0x0010
|
||||
#define ASCWHBABSTAT_SETSCSDET 0x0020
|
||||
#define ASCWHBABSTAT_CLRSCCDET 0x0040
|
||||
#define ASCWHBABSTAT_SETSCCDET 0x0080
|
||||
#define ASCWHBABSTAT_CLRDETWAIT 0x0100
|
||||
#define ASCWHBABSTAT_SETDETWAIT 0x0200
|
||||
|
||||
/* TXFCON register's bits and bitfields */
|
||||
#define ASCTXFCON_TXFIFO1 0x00000400
|
||||
#define ASCTXFCON_TXFEN 0x0001
|
||||
#define ASCTXFCON_TXFFLU 0x0002
|
||||
#define ASCTXFCON_TXFITLMASK 0x3F00
|
||||
#define ASCTXFCON_TXFITLOFF 8
|
||||
|
||||
/* RXFCON register's bits and bitfields */
|
||||
#define ASCRXFCON_RXFIFO1 0x00000400
|
||||
#define ASCRXFCON_RXFEN 0x0001
|
||||
#define ASCRXFCON_RXFFLU 0x0002
|
||||
#define ASCRXFCON_RXFITLMASK 0x3F00
|
||||
#define ASCRXFCON_RXFITLOFF 8
|
||||
|
||||
/* FSTAT register's bits and bitfields */
|
||||
#define ASCFSTAT_RXFFLMASK 0x003F
|
||||
#define ASCFSTAT_TXFFLMASK 0x3F00
|
||||
#define ASCFSTAT_TXFFLOFF 8
|
||||
|
||||
typedef struct IfxAsc_s
|
||||
{
|
||||
unsigned long asc_clc; /*0x0000*/
|
||||
unsigned long asc_pisel; /*0x0004*/
|
||||
unsigned long asc_id; /*0x0008*/
|
||||
unsigned long asc_rsvd1[1]; /* for mapping */ /*0x000C*/
|
||||
unsigned long asc_con; /*0x0010*/
|
||||
unsigned long asc_state; /*0x0014*/
|
||||
unsigned long asc_whbstate; /*0x0018*/
|
||||
unsigned long asc_rsvd2[1]; /* for mapping */ /*0x001C*/
|
||||
unsigned long asc_tbuf; /*0x0020*/
|
||||
unsigned long asc_rbuf; /*0x0024*/
|
||||
unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0028*/
|
||||
unsigned long asc_abcon; /*0x0030*/
|
||||
unsigned long asc_abstat; /* not used */ /*0x0034*/
|
||||
unsigned long asc_whbabcon; /*0x0038*/
|
||||
unsigned long asc_whbabstat; /* not used */ /*0x003C*/
|
||||
unsigned long asc_rxfcon; /*0x0040*/
|
||||
unsigned long asc_txfcon; /*0x0044*/
|
||||
unsigned long asc_fstat; /*0x0048*/
|
||||
unsigned long asc_rsvd4[1]; /* for mapping */ /*0x004C*/
|
||||
unsigned long asc_bg; /*0x0050*/
|
||||
unsigned long asc_bg_timer; /*0x0054*/
|
||||
unsigned long asc_fdv; /*0x0058*/
|
||||
unsigned long asc_pmw; /*0x005C*/
|
||||
unsigned long asc_modcon; /*0x0060*/
|
||||
unsigned long asc_modstat; /*0x0064*/
|
||||
unsigned long asc_rsvd5[2]; /* for mapping */ /*0x0068*/
|
||||
unsigned long asc_sfcc; /*0x0070*/
|
||||
unsigned long asc_rsvd6[3]; /* for mapping */ /*0x0074*/
|
||||
unsigned long asc_eomcon; /*0x0080*/
|
||||
unsigned long asc_rsvd7[26]; /* for mapping */ /*0x0084*/
|
||||
unsigned long asc_dmacon; /*0x00EC*/
|
||||
unsigned long asc_rsvd8[1]; /* for mapping */ /*0x00F0*/
|
||||
unsigned long asc_irnen; /*0x00F4*/
|
||||
unsigned long asc_irnicr; /*0x00F8*/
|
||||
unsigned long asc_irncr; /*0x00FC*/
|
||||
} IfxAsc_t;
|
||||
|
||||
|
||||
/* Register access macros */
|
||||
#define asc_readl(reg) \
|
||||
readl(&pAsc->reg)
|
||||
#define asc_writel(reg,value) \
|
||||
writel((value), &pAsc->reg)
|
||||
|
||||
|
||||
#endif /* __ASC_H */
|
||||
@ -0,0 +1,17 @@
|
||||
#ifndef __CONFIG_H_3527
|
||||
#define __CONFIG_H_3527
|
||||
|
||||
#define CONFIG_ARV3527 1
|
||||
#define CONFIG_ARCADYAN "ARV3527P"
|
||||
|
||||
#define CONFIG_SYS_MAX_RAM 32*1024*1024
|
||||
#define CONFIG_USE_DDR_PSC_32 1
|
||||
#define CONFIG_SYS_PROMPT "ARV3527 => "
|
||||
|
||||
/*#define CONFIG_BUTTON_PORT1
|
||||
#define CONFIG_BUTTON_PIN 13
|
||||
#define CONFIG_BUTTON_LEVEL 0
|
||||
*/
|
||||
#include "arcadyan-common.h"
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,20 @@
|
||||
#ifndef __CONFIG_H_4520
|
||||
#define __CONFIG_H_4520
|
||||
|
||||
#define CONFIG_ARV4520 1
|
||||
#define CONFIG_ARCADYAN "ARV4520PW"
|
||||
|
||||
#define CONFIG_SYS_MAX_RAM 32*1024*1024
|
||||
#define CONFIG_USE_DDR_PSC_32 1
|
||||
#define CONFIG_SYS_PROMPT "ARV4520 => "
|
||||
#define CONFIG_RMII 1
|
||||
#define CONFIG_ADM6996_SWITCH 1
|
||||
#define CONFIG_EBU_GPIO 0x400
|
||||
|
||||
#define CONFIG_BUTTON_PORT0
|
||||
#define CONFIG_BUTTON_PIN 11
|
||||
#define CONFIG_BUTTON_LEVEL 0
|
||||
|
||||
#include "arcadyan-common.h"
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,18 @@
|
||||
#ifndef __CONFIG_H_4525
|
||||
#define __CONFIG_H_4525
|
||||
|
||||
#define CONFIG_ARV4525 1
|
||||
#define CONFIG_ARCADYAN "ARV4525PW"
|
||||
|
||||
#define CONFIG_SYS_MAX_RAM 32*1024*1024
|
||||
#define CONFIG_USE_DDR_PSC_32 1
|
||||
#define CONFIG_SYS_PROMPT "ARV4525 => "
|
||||
|
||||
#define CONFIG_BUTTON_PORT1
|
||||
#define CONFIG_BUTTON_PIN 13
|
||||
#define CONFIG_BUTTON_LEVEL 0
|
||||
|
||||
|
||||
#include "arcadyan-common.h"
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue