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@ -617,9 +617,6 @@ r6040_close(struct net_device *dev)
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return 0;
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return 0;
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}
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}
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#define DMZ_GPIO 1
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#define RDC3210_CFGREG_ADDR 0x0CF8
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#define RDC3210_CFGREG_DATA 0x0CFC
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static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
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static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
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{
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{
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struct r6040_private *lp = dev->priv;
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struct r6040_private *lp = dev->priv;
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@ -641,25 +638,6 @@ static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
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if(args[0]&(1<<27))phy_write(ioaddr,29,20,(phy_read(ioaddr,29,20)|0x2000)); /* port 2 */
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if(args[0]&(1<<27))phy_write(ioaddr,29,20,(phy_read(ioaddr,29,20)|0x2000)); /* port 2 */
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if(args[0]&(1<<25))phy_write(ioaddr,29,20,(phy_read(ioaddr,29,20)|0x0020)); /* port 3 */
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if(args[0]&(1<<25))phy_write(ioaddr,29,20,(phy_read(ioaddr,29,20)|0x0020)); /* port 3 */
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/* DMZ LED */
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val = 0x80000000 | (7 << 11) | ((0x48));
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outl(val, RDC3210_CFGREG_ADDR);
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udelay(10);
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val = inl(RDC3210_CFGREG_DATA);
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val |= (0x1 << DMZ_GPIO);
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outl(val, RDC3210_CFGREG_DATA);
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udelay(10);
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val = 0x80000000 | (7 << 11) | ((0x4C));
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outl(val, RDC3210_CFGREG_ADDR);
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udelay(10);
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val = inl(RDC3210_CFGREG_DATA);
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if(args[0]&(1<<23)) /* DMZ enabled */
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val &= ~(0x1 << DMZ_GPIO); /* low activated */
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else val |= (0x1 << DMZ_GPIO);
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outl(val, RDC3210_CFGREG_DATA);
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udelay(10);
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}
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}
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return 0;
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return 0;
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}
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}
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