brcm63xx: update irq affinity code to latest version
Reduces code size a bit and sets affinity to boot cpu by default. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 41591v19.07.3_mercusys_ac12_duma
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From 653dcc09407a695efb203337c6f72515d4c4ee43 Mon Sep 17 00:00:00 2001
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From a2015bfad293a7eb79519beb60381cb996c6e298 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Thu, 21 Mar 2013 17:05:15 +0100
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Subject: [PATCH 29/53] MIPS: BCM63XX: rename __dispatch_internal to
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__dispatch_internal_32
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Subject: [PATCH 01/10] MIPS: BCM63XX: add width to __dispatch_internal
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Make it follow the same naming convention as the other functions.
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From 1003fb4a5ee9fcff518f20eefdee1a9bf500af7e Mon Sep 17 00:00:00 2001
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From 96ce0a9d195b2781d6f8d919dea8056b1c409703 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Thu, 25 Apr 2013 00:24:06 +0200
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Subject: [PATCH 32/53] MIPS: BCM63XX: append irq line number to
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irq_{stat,mask}*
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Subject: [PATCH 04/10] MIPS: BCM63XX: append irq line to irq_{stat,mask}*
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The SMP capable irq controllers have two interupt output pins which are
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The SMP capable irq controllers have two interrupt output pins which are
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controlled through separate registers, so make the variables arrays.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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@ -1,8 +1,7 @@
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From 653dcc09407a695efb203337c6f72515d4c4ee43 Mon Sep 17 00:00:00 2001
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From a2015bfad293a7eb79519beb60381cb996c6e298 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Thu, 21 Mar 2013 17:05:15 +0100
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Subject: [PATCH 29/53] MIPS: BCM63XX: rename __dispatch_internal to
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__dispatch_internal_32
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Subject: [PATCH 01/10] MIPS: BCM63XX: add width to __dispatch_internal
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Make it follow the same naming convention as the other functions.
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@ -1,10 +1,9 @@
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From 1003fb4a5ee9fcff518f20eefdee1a9bf500af7e Mon Sep 17 00:00:00 2001
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From 96ce0a9d195b2781d6f8d919dea8056b1c409703 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Thu, 25 Apr 2013 00:24:06 +0200
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Subject: [PATCH 32/53] MIPS: BCM63XX: append irq line number to
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irq_{stat,mask}*
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Subject: [PATCH 04/10] MIPS: BCM63XX: append irq line to irq_{stat,mask}*
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The SMP capable irq controllers have two interupt output pins which are
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The SMP capable irq controllers have two interrupt output pins which are
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controlled through separate registers, so make the variables arrays.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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