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@ -33,6 +33,7 @@
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#define RT2880_SDRAM_BASE 0x08000000
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#define RT2880_SDRAM_BASE 0x08000000
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#define RT2880_SYSC_SIZE 0x100
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#define RT2880_SYSC_SIZE 0x100
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#define RT2880_TIMER_SIZE 0x100
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#define RT2880_INTC_SIZE 0x100
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#define RT2880_INTC_SIZE 0x100
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#define RT2880_MEMC_SIZE 0x100
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#define RT2880_MEMC_SIZE 0x100
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#define RT2880_UART0_SIZE 0x100
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#define RT2880_UART0_SIZE 0x100
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@ -45,6 +46,7 @@
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#define SYSC_REG_CHIP_NAME1 0x004 /* Chip Name 1 */
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#define SYSC_REG_CHIP_NAME1 0x004 /* Chip Name 1 */
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#define SYSC_REG_CHIP_ID 0x00c /* Chip Identification */
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#define SYSC_REG_CHIP_ID 0x00c /* Chip Identification */
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#define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */
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#define SYSC_REG_SYSTEM_CONFIG 0x010 /* System Configuration */
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#define SYSC_REG_CLKCFG 0x030
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#define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/
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#define SYSC_REG_RESET_CTRL 0x034 /* Reset Control*/
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#define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/
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#define SYSC_REG_RESET_STATUS 0x038 /* Reset Status*/
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#define SYSC_REG_GPIO_MODE 0x060 /* GPIO Purpose Select */
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#define SYSC_REG_GPIO_MODE 0x060 /* GPIO Purpose Select */
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@ -62,6 +64,8 @@
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#define SYSTEM_CONFIG_CPUCLK_280 0x2
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#define SYSTEM_CONFIG_CPUCLK_280 0x2
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#define SYSTEM_CONFIG_CPUCLK_300 0x3
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#define SYSTEM_CONFIG_CPUCLK_300 0x3
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#define CLKCFG_SRAM_CS_N_WDT BIT(9)
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#define RT2880_RESET_SYSTEM BIT(0)
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#define RT2880_RESET_SYSTEM BIT(0)
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#define RT2880_RESET_TIMER BIT(1)
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#define RT2880_RESET_TIMER BIT(1)
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#define RT2880_RESET_INTC BIT(2)
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#define RT2880_RESET_INTC BIT(2)
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