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113 lines
2.8 KiB
Diff
113 lines
2.8 KiB
Diff
From 19fc79333af0d3733d4987bc1e554ae7e8a8cb0d Mon Sep 17 00:00:00 2001
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From: Sean Wang <sean.wang@mediatek.com>
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Date: Thu, 28 Dec 2017 16:26:10 +0800
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Subject: [PATCH 214/224] arm64: dts: mt7622: add cpufreq related device nodes
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Add clocks, regulators and opp information into cpu nodes.
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In addition, the power supply for cpu nodes is deployed on
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mt7622-rfb1 board.
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Signed-off-by: Sean Wang <sean.wang@mediatek.com>
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Cc: Viresh Kumar <viresh.kumar@linaro.org>
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---
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arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 12 +++++++
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arch/arm64/boot/dts/mediatek/mt7622.dtsi | 52 ++++++++++++++++++++++++++++
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2 files changed, 64 insertions(+)
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--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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@@ -20,6 +20,18 @@
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bootargs = "console=ttyS0,115200n1";
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};
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+ cpus {
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+ cpu@0 {
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+ proc-supply = <&mt6380_vcpu_reg>;
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+ sram-supply = <&mt6380_vm_reg>;
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+ };
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+
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+ cpu@1 {
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+ proc-supply = <&mt6380_vcpu_reg>;
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+ sram-supply = <&mt6380_vm_reg>;
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+ };
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+ };
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+
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gpio-keys {
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compatible = "gpio-keys-polled";
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poll-interval = <100>;
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -18,6 +18,50 @@
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#address-cells = <2>;
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#size-cells = <2>;
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+ cpu_opp_table: opp-table {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+ opp-300000000 {
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+ opp-hz = /bits/ 64 <30000000>;
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+ opp-microvolt = <950000>;
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+ };
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+
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+ opp-437500000 {
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+ opp-hz = /bits/ 64 <437500000>;
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+ opp-microvolt = <1000000>;
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+ };
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+
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+ opp-600000000 {
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+ opp-hz = /bits/ 64 <600000000>;
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+ opp-microvolt = <1050000>;
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+ };
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+
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+ opp-812500000 {
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+ opp-hz = /bits/ 64 <812500000>;
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+ opp-microvolt = <1100000>;
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+ };
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+
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+ opp-1025000000 {
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+ opp-hz = /bits/ 64 <1025000000>;
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+ opp-microvolt = <1150000>;
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+ };
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+
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+ opp-1137500000 {
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+ opp-hz = /bits/ 64 <1137500000>;
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+ opp-microvolt = <1200000>;
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+ };
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+
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+ opp-1262500000 {
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+ opp-hz = /bits/ 64 <1262500000>;
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+ opp-microvolt = <1250000>;
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+ };
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+
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+ opp-1350000000 {
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+ opp-hz = /bits/ 64 <1350000000>;
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+ opp-microvolt = <1310000>;
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+ };
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+ };
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+
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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@@ -26,6 +70,10 @@
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x0>;
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+ clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
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+ <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
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+ clock-names = "cpu", "intermediate";
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+ operating-points-v2 = <&cpu_opp_table>;
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enable-method = "psci";
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clock-frequency = <1300000000>;
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};
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@@ -34,6 +82,10 @@
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x1>;
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+ clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
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+ <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
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+ clock-names = "cpu", "intermediate";
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+ operating-points-v2 = <&cpu_opp_table>;
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enable-method = "psci";
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clock-frequency = <1300000000>;
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};
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