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78 lines
2.8 KiB
Diff
78 lines
2.8 KiB
Diff
From patchwork Fri Jul 13 11:32:42 2018
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: serial8250 on tegra hsuart: recover from spurious interrupts due to
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tegra2 silicon bug
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X-Patchwork-Submitter: "David R. Piegdon" <lkml@p23q.org>
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X-Patchwork-Id: 943440
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Message-Id: <4676ea34-69ce-5422-1ded-94218b89f7d9@p23q.org>
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To: linux-tegra@vger.kernel.org
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Date: Fri, 13 Jul 2018 11:32:42 +0000
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From: "David R. Piegdon" <lkml@p23q.org>
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List-Id: <linux-tegra.vger.kernel.org>
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Hi,
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a while back I sent a few mails regarding spurious interrupts in the
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UARTA (hsuart) block of the Tegra2 SoC, when using the 8250 driver for
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it instead of the hsuart driver. After going down a pretty deep
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debugging/testing hole, I think I found a patch that fixes the issue. So
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far testing in a reboot-cycle suggests that the error frequency dropped
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from >3% of all reboots to at least <0.05% of all reboots. Tests
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continue to run over the weekend.
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The patch below already is a second iteration; the first did not reset
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the MCR or contain the lines below '// clear interrupts'. This resulted
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in no more spurious interrupts, but in a few % of spurious interrupts
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that were recovered the UART block did not receive any characters any
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more. So further resetting was required to fully reacquire operational
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state of the UART block.
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I'd love any comments/suggestions on this!
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Cheers,
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David
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--- a/drivers/tty/serial/8250/8250_core.c
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+++ b/drivers/tty/serial/8250/8250_core.c
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@@ -136,6 +136,38 @@ static irqreturn_t serial8250_interrupt(
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"serial8250: too much work for irq%d\n", irq);
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break;
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}
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+
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+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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+ if (!handled && (port->type == PORT_TEGRA)) {
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+ /*
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+ * Fix Tegra 2 CPU silicon bug where sometimes
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+ * "TX holding register empty" interrupts result in a
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+ * bad (metastable?) state in Tegras HSUART IP core.
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+ * Only way to recover seems to be to reset all
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+ * interrupts as well as the TX queue and the MCR.
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+ * But we don't want to loose any outgoing characters,
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+ * so only do it if the RX and TX queues are empty.
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+ */
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+ unsigned char lsr = port->serial_in(port, UART_LSR);
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+ const unsigned char fifo_empty_mask =
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+ (UART_LSR_TEMT | UART_LSR_THRE);
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+ if (((lsr & (UART_LSR_DR | fifo_empty_mask)) ==
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+ fifo_empty_mask)) {
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+ port->serial_out(port, UART_IER, 0);
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+ port->serial_out(port, UART_MCR, 0);
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+ serial8250_clear_and_reinit_fifos(up);
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+ port->serial_out(port, UART_MCR, up->mcr);
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+ port->serial_out(port, UART_IER, up->ier);
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+ // clear interrupts
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+ serial_port_in(port, UART_LSR);
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+ serial_port_in(port, UART_RX);
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+ serial_port_in(port, UART_IIR);
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+ serial_port_in(port, UART_MSR);
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+ up->lsr_saved_flags = 0;
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+ up->msr_saved_flags = 0;
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+ }
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+ }
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+#endif
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} while (l != end);
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spin_unlock(&i->lock);
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