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75 lines
2.8 KiB
Diff
75 lines
2.8 KiB
Diff
From 550fabd71d7fcdfe099bbf41e00e28719737161e Mon Sep 17 00:00:00 2001
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From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Date: Tue, 10 Mar 2020 12:34:59 +0100
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Subject: [PATCH] staging: mt7621-pci: enable clock bit for each port
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The clock related code concerns me from the very beginning because
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there are some set ups got from legacy driver that are not documented
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anywhere. According to the programming guide 0x7c is 'CPE_ROSC_SEL1'
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register and 0x80 is 'CPU_CPE_CN'. I do think this set up is not needed
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at all and the proper thing to do is just enable the clock bit for each
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pcie port. Hence remove useless code and do the right thing which is
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setting up the clock bit for each port enabled.
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Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Link: https://lore.kernel.org/r/20200310113459.30539-1-sergio.paracuellos@gmail.com
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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drivers/staging/mt7621-pci/pci-mt7621.c | 17 ++++++-----------
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1 file changed, 6 insertions(+), 11 deletions(-)
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--- a/drivers/staging/mt7621-pci/pci-mt7621.c
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+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
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@@ -45,8 +45,6 @@
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/* rt_sysc_membase relative registers */
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#define RALINK_CLKCFG1 0x30
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-#define RALINK_PCIE_CLK_GEN 0x7c
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-#define RALINK_PCIE_CLK_GEN1 0x80
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/* Host-PCI bridge registers */
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#define RALINK_PCI_PCICFG_ADDR 0x0000
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@@ -85,10 +83,6 @@
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#define PCIE_PORT_CLK_EN(x) BIT(24 + (x))
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#define PCIE_PORT_LINKUP BIT(0)
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-#define PCIE_CLK_GEN_EN BIT(31)
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-#define PCIE_CLK_GEN_DIS 0
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-#define PCIE_CLK_GEN1_DIS GENMASK(30, 24)
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-#define PCIE_CLK_GEN1_EN (BIT(27) | BIT(25))
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#define MEMORY_BASE 0x0
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#define PERST_MODE_MASK GENMASK(11, 10)
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#define PERST_MODE_GPIO BIT(10)
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@@ -233,6 +227,11 @@ static inline bool mt7621_pcie_port_is_l
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return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;
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}
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+static inline void mt7621_pcie_port_clk_enable(struct mt7621_pcie_port *port)
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+{
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+ rt_sysc_m32(0, PCIE_PORT_CLK_EN(port->slot), RALINK_CLKCFG1);
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+}
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+
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static inline void mt7621_pcie_port_clk_disable(struct mt7621_pcie_port *port)
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{
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rt_sysc_m32(PCIE_PORT_CLK_EN(port->slot), 0, RALINK_CLKCFG1);
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@@ -501,11 +500,6 @@ static void mt7621_pcie_init_ports(struc
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}
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}
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- rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
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- rt_sysc_m32(PCIE_CLK_GEN_EN, PCIE_CLK_GEN_DIS, RALINK_PCIE_CLK_GEN);
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- rt_sysc_m32(PCIE_CLK_GEN1_DIS, PCIE_CLK_GEN1_EN, RALINK_PCIE_CLK_GEN1);
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- rt_sysc_m32(PCIE_CLK_GEN_DIS, PCIE_CLK_GEN_EN, RALINK_PCIE_CLK_GEN);
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- msleep(50);
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reset_control_deassert(pcie->rst);
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}
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@@ -542,6 +536,7 @@ static void mt7621_pcie_enable_ports(str
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list_for_each_entry(port, &pcie->ports, list) {
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if (port->enabled) {
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+ mt7621_pcie_port_clk_enable(port);
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mt7621_pcie_enable_port(port);
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dev_info(dev, "PCIE%d enabled\n", num_slots_enabled);
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num_slots_enabled++;
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