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456 lines
14 KiB
C
456 lines
14 KiB
C
/*
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* Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all copies.
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
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* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _EDMA_H_
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#define _EDMA_H_
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/io.h>
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#include <linux/vmalloc.h>
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#include <linux/pagemap.h>
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#include <linux/smp.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/clk.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/sysctl.h>
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#include <linux/phy.h>
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#include <linux/of_net.h>
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#include <net/checksum.h>
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#include <net/ip6_checksum.h>
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#include <asm-generic/bug.h>
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#include "ess_edma.h"
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#define EDMA_CPU_CORES_SUPPORTED 4
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#define EDMA_MAX_PORTID_SUPPORTED 5
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#define EDMA_MAX_VLAN_SUPPORTED EDMA_MAX_PORTID_SUPPORTED
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#define EDMA_MAX_PORTID_BITMAP_INDEX (EDMA_MAX_PORTID_SUPPORTED + 1)
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#define EDMA_MAX_PORTID_BITMAP_SUPPORTED 0x1f /* 0001_1111 = 0x1f */
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#define EDMA_MAX_NETDEV_PER_QUEUE 4 /* 3 Netdev per queue, 1 space for indexing */
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#define EDMA_MAX_RECEIVE_QUEUE 8
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#define EDMA_MAX_TRANSMIT_QUEUE 16
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/* WAN/LAN adapter number */
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#define EDMA_WAN 0
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#define EDMA_LAN 1
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/* VLAN tag */
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#define EDMA_LAN_DEFAULT_VLAN 1
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#define EDMA_WAN_DEFAULT_VLAN 2
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#define EDMA_DEFAULT_GROUP1_VLAN 1
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#define EDMA_DEFAULT_GROUP2_VLAN 2
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#define EDMA_DEFAULT_GROUP3_VLAN 3
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#define EDMA_DEFAULT_GROUP4_VLAN 4
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#define EDMA_DEFAULT_GROUP5_VLAN 5
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/* Queues exposed to linux kernel */
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#define EDMA_NETDEV_TX_QUEUE 4
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#define EDMA_NETDEV_RX_QUEUE 4
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/* Number of queues per core */
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#define EDMA_NUM_TXQ_PER_CORE 4
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#define EDMA_NUM_RXQ_PER_CORE 2
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#define EDMA_TPD_EOP_SHIFT 31
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#define EDMA_PORT_ID_SHIFT 12
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#define EDMA_PORT_ID_MASK 0x7
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/* tpd word 3 bit 18-28 */
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#define EDMA_TPD_PORT_BITMAP_SHIFT 18
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#define EDMA_TPD_FROM_CPU_SHIFT 25
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#define EDMA_FROM_CPU_MASK 0x80
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#define EDMA_SKB_PRIORITY_MASK 0x38
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/* TX/RX descriptor ring count */
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/* should be a power of 2 */
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#define EDMA_RX_RING_SIZE 128
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#define EDMA_TX_RING_SIZE 128
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/* Flags used in paged/non paged mode */
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#define EDMA_RX_HEAD_BUFF_SIZE_JUMBO 256
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#define EDMA_RX_HEAD_BUFF_SIZE 1540
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/* MAX frame size supported by switch */
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#define EDMA_MAX_JUMBO_FRAME_SIZE 9216
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/* Configurations */
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#define EDMA_INTR_CLEAR_TYPE 0
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#define EDMA_INTR_SW_IDX_W_TYPE 0
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#define EDMA_FIFO_THRESH_TYPE 0
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#define EDMA_RSS_TYPE 0
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#define EDMA_RX_IMT 0x0020
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#define EDMA_TX_IMT 0x0050
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#define EDMA_TPD_BURST 5
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#define EDMA_TXF_BURST 0x100
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#define EDMA_RFD_BURST 8
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#define EDMA_RFD_THR 16
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#define EDMA_RFD_LTHR 0
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/* RX/TX per CPU based mask/shift */
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#define EDMA_TX_PER_CPU_MASK 0xF
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#define EDMA_RX_PER_CPU_MASK 0x3
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#define EDMA_TX_PER_CPU_MASK_SHIFT 0x2
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#define EDMA_RX_PER_CPU_MASK_SHIFT 0x1
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#define EDMA_TX_CPU_START_SHIFT 0x2
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#define EDMA_RX_CPU_START_SHIFT 0x1
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/* FLags used in transmit direction */
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#define EDMA_HW_CHECKSUM 0x00000001
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#define EDMA_VLAN_TX_TAG_INSERT_FLAG 0x00000002
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#define EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG 0x00000004
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#define EDMA_SW_DESC_FLAG_LAST 0x1
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#define EDMA_SW_DESC_FLAG_SKB_HEAD 0x2
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#define EDMA_SW_DESC_FLAG_SKB_FRAG 0x4
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#define EDMA_SW_DESC_FLAG_SKB_FRAGLIST 0x8
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#define EDMA_SW_DESC_FLAG_SKB_NONE 0x10
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#define EDMA_SW_DESC_FLAG_SKB_REUSE 0x20
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#define EDMA_MAX_SKB_FRAGS (MAX_SKB_FRAGS + 1)
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/* Ethtool specific list of EDMA supported features */
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#define EDMA_SUPPORTED_FEATURES (SUPPORTED_10baseT_Half \
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| SUPPORTED_10baseT_Full \
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| SUPPORTED_100baseT_Half \
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| SUPPORTED_100baseT_Full \
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| SUPPORTED_1000baseT_Full)
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/* Recevie side atheros Header */
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#define EDMA_RX_ATH_HDR_VERSION 0x2
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#define EDMA_RX_ATH_HDR_VERSION_SHIFT 14
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#define EDMA_RX_ATH_HDR_PRIORITY_SHIFT 11
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#define EDMA_RX_ATH_PORT_TYPE_SHIFT 6
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#define EDMA_RX_ATH_HDR_RSTP_PORT_TYPE 0x4
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/* Transmit side atheros Header */
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#define EDMA_TX_ATH_HDR_PORT_BITMAP_MASK 0x7F
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#define EDMA_TX_ATH_HDR_FROM_CPU_MASK 0x80
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#define EDMA_TX_ATH_HDR_FROM_CPU_SHIFT 7
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#define EDMA_TXQ_START_CORE0 8
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#define EDMA_TXQ_START_CORE1 12
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#define EDMA_TXQ_START_CORE2 0
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#define EDMA_TXQ_START_CORE3 4
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#define EDMA_TXQ_IRQ_MASK_CORE0 0x0F00
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#define EDMA_TXQ_IRQ_MASK_CORE1 0xF000
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#define EDMA_TXQ_IRQ_MASK_CORE2 0x000F
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#define EDMA_TXQ_IRQ_MASK_CORE3 0x00F0
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#define EDMA_ETH_HDR_LEN 12
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#define EDMA_ETH_TYPE_MASK 0xFFFF
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#define EDMA_RX_BUFFER_WRITE 16
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#define EDMA_RFD_AVAIL_THR 80
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#define EDMA_GMAC_NO_MDIO_PHY PHY_MAX_ADDR
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extern int ssdk_rfs_ipct_rule_set(__be32 ip_src, __be32 ip_dst,
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__be16 sport, __be16 dport,
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uint8_t proto, u16 loadbalance, bool action);
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struct edma_ethtool_statistics {
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u32 tx_q0_pkt;
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u32 tx_q1_pkt;
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u32 tx_q2_pkt;
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u32 tx_q3_pkt;
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u32 tx_q4_pkt;
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u32 tx_q5_pkt;
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u32 tx_q6_pkt;
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u32 tx_q7_pkt;
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u32 tx_q8_pkt;
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u32 tx_q9_pkt;
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u32 tx_q10_pkt;
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u32 tx_q11_pkt;
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u32 tx_q12_pkt;
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u32 tx_q13_pkt;
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u32 tx_q14_pkt;
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u32 tx_q15_pkt;
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u32 tx_q0_byte;
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u32 tx_q1_byte;
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u32 tx_q2_byte;
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u32 tx_q3_byte;
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u32 tx_q4_byte;
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u32 tx_q5_byte;
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u32 tx_q6_byte;
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u32 tx_q7_byte;
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u32 tx_q8_byte;
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u32 tx_q9_byte;
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u32 tx_q10_byte;
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u32 tx_q11_byte;
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u32 tx_q12_byte;
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u32 tx_q13_byte;
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u32 tx_q14_byte;
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u32 tx_q15_byte;
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u32 rx_q0_pkt;
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u32 rx_q1_pkt;
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u32 rx_q2_pkt;
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u32 rx_q3_pkt;
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u32 rx_q4_pkt;
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u32 rx_q5_pkt;
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u32 rx_q6_pkt;
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u32 rx_q7_pkt;
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u32 rx_q0_byte;
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u32 rx_q1_byte;
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u32 rx_q2_byte;
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u32 rx_q3_byte;
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u32 rx_q4_byte;
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u32 rx_q5_byte;
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u32 rx_q6_byte;
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u32 rx_q7_byte;
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u32 tx_desc_error;
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u32 rx_alloc_fail_ctr;
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};
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struct edma_mdio_data {
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struct mii_bus *mii_bus;
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void __iomem *membase;
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int phy_irq[PHY_MAX_ADDR];
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};
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/* EDMA LINK state */
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enum edma_link_state {
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__EDMA_LINKUP, /* Indicate link is UP */
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__EDMA_LINKDOWN /* Indicate link is down */
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};
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/* EDMA GMAC state */
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enum edma_gmac_state {
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__EDMA_UP /* use to indicate GMAC is up */
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};
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/* edma transmit descriptor */
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struct edma_tx_desc {
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__le16 len; /* full packet including CRC */
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__le16 svlan_tag; /* vlan tag */
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__le32 word1; /* byte 4-7 */
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__le32 addr; /* address of buffer */
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__le32 word3; /* byte 12 */
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};
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/* edma receive return descriptor */
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struct edma_rx_return_desc {
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u16 rrd0;
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u16 rrd1;
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u16 rrd2;
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u16 rrd3;
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u16 rrd4;
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u16 rrd5;
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u16 rrd6;
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u16 rrd7;
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};
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/* RFD descriptor */
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struct edma_rx_free_desc {
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__le32 buffer_addr; /* buffer address */
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};
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/* edma hw specific data */
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struct edma_hw {
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u32 __iomem *hw_addr; /* inner register address */
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struct edma_adapter *adapter; /* netdevice adapter */
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u32 rx_intr_mask; /*rx interrupt mask */
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u32 tx_intr_mask; /* tx interrupt nask */
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u32 misc_intr_mask; /* misc interrupt mask */
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u32 wol_intr_mask; /* wake on lan interrupt mask */
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bool intr_clear_type; /* interrupt clear */
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bool intr_sw_idx_w; /* interrupt software index */
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u32 rx_head_buff_size; /* Rx buffer size */
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u8 rss_type; /* rss protocol type */
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};
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/* edma_sw_desc stores software descriptor
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* SW descriptor has 1:1 map with HW descriptor
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*/
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struct edma_sw_desc {
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struct sk_buff *skb;
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dma_addr_t dma; /* dma address */
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u16 length; /* Tx/Rx buffer length */
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u32 flags;
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};
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/* per core related information */
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struct edma_per_cpu_queues_info {
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struct napi_struct napi; /* napi associated with the core */
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u32 tx_mask; /* tx interrupt mask */
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u32 rx_mask; /* rx interrupt mask */
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u32 tx_status; /* tx interrupt status */
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u32 rx_status; /* rx interrupt status */
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u32 tx_start; /* tx queue start */
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u32 rx_start; /* rx queue start */
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struct edma_common_info *edma_cinfo; /* edma common info */
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};
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/* edma specific common info */
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struct edma_common_info {
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struct edma_tx_desc_ring *tpd_ring[16]; /* 16 Tx queues */
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struct edma_rfd_desc_ring *rfd_ring[8]; /* 8 Rx queues */
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struct platform_device *pdev; /* device structure */
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struct net_device *netdev[EDMA_MAX_PORTID_SUPPORTED];
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struct net_device *portid_netdev_lookup_tbl[EDMA_MAX_PORTID_BITMAP_INDEX];
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struct ctl_table_header *edma_ctl_table_hdr;
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int num_gmac;
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struct edma_ethtool_statistics edma_ethstats; /* ethtool stats */
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int num_rx_queues; /* number of rx queue */
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u32 num_tx_queues; /* number of tx queue */
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u32 tx_irq[16]; /* number of tx irq */
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u32 rx_irq[8]; /* number of rx irq */
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u32 from_cpu; /* from CPU TPD field */
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u32 num_rxq_per_core; /* Rx queues per core */
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u32 num_txq_per_core; /* Tx queues per core */
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u16 tx_ring_count; /* Tx ring count */
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u16 rx_ring_count; /* Rx ring*/
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u16 rx_head_buffer_len; /* rx buffer length */
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u16 rx_page_buffer_len; /* rx buffer length */
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u32 page_mode; /* Jumbo frame supported flag */
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u32 fraglist_mode; /* fraglist supported flag */
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struct edma_hw hw; /* edma hw specific structure */
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struct edma_per_cpu_queues_info edma_percpu_info[CONFIG_NR_CPUS]; /* per cpu information */
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spinlock_t stats_lock; /* protect edma stats area for updation */
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struct timer_list edma_stats_timer;
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bool is_single_phy;
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void __iomem *ess_hw_addr;
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struct clk *ess_clk;
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};
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/* transimit packet descriptor (tpd) ring */
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struct edma_tx_desc_ring {
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struct netdev_queue *nq[EDMA_MAX_NETDEV_PER_QUEUE]; /* Linux queue index */
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struct net_device *netdev[EDMA_MAX_NETDEV_PER_QUEUE];
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/* Array of netdevs associated with the tpd ring */
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void *hw_desc; /* descriptor ring virtual address */
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struct edma_sw_desc *sw_desc; /* buffer associated with ring */
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int netdev_bmp; /* Bitmap for per-ring netdevs */
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u32 size; /* descriptor ring length in bytes */
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u16 count; /* number of descriptors in the ring */
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dma_addr_t dma; /* descriptor ring physical address */
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u16 sw_next_to_fill; /* next Tx descriptor to fill */
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u16 sw_next_to_clean; /* next Tx descriptor to clean */
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};
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/* receive free descriptor (rfd) ring */
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struct edma_rfd_desc_ring {
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void *hw_desc; /* descriptor ring virtual address */
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struct edma_sw_desc *sw_desc; /* buffer associated with ring */
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u16 size; /* bytes allocated to sw_desc */
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u16 count; /* number of descriptors in the ring */
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dma_addr_t dma; /* descriptor ring physical address */
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u16 sw_next_to_fill; /* next descriptor to fill */
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u16 sw_next_to_clean; /* next descriptor to clean */
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u16 pending_fill; /* fill pending from previous iteration */
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};
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/* edma_rfs_flter_node - rfs filter node in hash table */
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struct edma_rfs_filter_node {
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struct flow_keys keys;
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u32 flow_id; /* flow_id of filter provided by kernel */
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u16 filter_id; /* filter id of filter returned by adaptor */
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u16 rq_id; /* desired rq index */
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struct hlist_node node; /* edma rfs list node */
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};
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/* edma_rfs_flow_tbl - rfs flow table */
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struct edma_rfs_flow_table {
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u16 max_num_filter; /* Maximum number of filters edma supports */
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u16 hashtoclean; /* hash table index to clean next */
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int filter_available; /* Number of free filters available */
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struct hlist_head hlist_head[EDMA_RFS_FLOW_ENTRIES];
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spinlock_t rfs_ftab_lock;
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struct timer_list expire_rfs; /* timer function for edma_rps_may_expire_flow */
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};
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/* EDMA net device structure */
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struct edma_adapter {
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struct net_device *netdev; /* netdevice */
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struct platform_device *pdev; /* platform device */
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struct edma_common_info *edma_cinfo; /* edma common info */
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struct phy_device *phydev; /* Phy device */
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struct edma_rfs_flow_table rfs; /* edma rfs flow table */
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struct net_device_stats stats; /* netdev statistics */
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set_rfs_filter_callback_t set_rfs_rule;
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u32 flags;/* status flags */
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unsigned long state_flags; /* GMAC up/down flags */
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u32 forced_speed; /* link force speed */
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u32 forced_duplex; /* link force duplex */
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u32 link_state; /* phy link state */
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u32 phy_mdio_addr; /* PHY device address on MII interface */
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u32 poll_required; /* check if link polling is required */
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u32 tx_start_offset[CONFIG_NR_CPUS]; /* tx queue start */
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u32 default_vlan_tag; /* vlan tag */
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u32 dp_bitmap;
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uint8_t phy_id[MII_BUS_ID_SIZE + 3];
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};
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int edma_alloc_queues_tx(struct edma_common_info *edma_cinfo);
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int edma_alloc_queues_rx(struct edma_common_info *edma_cinfo);
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int edma_open(struct net_device *netdev);
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int edma_close(struct net_device *netdev);
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void edma_free_tx_resources(struct edma_common_info *edma_c_info);
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void edma_free_rx_resources(struct edma_common_info *edma_c_info);
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int edma_alloc_tx_rings(struct edma_common_info *edma_cinfo);
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int edma_alloc_rx_rings(struct edma_common_info *edma_cinfo);
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void edma_free_tx_rings(struct edma_common_info *edma_cinfo);
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void edma_free_rx_rings(struct edma_common_info *edma_cinfo);
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void edma_free_queues(struct edma_common_info *edma_cinfo);
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void edma_irq_disable(struct edma_common_info *edma_cinfo);
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int edma_reset(struct edma_common_info *edma_cinfo);
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int edma_poll(struct napi_struct *napi, int budget);
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netdev_tx_t edma_xmit(struct sk_buff *skb,
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struct net_device *netdev);
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int edma_configure(struct edma_common_info *edma_cinfo);
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void edma_irq_enable(struct edma_common_info *edma_cinfo);
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void edma_enable_tx_ctrl(struct edma_hw *hw);
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void edma_enable_rx_ctrl(struct edma_hw *hw);
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void edma_stop_rx_tx(struct edma_hw *hw);
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void edma_free_irqs(struct edma_adapter *adapter);
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irqreturn_t edma_interrupt(int irq, void *dev);
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void edma_write_reg(u16 reg_addr, u32 reg_value);
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void edma_read_reg(u16 reg_addr, volatile u32 *reg_value);
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struct net_device_stats *edma_get_stats(struct net_device *netdev);
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int edma_set_mac_addr(struct net_device *netdev, void *p);
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int edma_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
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u16 rxq, u32 flow_id);
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int edma_register_rfs_filter(struct net_device *netdev,
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set_rfs_filter_callback_t set_filter);
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void edma_flow_may_expire(struct timer_list *t);
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void edma_set_ethtool_ops(struct net_device *netdev);
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void edma_set_stp_rstp(bool tag);
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void edma_assign_ath_hdr_type(int tag);
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int edma_get_default_vlan_tag(struct net_device *netdev);
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void edma_adjust_link(struct net_device *netdev);
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int edma_fill_netdev(struct edma_common_info *edma_cinfo, int qid, int num, int txq_id);
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void edma_read_append_stats(struct edma_common_info *edma_cinfo);
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void edma_change_tx_coalesce(int usecs);
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void edma_change_rx_coalesce(int usecs);
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void edma_get_tx_rx_coalesce(u32 *reg_val);
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void edma_clear_irq_status(void);
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void ess_set_port_status_speed(struct edma_common_info *edma_cinfo,
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struct phy_device *phydev, uint8_t port_id);
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#endif /* _EDMA_H_ */
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