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107 lines
3.1 KiB
Diff
107 lines
3.1 KiB
Diff
--- a/arch/mips/ath79/irq.c
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+++ b/arch/mips/ath79/irq.c
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@@ -27,6 +27,9 @@
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#include "machtypes.h"
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+static struct irq_chip ip2_chip;
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+static struct irq_chip ip3_chip;
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+
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static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
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{
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u32 status;
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@@ -56,8 +59,7 @@ static void ar934x_ip2_irq_init(void)
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for (i = ATH79_IP2_IRQ_BASE;
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip,
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- handle_level_irq);
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+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
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}
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@@ -85,7 +87,7 @@ static void qca953x_irq_init(void)
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for (i = ATH79_IP2_IRQ_BASE;
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
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+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
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}
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@@ -149,15 +151,13 @@ static void qca955x_irq_init(void)
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for (i = ATH79_IP2_IRQ_BASE;
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip,
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- handle_level_irq);
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+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
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for (i = ATH79_IP3_IRQ_BASE;
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i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip,
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- handle_level_irq);
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+ irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
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}
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@@ -228,13 +228,13 @@ static void qca956x_irq_init(void)
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for (i = ATH79_IP2_IRQ_BASE;
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
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+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
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for (i = ATH79_IP3_IRQ_BASE;
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i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
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+ irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
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@@ -243,12 +243,40 @@ static void qca956x_irq_init(void)
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late_time_init = &qca956x_enable_timer_cb;
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}
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+static void ath79_ip2_disable(struct irq_data *data)
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+{
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+ disable_irq(ATH79_CPU_IRQ(2));
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+}
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+
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+static void ath79_ip2_enable(struct irq_data *data)
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+{
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+ enable_irq(ATH79_CPU_IRQ(2));
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+}
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+
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+static void ath79_ip3_disable(struct irq_data *data)
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+{
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+ disable_irq(ATH79_CPU_IRQ(3));
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+}
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+
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+static void ath79_ip3_enable(struct irq_data *data)
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+{
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+ enable_irq(ATH79_CPU_IRQ(3));
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+}
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+
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void __init arch_init_irq(void)
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{
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unsigned irq_wb_chan2 = -1;
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unsigned irq_wb_chan3 = -1;
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bool misc_is_ar71xx;
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+ ip2_chip = dummy_irq_chip;
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+ ip2_chip.irq_disable = ath79_ip2_disable;
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+ ip2_chip.irq_enable = ath79_ip2_enable;
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+
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+ ip3_chip = dummy_irq_chip;
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+ ip3_chip.irq_disable = ath79_ip3_disable;
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+ ip3_chip.irq_enable = ath79_ip3_enable;
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+
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if (mips_machtype == ATH79_MACH_GENERIC_OF) {
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irqchip_init();
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return;
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