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61 lines
2.3 KiB
Diff
61 lines
2.3 KiB
Diff
From: Mantas Pucka <mantas@8devices.com>
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To: linux-mtd@lists.infradead.org
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Subject: [PATCH] mtd: spi-nor: fix 4-byte opcode support for w25q256
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Date: Wed, 15 Apr 2020 16:48:30 +0300
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Message-ID: <1586958510-24012-1-git-send-email-mantas@8devices.com>
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There are 2 different chips (w25q256fv and w25q256jv) that share
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the same JEDEC ID. Only w25q256jv fully supports 4-byte opcodes.
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Use SFDP header version to differentiate between them.
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for OpenWRT only: rebased to linux-v5.4
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Signed-off-by: Mantas Pucka <mantas@8devices.com>
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---
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -2170,6 +2170,32 @@ static struct spi_nor_fixups gd25q256_fi
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.default_init = gd25q256_default_init,
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};
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+static int
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+w25q256_post_bfpt_fixups(struct spi_nor *nor,
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+ const struct sfdp_parameter_header *bfpt_header,
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+ const struct sfdp_bfpt *bfpt,
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+ struct spi_nor_flash_parameter *params)
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+{
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+ /*
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+ * W25Q256JV supports 4B opcodes but W25Q256FV does not.
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+ * Unfortunately, Winbond has re-used the same JEDEC ID for both
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+ * variants which prevents us from defining a new entry in the parts
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+ * table.
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+ * To differentiate between W25Q256JV and W25Q256FV check SFDP header
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+ * version: only JV has JESD216A compliant structure (version 5)
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+ */
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+
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+ if (bfpt_header->major == SFDP_JESD216_MAJOR &&
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+ bfpt_header->minor == SFDP_JESD216A_MINOR)
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+ nor->flags |= SNOR_F_4B_OPCODES;
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+
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+ return 0;
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+}
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+
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+static struct spi_nor_fixups w25q256_fixups = {
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+ .post_bfpt = w25q256_post_bfpt_fixups,
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+};
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+
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/* NOTE: double check command sets and memory organization when you add
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* more nor chips. This current list focusses on newer chips, which
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* have been converging on command sets which including JEDEC ID.
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@@ -2513,7 +2539,8 @@ static const struct flash_info spi_nor_i
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{ "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
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{ "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
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{ "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
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- { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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+ { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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+ .fixups = &w25q256_fixups },
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{ "w25q256jvm", INFO(0xef7019, 0, 64 * 1024, 512,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024,
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