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159 lines
6.3 KiB
Diff
159 lines
6.3 KiB
Diff
From fb9e4932d17ad32786d03cb672fb62f2b337acf5 Mon Sep 17 00:00:00 2001
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From: Jon Mason <jonmason@broadcom.com>
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Date: Thu, 15 Oct 2015 15:48:29 -0400
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Subject: [PATCH 48/50] clk: iproc: Split off dig_filter
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The PLL loop filter/gain can be located in a separate register on some
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SoCs. Split these off into a separate variable, so that an offset can
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be added if necessary. Also, make the necessary modifications to the
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Cygnus and NSP drivers for this change.
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Signed-off-by: Jon Mason <jonmason@broadcom.com>
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---
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drivers/clk/bcm/clk-cygnus.c | 17 +++++++++++------
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drivers/clk/bcm/clk-iproc-pll.c | 14 +++++++++-----
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drivers/clk/bcm/clk-iproc.h | 10 +++++++++-
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drivers/clk/bcm/clk-nsp.c | 14 +++++++++-----
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4 files changed, 38 insertions(+), 17 deletions(-)
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--- a/drivers/clk/bcm/clk-cygnus.c
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+++ b/drivers/clk/bcm/clk-cygnus.c
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@@ -34,9 +34,11 @@
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{ .offset = o, .en_shift = es, .high_shift = hs, \
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.high_width = hw, .low_shift = ls, .low_width = lw }
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-#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
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- .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \
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- .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
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+#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
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+ .p_reset_shift = prs }
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+
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+#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\
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+ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
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.ka_width = kaw }
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#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
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@@ -56,7 +58,8 @@ static const struct iproc_pll_ctrl genpl
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.flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
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IPROC_CLK_PLL_NEEDS_SW_CFG,
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.aon = AON_VAL(0x0, 2, 1, 0),
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- .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
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+ .reset = RESET_VAL(0x0, 11, 10),
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+ .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
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.sw_ctrl = SW_CTRL_VAL(0x10, 31),
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.ndiv_int = REG_VAL(0x10, 20, 10),
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.ndiv_frac = REG_VAL(0x10, 0, 20),
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@@ -114,7 +117,8 @@ CLK_OF_DECLARE(cygnus_genpll, "brcm,cygn
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static const struct iproc_pll_ctrl lcpll0 = {
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.flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG,
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.aon = AON_VAL(0x0, 2, 5, 4),
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- .reset = RESET_VAL(0x0, 31, 30, 27, 3, 23, 4, 19, 4),
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+ .reset = RESET_VAL(0x0, 31, 30),
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+ .dig_filter = DF_VAL(0x0, 27, 3, 23, 4, 19, 4),
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.sw_ctrl = SW_CTRL_VAL(0x4, 31),
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.ndiv_int = REG_VAL(0x4, 16, 10),
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.pdiv = REG_VAL(0x4, 26, 4),
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@@ -191,7 +195,8 @@ static const struct iproc_pll_ctrl mipip
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IPROC_CLK_NEEDS_READ_BACK,
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.aon = AON_VAL(0x0, 4, 17, 16),
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.asiu = ASIU_GATE_VAL(0x0, 3),
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- .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 4),
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+ .reset = RESET_VAL(0x0, 11, 10),
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+ .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 4),
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.ndiv_int = REG_VAL(0x10, 20, 10),
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.ndiv_frac = REG_VAL(0x10, 0, 20),
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.pdiv = REG_VAL(0x14, 0, 4),
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--- a/drivers/clk/bcm/clk-iproc-pll.c
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+++ b/drivers/clk/bcm/clk-iproc-pll.c
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@@ -224,13 +224,17 @@ static void __pll_bring_out_reset(struct
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u32 val;
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const struct iproc_pll_ctrl *ctrl = pll->ctrl;
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const struct iproc_pll_reset_ctrl *reset = &ctrl->reset;
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+ const struct iproc_pll_dig_filter_ctrl *dig_filter = &ctrl->dig_filter;
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+
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+ val = readl(pll->pll_base + dig_filter->offset);
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+ val &= ~(bit_mask(dig_filter->ki_width) << dig_filter->ki_shift |
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+ bit_mask(dig_filter->kp_width) << dig_filter->kp_shift |
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+ bit_mask(dig_filter->ka_width) << dig_filter->ka_shift);
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+ val |= ki << dig_filter->ki_shift | kp << dig_filter->kp_shift |
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+ ka << dig_filter->ka_shift;
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+ iproc_pll_write(pll, pll->pll_base, dig_filter->offset, val);
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val = readl(pll->pll_base + reset->offset);
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- val &= ~(bit_mask(reset->ki_width) << reset->ki_shift |
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- bit_mask(reset->kp_width) << reset->kp_shift |
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- bit_mask(reset->ka_width) << reset->ka_shift);
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- val |= ki << reset->ki_shift | kp << reset->kp_shift |
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- ka << reset->ka_shift;
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val |= 1 << reset->reset_shift | 1 << reset->p_reset_shift;
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iproc_pll_write(pll, pll->pll_base, reset->offset, val);
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}
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--- a/drivers/clk/bcm/clk-iproc.h
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+++ b/drivers/clk/bcm/clk-iproc.h
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@@ -94,12 +94,19 @@ struct iproc_pll_aon_pwr_ctrl {
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};
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/*
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- * Control of the PLL reset, with Ki, Kp, and Ka parameters
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+ * Control of the PLL reset
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*/
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struct iproc_pll_reset_ctrl {
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unsigned int offset;
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unsigned int reset_shift;
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unsigned int p_reset_shift;
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+};
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+
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+/*
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+ * Control of the Ki, Kp, and Ka parameters
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+ */
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+struct iproc_pll_dig_filter_ctrl {
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+ unsigned int offset;
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unsigned int ki_shift;
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unsigned int ki_width;
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unsigned int kp_shift;
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@@ -129,6 +136,7 @@ struct iproc_pll_ctrl {
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struct iproc_pll_aon_pwr_ctrl aon;
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struct iproc_asiu_gate asiu;
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struct iproc_pll_reset_ctrl reset;
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+ struct iproc_pll_dig_filter_ctrl dig_filter;
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struct iproc_pll_sw_ctrl sw_ctrl;
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struct iproc_clk_reg_op ndiv_int;
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struct iproc_clk_reg_op ndiv_frac;
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--- a/drivers/clk/bcm/clk-nsp.c
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+++ b/drivers/clk/bcm/clk-nsp.c
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@@ -26,9 +26,11 @@
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#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
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.pwr_shift = ps, .iso_shift = is }
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-#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
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- .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \
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- .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
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+#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
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+ .p_reset_shift = prs }
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+
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+#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\
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+ .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
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.ka_width = kaw }
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#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
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@@ -43,7 +45,8 @@ CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-arm
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static const struct iproc_pll_ctrl genpll = {
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.flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL,
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.aon = AON_VAL(0x0, 1, 12, 0),
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- .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
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+ .reset = RESET_VAL(0x0, 11, 10),
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+ .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
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.ndiv_int = REG_VAL(0x14, 20, 10),
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.ndiv_frac = REG_VAL(0x14, 0, 20),
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.pdiv = REG_VAL(0x18, 24, 3),
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@@ -99,7 +102,8 @@ CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp
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static const struct iproc_pll_ctrl lcpll0 = {
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.flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL,
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.aon = AON_VAL(0x0, 1, 24, 0),
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- .reset = RESET_VAL(0x0, 23, 22, 16, 3, 12, 4, 19, 4),
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+ .reset = RESET_VAL(0x0, 23, 22),
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+ .dig_filter = DF_VAL(0x0, 16, 3, 12, 4, 19, 4),
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.ndiv_int = REG_VAL(0x4, 20, 8),
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.ndiv_frac = REG_VAL(0x4, 0, 20),
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.pdiv = REG_VAL(0x4, 28, 3),
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