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293 lines
10 KiB
Diff
293 lines
10 KiB
Diff
From b5116083e227fa478e20d5ed945430088aa1a00b Mon Sep 17 00:00:00 2001
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From: Jon Mason <jonmason@broadcom.com>
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Date: Thu, 15 Oct 2015 15:48:25 -0400
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Subject: [PATCH 44/50] clk: cygnus: Convert all macros to all caps
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The macros that are being used to initialize the values of the clk
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structures should be all caps. Find and replace all of them with their
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relevant counterparts.
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Signed-off-by: Jon Mason <jonmason@broadcom.com>
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---
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drivers/clk/bcm/clk-cygnus.c | 146 +++++++++++++++++++++----------------------
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1 file changed, 73 insertions(+), 73 deletions(-)
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--- a/drivers/clk/bcm/clk-cygnus.c
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+++ b/drivers/clk/bcm/clk-cygnus.c
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@@ -23,28 +23,28 @@
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#include <dt-bindings/clock/bcm-cygnus.h>
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#include "clk-iproc.h"
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-#define reg_val(o, s, w) { .offset = o, .shift = s, .width = w, }
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+#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
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-#define aon_val(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
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+#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
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.pwr_shift = ps, .iso_shift = is }
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-#define sw_ctrl_val(o, s) { .offset = o, .shift = s, }
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+#define SW_CTRL_VAL(o, s) { .offset = o, .shift = s, }
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-#define asiu_div_val(o, es, hs, hw, ls, lw) \
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+#define ASIU_DIV_VAL(o, es, hs, hw, ls, lw) \
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{ .offset = o, .en_shift = es, .high_shift = hs, \
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.high_width = hw, .low_shift = ls, .low_width = lw }
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-#define reset_val(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
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+#define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
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.reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \
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.ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
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.ka_width = kaw }
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-#define vco_ctrl_val(uo, lo) { .u_offset = uo, .l_offset = lo }
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+#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
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-#define enable_val(o, es, hs, bs) { .offset = o, .enable_shift = es, \
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+#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
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.hold_shift = hs, .bypass_shift = bs }
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-#define asiu_gate_val(o, es) { .offset = o, .en_shift = es }
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+#define ASIU_GATE_VAL(o, es) { .offset = o, .en_shift = es }
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static void __init cygnus_armpll_init(struct device_node *node)
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{
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@@ -55,52 +55,52 @@ CLK_OF_DECLARE(cygnus_armpll, "brcm,cygn
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static const struct iproc_pll_ctrl genpll = {
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.flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
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IPROC_CLK_PLL_NEEDS_SW_CFG,
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- .aon = aon_val(0x0, 2, 1, 0),
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- .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
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- .sw_ctrl = sw_ctrl_val(0x10, 31),
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- .ndiv_int = reg_val(0x10, 20, 10),
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- .ndiv_frac = reg_val(0x10, 0, 20),
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- .pdiv = reg_val(0x14, 0, 4),
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- .vco_ctrl = vco_ctrl_val(0x18, 0x1c),
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- .status = reg_val(0x28, 12, 1),
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+ .aon = AON_VAL(0x0, 2, 1, 0),
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+ .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3),
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+ .sw_ctrl = SW_CTRL_VAL(0x10, 31),
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+ .ndiv_int = REG_VAL(0x10, 20, 10),
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+ .ndiv_frac = REG_VAL(0x10, 0, 20),
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+ .pdiv = REG_VAL(0x14, 0, 4),
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+ .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c),
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+ .status = REG_VAL(0x28, 12, 1),
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};
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static const struct iproc_clk_ctrl genpll_clk[] = {
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[BCM_CYGNUS_GENPLL_AXI21_CLK] = {
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.channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
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.flags = IPROC_CLK_AON,
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- .enable = enable_val(0x4, 6, 0, 12),
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- .mdiv = reg_val(0x20, 0, 8),
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+ .enable = ENABLE_VAL(0x4, 6, 0, 12),
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+ .mdiv = REG_VAL(0x20, 0, 8),
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},
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[BCM_CYGNUS_GENPLL_250MHZ_CLK] = {
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.channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
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.flags = IPROC_CLK_AON,
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- .enable = enable_val(0x4, 7, 1, 13),
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- .mdiv = reg_val(0x20, 10, 8),
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+ .enable = ENABLE_VAL(0x4, 7, 1, 13),
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+ .mdiv = REG_VAL(0x20, 10, 8),
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},
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[BCM_CYGNUS_GENPLL_IHOST_SYS_CLK] = {
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.channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
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.flags = IPROC_CLK_AON,
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- .enable = enable_val(0x4, 8, 2, 14),
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- .mdiv = reg_val(0x20, 20, 8),
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+ .enable = ENABLE_VAL(0x4, 8, 2, 14),
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+ .mdiv = REG_VAL(0x20, 20, 8),
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},
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[BCM_CYGNUS_GENPLL_ENET_SW_CLK] = {
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.channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
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.flags = IPROC_CLK_AON,
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- .enable = enable_val(0x4, 9, 3, 15),
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- .mdiv = reg_val(0x24, 0, 8),
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+ .enable = ENABLE_VAL(0x4, 9, 3, 15),
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+ .mdiv = REG_VAL(0x24, 0, 8),
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},
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[BCM_CYGNUS_GENPLL_AUDIO_125_CLK] = {
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.channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK,
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.flags = IPROC_CLK_AON,
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- .enable = enable_val(0x4, 10, 4, 16),
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- .mdiv = reg_val(0x24, 10, 8),
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+ .enable = ENABLE_VAL(0x4, 10, 4, 16),
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+ .mdiv = REG_VAL(0x24, 10, 8),
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},
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[BCM_CYGNUS_GENPLL_CAN_CLK] = {
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.channel = BCM_CYGNUS_GENPLL_CAN_CLK,
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.flags = IPROC_CLK_AON,
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- .enable = enable_val(0x4, 11, 5, 17),
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- .mdiv = reg_val(0x24, 20, 8),
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+ .enable = ENABLE_VAL(0x4, 11, 5, 17),
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+ .mdiv = REG_VAL(0x24, 20, 8),
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},
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};
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@@ -113,51 +113,51 @@ CLK_OF_DECLARE(cygnus_genpll, "brcm,cygn
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static const struct iproc_pll_ctrl lcpll0 = {
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.flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG,
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- .aon = aon_val(0x0, 2, 5, 4),
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- .reset = reset_val(0x0, 31, 30, 27, 3, 23, 4, 19, 4),
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- .sw_ctrl = sw_ctrl_val(0x4, 31),
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- .ndiv_int = reg_val(0x4, 16, 10),
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- .pdiv = reg_val(0x4, 26, 4),
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- .vco_ctrl = vco_ctrl_val(0x10, 0x14),
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- .status = reg_val(0x18, 12, 1),
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+ .aon = AON_VAL(0x0, 2, 5, 4),
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+ .reset = RESET_VAL(0x0, 31, 30, 27, 3, 23, 4, 19, 4),
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+ .sw_ctrl = SW_CTRL_VAL(0x4, 31),
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+ .ndiv_int = REG_VAL(0x4, 16, 10),
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+ .pdiv = REG_VAL(0x4, 26, 4),
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+ .vco_ctrl = VCO_CTRL_VAL(0x10, 0x14),
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+ .status = REG_VAL(0x18, 12, 1),
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};
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static const struct iproc_clk_ctrl lcpll0_clk[] = {
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[BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK] = {
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.channel = BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK,
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.flags = IPROC_CLK_AON,
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- .enable = enable_val(0x0, 7, 1, 13),
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- .mdiv = reg_val(0x8, 0, 8),
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+ .enable = ENABLE_VAL(0x0, 7, 1, 13),
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+ .mdiv = REG_VAL(0x8, 0, 8),
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},
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[BCM_CYGNUS_LCPLL0_DDR_PHY_CLK] = {
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.channel = BCM_CYGNUS_LCPLL0_DDR_PHY_CLK,
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.flags = IPROC_CLK_AON,
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- .enable = enable_val(0x0, 8, 2, 14),
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- .mdiv = reg_val(0x8, 10, 8),
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+ .enable = ENABLE_VAL(0x0, 8, 2, 14),
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+ .mdiv = REG_VAL(0x8, 10, 8),
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},
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[BCM_CYGNUS_LCPLL0_SDIO_CLK] = {
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.channel = BCM_CYGNUS_LCPLL0_SDIO_CLK,
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.flags = IPROC_CLK_AON,
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- .enable = enable_val(0x0, 9, 3, 15),
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- .mdiv = reg_val(0x8, 20, 8),
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+ .enable = ENABLE_VAL(0x0, 9, 3, 15),
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+ .mdiv = REG_VAL(0x8, 20, 8),
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},
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[BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK] = {
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.channel = BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK,
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.flags = IPROC_CLK_AON,
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- .enable = enable_val(0x0, 10, 4, 16),
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- .mdiv = reg_val(0xc, 0, 8),
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+ .enable = ENABLE_VAL(0x0, 10, 4, 16),
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+ .mdiv = REG_VAL(0xc, 0, 8),
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},
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[BCM_CYGNUS_LCPLL0_SMART_CARD_CLK] = {
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.channel = BCM_CYGNUS_LCPLL0_SMART_CARD_CLK,
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.flags = IPROC_CLK_AON,
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- .enable = enable_val(0x0, 11, 5, 17),
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- .mdiv = reg_val(0xc, 10, 8),
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+ .enable = ENABLE_VAL(0x0, 11, 5, 17),
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+ .mdiv = REG_VAL(0xc, 10, 8),
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},
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[BCM_CYGNUS_LCPLL0_CH5_UNUSED] = {
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.channel = BCM_CYGNUS_LCPLL0_CH5_UNUSED,
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.flags = IPROC_CLK_AON,
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- .enable = enable_val(0x0, 12, 6, 18),
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- .mdiv = reg_val(0xc, 20, 8),
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+ .enable = ENABLE_VAL(0x0, 12, 6, 18),
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+ .mdiv = REG_VAL(0xc, 20, 8),
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},
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};
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@@ -189,52 +189,52 @@ static const struct iproc_pll_vco_param
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static const struct iproc_pll_ctrl mipipll = {
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.flags = IPROC_CLK_PLL_ASIU | IPROC_CLK_PLL_HAS_NDIV_FRAC |
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IPROC_CLK_NEEDS_READ_BACK,
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- .aon = aon_val(0x0, 4, 17, 16),
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- .asiu = asiu_gate_val(0x0, 3),
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- .reset = reset_val(0x0, 11, 10, 4, 3, 0, 4, 7, 4),
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- .ndiv_int = reg_val(0x10, 20, 10),
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- .ndiv_frac = reg_val(0x10, 0, 20),
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- .pdiv = reg_val(0x14, 0, 4),
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- .vco_ctrl = vco_ctrl_val(0x18, 0x1c),
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- .status = reg_val(0x28, 12, 1),
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+ .aon = AON_VAL(0x0, 4, 17, 16),
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+ .asiu = ASIU_GATE_VAL(0x0, 3),
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+ .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 4),
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+ .ndiv_int = REG_VAL(0x10, 20, 10),
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+ .ndiv_frac = REG_VAL(0x10, 0, 20),
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+ .pdiv = REG_VAL(0x14, 0, 4),
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+ .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c),
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+ .status = REG_VAL(0x28, 12, 1),
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};
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static const struct iproc_clk_ctrl mipipll_clk[] = {
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[BCM_CYGNUS_MIPIPLL_CH0_UNUSED] = {
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.channel = BCM_CYGNUS_MIPIPLL_CH0_UNUSED,
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.flags = IPROC_CLK_NEEDS_READ_BACK,
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- .enable = enable_val(0x4, 12, 6, 18),
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- .mdiv = reg_val(0x20, 0, 8),
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+ .enable = ENABLE_VAL(0x4, 12, 6, 18),
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+ .mdiv = REG_VAL(0x20, 0, 8),
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},
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[BCM_CYGNUS_MIPIPLL_CH1_LCD] = {
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.channel = BCM_CYGNUS_MIPIPLL_CH1_LCD,
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.flags = IPROC_CLK_NEEDS_READ_BACK,
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- .enable = enable_val(0x4, 13, 7, 19),
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- .mdiv = reg_val(0x20, 10, 8),
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+ .enable = ENABLE_VAL(0x4, 13, 7, 19),
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+ .mdiv = REG_VAL(0x20, 10, 8),
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},
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[BCM_CYGNUS_MIPIPLL_CH2_V3D] = {
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.channel = BCM_CYGNUS_MIPIPLL_CH2_V3D,
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.flags = IPROC_CLK_NEEDS_READ_BACK,
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- .enable = enable_val(0x4, 14, 8, 20),
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- .mdiv = reg_val(0x20, 20, 8),
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+ .enable = ENABLE_VAL(0x4, 14, 8, 20),
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+ .mdiv = REG_VAL(0x20, 20, 8),
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},
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[BCM_CYGNUS_MIPIPLL_CH3_UNUSED] = {
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.channel = BCM_CYGNUS_MIPIPLL_CH3_UNUSED,
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.flags = IPROC_CLK_NEEDS_READ_BACK,
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- .enable = enable_val(0x4, 15, 9, 21),
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- .mdiv = reg_val(0x24, 0, 8),
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+ .enable = ENABLE_VAL(0x4, 15, 9, 21),
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+ .mdiv = REG_VAL(0x24, 0, 8),
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},
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[BCM_CYGNUS_MIPIPLL_CH4_UNUSED] = {
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.channel = BCM_CYGNUS_MIPIPLL_CH4_UNUSED,
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.flags = IPROC_CLK_NEEDS_READ_BACK,
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- .enable = enable_val(0x4, 16, 10, 22),
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- .mdiv = reg_val(0x24, 10, 8),
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+ .enable = ENABLE_VAL(0x4, 16, 10, 22),
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+ .mdiv = REG_VAL(0x24, 10, 8),
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},
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[BCM_CYGNUS_MIPIPLL_CH5_UNUSED] = {
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.channel = BCM_CYGNUS_MIPIPLL_CH5_UNUSED,
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.flags = IPROC_CLK_NEEDS_READ_BACK,
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- .enable = enable_val(0x4, 17, 11, 23),
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- .mdiv = reg_val(0x24, 20, 8),
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+ .enable = ENABLE_VAL(0x4, 17, 11, 23),
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+ .mdiv = REG_VAL(0x24, 20, 8),
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},
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};
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@@ -247,15 +247,15 @@ static void __init cygnus_mipipll_clk_in
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CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_clk_init);
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static const struct iproc_asiu_div asiu_div[] = {
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- [BCM_CYGNUS_ASIU_KEYPAD_CLK] = asiu_div_val(0x0, 31, 16, 10, 0, 10),
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- [BCM_CYGNUS_ASIU_ADC_CLK] = asiu_div_val(0x4, 31, 16, 10, 0, 10),
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- [BCM_CYGNUS_ASIU_PWM_CLK] = asiu_div_val(0x8, 31, 16, 10, 0, 10),
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+ [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_DIV_VAL(0x0, 31, 16, 10, 0, 10),
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+ [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_DIV_VAL(0x4, 31, 16, 10, 0, 10),
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+ [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_DIV_VAL(0x8, 31, 16, 10, 0, 10),
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};
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static const struct iproc_asiu_gate asiu_gate[] = {
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- [BCM_CYGNUS_ASIU_KEYPAD_CLK] = asiu_gate_val(0x0, 7),
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- [BCM_CYGNUS_ASIU_ADC_CLK] = asiu_gate_val(0x0, 9),
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- [BCM_CYGNUS_ASIU_PWM_CLK] = asiu_gate_val(IPROC_CLK_INVALID_OFFSET, 0),
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+ [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_GATE_VAL(0x0, 7),
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+ [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_GATE_VAL(0x0, 9),
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+ [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_GATE_VAL(IPROC_CLK_INVALID_OFFSET, 0),
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};
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static void __init cygnus_asiu_init(struct device_node *node)
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