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35 lines
1.3 KiB
Diff
35 lines
1.3 KiB
Diff
From e2d8a52d3ade83f5c114b1edba601ebcf2c39517 Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.org>
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Date: Mon, 11 Nov 2019 14:01:41 +0000
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Subject: [PATCH] drm/v3d: Don't clear MMU control bits on exception
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MMU exception conditions are reported in the V3D_MMU_CTRL register as
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write-1-to-clear (W1C) bits. The MMU interrupt handling code clears any
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exceptions, but does so by masking out any other bits and writing the
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result back. There are some important control bits in that register,
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including MMU_ENABLE, so a safer approach is to simply write back the
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value just read unaltered.
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This patch doesn't remove the cause of the apparent PTE errors, but it
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does reduce the impact to just an error in the kernel log.
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Signed-off-by: Phil Elwell <phil@raspberrypi.org>
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---
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drivers/gpu/drm/v3d/v3d_irq.c | 5 +----
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1 file changed, 1 insertion(+), 4 deletions(-)
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--- a/drivers/gpu/drm/v3d/v3d_irq.c
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+++ b/drivers/gpu/drm/v3d/v3d_irq.c
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@@ -178,10 +178,7 @@ v3d_hub_irq(int irq, void *arg)
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};
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const char *client = "?";
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- V3D_WRITE(V3D_MMU_CTL,
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- V3D_READ(V3D_MMU_CTL) & (V3D_MMU_CTL_CAP_EXCEEDED |
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- V3D_MMU_CTL_PT_INVALID |
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- V3D_MMU_CTL_WRITE_VIOLATION));
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+ V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL));
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if (v3d->ver >= 41) {
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axi_id = axi_id >> 5;
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