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352 lines
9.6 KiB
Diff
352 lines
9.6 KiB
Diff
From f8c8f4bd2a13e0cc060c93812377373d436f7f02 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Wed, 18 Nov 2015 03:13:05 +0100
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Subject: [PATCH 505/513] net-next: mediatek: add support for rt2880
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rt2880 is the oldest SoC with this core. It has a single gBit port that will
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normally be attached to an external phy of switch. The patch also adds the
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code required to drive the mdio bus.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
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Signed-off-by: Michael Lee <igvtee@gmail.com>
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---
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drivers/net/ethernet/mediatek/mdio_rt2880.c | 222 +++++++++++++++++++++++++++
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drivers/net/ethernet/mediatek/mdio_rt2880.h | 23 +++
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drivers/net/ethernet/mediatek/soc_rt2880.c | 76 +++++++++
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3 files changed, 321 insertions(+)
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create mode 100644 drivers/net/ethernet/mediatek/mdio_rt2880.c
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create mode 100644 drivers/net/ethernet/mediatek/mdio_rt2880.h
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create mode 100644 drivers/net/ethernet/mediatek/soc_rt2880.c
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--- /dev/null
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+++ b/drivers/net/ethernet/mediatek/mdio_rt2880.c
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@@ -0,0 +1,222 @@
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+/* This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; version 2 of the License
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
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+ * Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
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+ * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/kernel.h>
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+#include <linux/types.h>
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+#include <linux/of_net.h>
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+#include <linux/of_mdio.h>
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+
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+#include "mtk_eth_soc.h"
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+#include "mdio_rt2880.h"
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+#include "mdio.h"
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+
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+#define FE_MDIO_RETRY 1000
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+
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+static unsigned char *rt2880_speed_str(struct fe_priv *priv)
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+{
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+ switch (priv->phy->speed[0]) {
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+ case SPEED_1000:
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+ return "1000";
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+ case SPEED_100:
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+ return "100";
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+ case SPEED_10:
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+ return "10";
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+ }
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+
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+ return "?";
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+}
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+
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+void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
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+{
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+ u32 mdio_cfg;
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+
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+ if (!priv->link[0]) {
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+ netif_carrier_off(priv->netdev);
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+ netdev_info(priv->netdev, "link down\n");
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+ return;
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+ }
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+
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+ mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
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+ FE_MDIO_CFG_RX_CLK_SKEW_200 |
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+ FE_MDIO_CFG_GP1_FRC_EN;
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+
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+ if (priv->phy->duplex[0] == DUPLEX_FULL)
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+ mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
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+
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+ if (priv->phy->tx_fc[0])
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+ mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
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+
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+ if (priv->phy->rx_fc[0])
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+ mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
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+
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+ switch (priv->phy->speed[0]) {
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+ case SPEED_10:
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+ mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
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+ break;
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+ case SPEED_100:
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+ mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
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+ break;
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+ case SPEED_1000:
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+ mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
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+ break;
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+ default:
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+ BUG();
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+ }
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+
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+ fe_w32(mdio_cfg, FE_MDIO_CFG);
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+
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+ netif_carrier_on(priv->netdev);
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+ netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
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+ rt2880_speed_str(priv),
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+ (priv->phy->duplex[0] == DUPLEX_FULL) ? "Full" : "Half");
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+}
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+
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+static int rt2880_mdio_wait_ready(struct fe_priv *priv)
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+{
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+ int retries;
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+
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+ retries = FE_MDIO_RETRY;
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+ while (1) {
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+ u32 t;
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+
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+ t = fe_r32(FE_MDIO_ACCESS);
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+ if ((t & BIT(31)) == 0)
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+ return 0;
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+
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+ if (retries-- == 0)
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+ break;
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+
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+ udelay(1);
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+ }
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+
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+ dev_err(priv->device, "MDIO operation timed out\n");
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+ return -ETIMEDOUT;
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+}
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+
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+int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
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+{
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+ struct fe_priv *priv = bus->priv;
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+ int err;
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+ u32 t;
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+
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+ err = rt2880_mdio_wait_ready(priv);
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+ if (err)
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+ return 0xffff;
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+
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+ t = (phy_addr << 24) | (phy_reg << 16);
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+ fe_w32(t, FE_MDIO_ACCESS);
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+ t |= BIT(31);
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+ fe_w32(t, FE_MDIO_ACCESS);
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+
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+ err = rt2880_mdio_wait_ready(priv);
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+ if (err)
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+ return 0xffff;
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+
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+ pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
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+ phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
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+
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+ return fe_r32(FE_MDIO_ACCESS) & 0xffff;
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+}
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+
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+int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
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+{
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+ struct fe_priv *priv = bus->priv;
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+ int err;
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+ u32 t;
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+
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+ pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
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+ phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
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+
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+ err = rt2880_mdio_wait_ready(priv);
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+ if (err)
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+ return err;
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+
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+ t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
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+ fe_w32(t, FE_MDIO_ACCESS);
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+ t |= BIT(31);
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+ fe_w32(t, FE_MDIO_ACCESS);
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+
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+ return rt2880_mdio_wait_ready(priv);
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+}
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+
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+void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
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+{
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+ const __be32 *id = of_get_property(np, "reg", NULL);
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+ const __be32 *link;
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+ int size;
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+ int phy_mode;
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+
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+ if (!id || (be32_to_cpu(*id) != 0)) {
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+ pr_err("%s: invalid port id\n", np->name);
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+ return;
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+ }
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+
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+ priv->phy->phy_fixed[0] = of_get_property(np,
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+ "mediatek,fixed-link", &size);
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+ if (priv->phy->phy_fixed[0] &&
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+ (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
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+ pr_err("%s: invalid fixed link property\n", np->name);
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+ priv->phy->phy_fixed[0] = NULL;
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+ return;
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+ }
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+
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+ phy_mode = of_get_phy_mode(np);
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+ switch (phy_mode) {
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+ case PHY_INTERFACE_MODE_RGMII:
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+ break;
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+ case PHY_INTERFACE_MODE_MII:
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+ break;
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+ case PHY_INTERFACE_MODE_RMII:
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+ break;
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+ default:
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+ if (!priv->phy->phy_fixed[0])
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+ dev_err(priv->device, "port %d - invalid phy mode\n",
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+ priv->phy->speed[0]);
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+ break;
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+ }
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+
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+ priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
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+ if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
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+ return;
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+
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+ if (priv->phy->phy_fixed[0]) {
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+ link = priv->phy->phy_fixed[0];
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+ priv->phy->speed[0] = be32_to_cpup(link++);
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+ priv->phy->duplex[0] = be32_to_cpup(link++);
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+ priv->phy->tx_fc[0] = be32_to_cpup(link++);
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+ priv->phy->rx_fc[0] = be32_to_cpup(link++);
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+
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+ priv->link[0] = 1;
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+ switch (priv->phy->speed[0]) {
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+ case SPEED_10:
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+ break;
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+ case SPEED_100:
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+ break;
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+ case SPEED_1000:
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+ break;
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+ default:
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+ dev_err(priv->device, "invalid link speed: %d\n",
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+ priv->phy->speed[0]);
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+ priv->phy->phy_fixed[0] = 0;
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+ return;
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+ }
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+ dev_info(priv->device, "using fixed link parameters\n");
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+ rt2880_mdio_link_adjust(priv, 0);
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+ return;
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+ }
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+
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+ if (priv->phy->phy_node[0] && priv->mii_bus->phy_map[0])
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+ fe_connect_phy_node(priv, priv->phy->phy_node[0]);
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+}
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--- /dev/null
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+++ b/drivers/net/ethernet/mediatek/mdio_rt2880.h
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@@ -0,0 +1,23 @@
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+/* This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; version 2 of the License
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
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+ * Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
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+ * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
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+ */
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+
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+#ifndef _RALINK_MDIO_RT2880_H__
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+#define _RALINK_MDIO_RT2880_H__
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+
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+void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
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+int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
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+int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
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+void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
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+
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+#endif
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--- /dev/null
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+++ b/drivers/net/ethernet/mediatek/soc_rt2880.c
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@@ -0,0 +1,76 @@
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+/* This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; version 2 of the License
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
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+ * Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
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+ * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
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+ */
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+
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+#include <linux/module.h>
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+
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+#include <asm/mach-ralink/ralink_regs.h>
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+
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+#include "mtk_eth_soc.h"
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+#include "mdio_rt2880.h"
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+
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+#define RT2880_RESET_FE BIT(18)
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+
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+static void rt2880_init_data(struct fe_soc_data *data,
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+ struct net_device *netdev)
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+{
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+ struct fe_priv *priv = netdev_priv(netdev);
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+
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+ priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
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+ FE_FLAG_JUMBO_FRAME | FE_FLAG_CALIBRATE_CLK;
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+ netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_TX;
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+ /* this should work according to the datasheet but actually does not*/
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+ /* netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM; */
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+}
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+
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+void rt2880_fe_reset(void)
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+{
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+ fe_reset(RT2880_RESET_FE);
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+}
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+
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+static int rt2880_fwd_config(struct fe_priv *priv)
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+{
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+ int ret;
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+
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+ ret = fe_set_clock_cycle(priv);
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+ if (ret)
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+ return ret;
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+
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+ fe_fwd_config(priv);
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+ fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
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+ fe_csum_config(priv);
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+
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+ return ret;
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+}
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+
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+struct fe_soc_data rt2880_data = {
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+ .init_data = rt2880_init_data,
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+ .reset_fe = rt2880_fe_reset,
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+ .fwd_config = rt2880_fwd_config,
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+ .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
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+ .checksum_bit = RX_DMA_L4VALID,
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+ .rx_int = FE_RX_DONE_INT,
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+ .tx_int = FE_TX_DONE_INT,
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+ .status_int = FE_CNT_GDM_AF,
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+ .mdio_read = rt2880_mdio_read,
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+ .mdio_write = rt2880_mdio_write,
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+ .mdio_adjust_link = rt2880_mdio_link_adjust,
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+ .port_init = rt2880_port_init,
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+};
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+
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+const struct of_device_id of_fe_match[] = {
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+ { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
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+ {},
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+};
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+
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+MODULE_DEVICE_TABLE(of, of_fe_match);
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