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302 lines
7.9 KiB
Diff
302 lines
7.9 KiB
Diff
From 9fc19d5f7354709298dcb15b3a4c7cd9a18acebf Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 14 Dec 2015 21:24:46 +0100
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Subject: [PATCH 504/513] net-next: mediatek: add switch driver for mt7621
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This driver is very basic and only provides basic init and irq support.
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Switchdev support for this device will follow.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/net/ethernet/mediatek/gsw_mt7621.c | 284 ++++++++++++++++++++++++++++
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1 file changed, 284 insertions(+)
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create mode 100644 drivers/net/ethernet/mediatek/gsw_mt7621.c
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--- /dev/null
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+++ b/drivers/net/ethernet/mediatek/gsw_mt7621.c
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@@ -0,0 +1,284 @@
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+/* This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; version 2 of the License
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
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+ * Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
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+ * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/kernel.h>
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+#include <linux/types.h>
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+#include <linux/platform_device.h>
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+#include <linux/of_device.h>
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+#include <linux/of_irq.h>
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+
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+#include <ralink_regs.h>
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+
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+#include "mtk_eth_soc.h"
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+#include "gsw_mt7620.h"
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+
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+void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
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+{
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+ iowrite32(val, gsw->base + reg);
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+}
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+
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+u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
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+{
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+ return ioread32(gsw->base + reg);
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+}
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+
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+static irqreturn_t gsw_interrupt_mt7621(int irq, void *_priv)
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+{
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+ struct fe_priv *priv = (struct fe_priv *)_priv;
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+ struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
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+ u32 reg, i;
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+
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+ reg = mt7530_mdio_r32(gsw, 0x700c);
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+
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+ for (i = 0; i < 5; i++)
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+ if (reg & BIT(i)) {
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+ unsigned int link;
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+
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+ link = mt7530_mdio_r32(gsw,
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+ 0x3008 + (i * 0x100)) & 0x1;
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+
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+ if (link != priv->link[i]) {
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+ priv->link[i] = link;
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+ if (link)
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+ netdev_info(priv->netdev,
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+ "port %d link up\n", i);
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+ else
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+ netdev_info(priv->netdev,
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+ "port %d link down\n", i);
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+ }
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+ }
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+
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+ mt7530_mdio_w32(gsw, 0x700c, 0x1f);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static void mt7621_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
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+{
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+ u32 i;
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+ u32 val;
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+
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+ /* wardware reset the switch */
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+ fe_reset(RST_CTRL_MCM);
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+ mdelay(10);
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+
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+ /* reduce RGMII2 PAD driving strength */
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+ rt_sysc_m32(3 << 4, 0, SYSC_PAD_RGMII2_MDIO);
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+
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+ /* gpio mux - RGMII1=Normal mode */
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+ rt_sysc_m32(BIT(14), 0, SYSC_GPIO_MODE);
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+
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+ /* set GMAC1 RGMII mode */
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+ rt_sysc_m32(3 << 12, 0, SYSC_REG_CFG1);
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+
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+ /* enable MDIO to control MT7530 */
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+ rt_sysc_m32(3 << 12, 0, SYSC_GPIO_MODE);
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+
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+ /* turn off all PHYs */
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+ for (i = 0; i <= 4; i++) {
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+ val = _mt7620_mii_read(gsw, i, 0x0);
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+ val |= BIT(11);
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+ _mt7620_mii_write(gsw, i, 0x0, val);
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+ }
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+
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+ /* reset the switch */
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+ mt7530_mdio_w32(gsw, 0x7000, 0x3);
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+ usleep_range(10, 20);
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+
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+ if ((rt_sysc_r32(SYSC_REG_CHIP_REV_ID) & 0xFFFF) == 0x0101) {
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+ /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
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+ mtk_switch_w32(gsw, 0x2105e30b, 0x100);
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+ mt7530_mdio_w32(gsw, 0x3600, 0x5e30b);
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+ } else {
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+ /* (GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536) */
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+ mtk_switch_w32(gsw, 0x2105e33b, 0x100);
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+ mt7530_mdio_w32(gsw, 0x3600, 0x5e33b);
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+ }
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+
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+ /* (GE2, Link down) */
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+ mtk_switch_w32(gsw, 0x8000, 0x200);
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+
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+ /* Enable Port 6, P5 as GMAC5, P5 disable */
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+ val = mt7530_mdio_r32(gsw, 0x7804);
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+ val &= ~BIT(8);
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+ val |= BIT(6) | BIT(13) | BIT(16);
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+ mt7530_mdio_w32(gsw, 0x7804, val);
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+
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+ val = rt_sysc_r32(0x10);
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+ val = (val >> 6) & 0x7;
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+ if (val >= 6) {
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+ /* 25Mhz Xtal - do nothing */
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+ } else if (val >= 3) {
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+ /* 40Mhz */
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+
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+ /* disable MT7530 core clock */
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+ _mt7620_mii_write(gsw, 0, 13, 0x1f);
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+ _mt7620_mii_write(gsw, 0, 14, 0x410);
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+ _mt7620_mii_write(gsw, 0, 13, 0x401f);
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+ _mt7620_mii_write(gsw, 0, 14, 0x0);
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+
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+ /* disable MT7530 PLL */
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+ _mt7620_mii_write(gsw, 0, 13, 0x1f);
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+ _mt7620_mii_write(gsw, 0, 14, 0x40d);
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+ _mt7620_mii_write(gsw, 0, 13, 0x401f);
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+ _mt7620_mii_write(gsw, 0, 14, 0x2020);
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+
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+ /* for MT7530 core clock = 500Mhz */
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+ _mt7620_mii_write(gsw, 0, 13, 0x1f);
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+ _mt7620_mii_write(gsw, 0, 14, 0x40e);
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+ _mt7620_mii_write(gsw, 0, 13, 0x401f);
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+ _mt7620_mii_write(gsw, 0, 14, 0x119);
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+
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+ /* enable MT7530 PLL */
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+ _mt7620_mii_write(gsw, 0, 13, 0x1f);
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+ _mt7620_mii_write(gsw, 0, 14, 0x40d);
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+ _mt7620_mii_write(gsw, 0, 13, 0x401f);
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+ _mt7620_mii_write(gsw, 0, 14, 0x2820);
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+
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+ usleep_range(20, 40);
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+
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+ /* enable MT7530 core clock */
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+ _mt7620_mii_write(gsw, 0, 13, 0x1f);
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+ _mt7620_mii_write(gsw, 0, 14, 0x410);
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+ _mt7620_mii_write(gsw, 0, 13, 0x401f);
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+ } else {
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+ /* 20Mhz Xtal - TODO */
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+ }
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+
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+ /* RGMII */
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+ _mt7620_mii_write(gsw, 0, 14, 0x1);
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+
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+ /* set MT7530 central align */
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+ val = mt7530_mdio_r32(gsw, 0x7830);
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+ val &= ~BIT(0);
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+ val |= BIT(1);
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+ mt7530_mdio_w32(gsw, 0x7830, val);
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+ val = mt7530_mdio_r32(gsw, 0x7a40);
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+ val &= ~BIT(30);
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+ mt7530_mdio_w32(gsw, 0x7a40, val);
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+ mt7530_mdio_w32(gsw, 0x7a78, 0x855);
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+
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+ /* delay setting for 10/1000M */
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+ mt7530_mdio_w32(gsw, 0x7b00, 0x102);
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+ mt7530_mdio_w32(gsw, 0x7b04, 0x14);
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+
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+ /* lower Tx Driving*/
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+ mt7530_mdio_w32(gsw, 0x7a54, 0x44);
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+ mt7530_mdio_w32(gsw, 0x7a5c, 0x44);
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+ mt7530_mdio_w32(gsw, 0x7a64, 0x44);
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+ mt7530_mdio_w32(gsw, 0x7a6c, 0x44);
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+ mt7530_mdio_w32(gsw, 0x7a74, 0x44);
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+ mt7530_mdio_w32(gsw, 0x7a7c, 0x44);
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+
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+ /* turn on all PHYs */
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+ for (i = 0; i <= 4; i++) {
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+ val = _mt7620_mii_read(gsw, i, 0);
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+ val &= ~BIT(11);
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+ _mt7620_mii_write(gsw, i, 0, val);
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+ }
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+
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+ /* enable irq */
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+ val = mt7530_mdio_r32(gsw, 0x7808);
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+ val |= 3 << 16;
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+ mt7530_mdio_w32(gsw, 0x7808, val);
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+}
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+
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+static const struct of_device_id mediatek_gsw_match[] = {
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+ { .compatible = "mediatek,mt7621-gsw" },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
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+
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+int mtk_gsw_init(struct fe_priv *priv)
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+{
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+ struct device_node *np = priv->switch_np;
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+ struct platform_device *pdev = of_find_device_by_node(np);
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+ struct mt7620_gsw *gsw;
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+
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+ if (!pdev)
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+ return -ENODEV;
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+
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+ if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
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+ return -EINVAL;
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+
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+ gsw = platform_get_drvdata(pdev);
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+ priv->soc->swpriv = gsw;
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+
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+ mt7621_hw_init(gsw, np);
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+
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+ if (gsw->irq) {
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+ request_irq(gsw->irq, gsw_interrupt_mt7621, 0,
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+ "gsw", priv);
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+ mt7530_mdio_w32(gsw, 0x7008, 0x1f);
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+ }
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+
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+ return 0;
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+}
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+
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+static int mt7621_gsw_probe(struct platform_device *pdev)
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+{
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+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ const char *port4 = NULL;
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+ struct mt7620_gsw *gsw;
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+ struct device_node *np;
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+
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+ gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
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+ if (!gsw)
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+ return -ENOMEM;
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+
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+ gsw->base = devm_ioremap_resource(&pdev->dev, res);
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+ if (!gsw->base)
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+ return -EADDRNOTAVAIL;
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+
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+ gsw->dev = &pdev->dev;
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+
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+ of_property_read_string(np, "mediatek,port4", &port4);
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+ if (port4 && !strcmp(port4, "ephy"))
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+ gsw->port4 = PORT4_EPHY;
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+ else if (port4 && !strcmp(port4, "gmac"))
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+ gsw->port4 = PORT4_EXT;
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+ else
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+ gsw->port4 = PORT4_EPHY;
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+
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+ gsw->irq = irq_of_parse_and_map(np, 0);
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+
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+ platform_set_drvdata(pdev, gsw);
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+
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+ return 0;
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+}
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+
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+static int mt7621_gsw_remove(struct platform_device *pdev)
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+{
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+ platform_set_drvdata(pdev, NULL);
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+
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+ return 0;
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+}
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+
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+static struct platform_driver gsw_driver = {
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+ .probe = mt7621_gsw_probe,
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+ .remove = mt7621_gsw_remove,
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+ .driver = {
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+ .name = "mt7621-gsw",
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+ .owner = THIS_MODULE,
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+ .of_match_table = mediatek_gsw_match,
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+ },
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+};
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+
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+module_platform_driver(gsw_driver);
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+
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+MODULE_LICENSE("GPL");
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+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
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+MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7621 SoC");
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+MODULE_VERSION(MTK_FE_DRV_VERSION);
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