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50 lines
1.6 KiB
Diff
50 lines
1.6 KiB
Diff
commit 78a54c4d8e5a7915a4ec2ba0eb461fae50590683
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Author: Paul Burton <paul.burton@imgtec.com>
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Date: Tue Sep 22 11:12:18 2015 -0700
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MIPS: CM, CPC: Ensure core-other GCRs reflect the correct core
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Ensure the update to which core the core-other GCR regions reflect has
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taken place before any core-other GCRs are accessed by placing a memory
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barrier (sync instruction) between the write to the core-other registers
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and any such GCR accesses.
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Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Cc: linux-mips@linux-mips.org
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Cc: Bjorn Helgaas <bhelgaas@google.com>
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Cc: linux-kernel@vger.kernel.org
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Cc: Markos Chandras <markos.chandras@imgtec.com>
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Patchwork: https://patchwork.linux-mips.org/patch/11209/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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--- a/arch/mips/kernel/mips-cm.c
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+++ b/arch/mips/kernel/mips-cm.c
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@@ -278,6 +278,12 @@ void mips_cm_lock_other(unsigned int cor
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}
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write_gcr_cl_other(val);
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+
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+ /*
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+ * Ensure the core-other region reflects the appropriate core &
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+ * VP before any accesses to it occur.
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+ */
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+ mb();
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}
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void mips_cm_unlock_other(void)
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--- a/arch/mips/kernel/mips-cpc.c
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+++ b/arch/mips/kernel/mips-cpc.c
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@@ -76,6 +76,12 @@ void mips_cpc_lock_other(unsigned int co
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spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core),
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per_cpu(cpc_core_lock_flags, curr_core));
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write_cpc_cl_other(core << CPC_Cx_OTHER_CORENUM_SHF);
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+
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+ /*
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+ * Ensure the core-other region reflects the appropriate core &
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+ * VP before any accesses to it occur.
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+ */
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+ mb();
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}
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void mips_cpc_unlock_other(void)
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