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438 lines
12 KiB
Diff
438 lines
12 KiB
Diff
From 450b6e8257e22708173d0c1c86d34394fba0c5eb Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 7 Dec 2015 17:08:31 +0100
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Subject: [PATCH 01/53] arch: mips: ralink: add mt7621 support
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/include/asm/mach-ralink/irq.h | 9 +
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arch/mips/include/asm/mach-ralink/mt7621.h | 39 ++++
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arch/mips/kernel/mips-cm.c | 4 +-
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arch/mips/kernel/vmlinux.lds.S | 1 +
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arch/mips/ralink/Kconfig | 18 ++
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arch/mips/ralink/Makefile | 7 +-
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arch/mips/ralink/Platform | 5 +
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arch/mips/ralink/irq-gic.c | 268 ++++++++++++++++++++++++++++
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arch/mips/ralink/malta-amon.c | 81 +++++++++
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arch/mips/ralink/mt7621.c | 209 ++++++++++++++++++++++
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10 files changed, 638 insertions(+), 3 deletions(-)
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create mode 100644 arch/mips/include/asm/mach-ralink/irq.h
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create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
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create mode 100644 arch/mips/ralink/irq-gic.c
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create mode 100644 arch/mips/ralink/malta-amon.c
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create mode 100644 arch/mips/ralink/mt7621.c
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-ralink/irq.h
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@@ -0,0 +1,9 @@
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+#ifndef __ASM_MACH_RALINK_IRQ_H
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+#define __ASM_MACH_RALINK_IRQ_H
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+
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+#define GIC_NUM_INTRS 64
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+#define NR_IRQS 256
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+
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+#include_next <irq.h>
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+
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+#endif
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-ralink/mt7621.h
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@@ -0,0 +1,42 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Parts of this file are based on Ralink's 2.6.21 BSP
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+ *
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+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#ifndef _MT7621_REGS_H_
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+#define _MT7621_REGS_H_
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+
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+#define MT7621_PALMBUS_BASE 0x1C000000
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+#define MT7621_PALMBUS_SIZE 0x03FFFFFF
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+
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+#define MT7621_SYSC_BASE 0x1E000000
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+
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+#define SYSC_REG_CHIP_NAME0 0x00
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+#define SYSC_REG_CHIP_NAME1 0x04
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+#define SYSC_REG_CHIP_REV 0x0c
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+#define SYSC_REG_SYSTEM_CONFIG0 0x10
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+#define SYSC_REG_SYSTEM_CONFIG1 0x14
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+
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+#define CHIP_REV_PKG_MASK 0x1
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+#define CHIP_REV_PKG_SHIFT 16
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+#define CHIP_REV_VER_MASK 0xf
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+#define CHIP_REV_VER_SHIFT 8
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+#define CHIP_REV_ECO_MASK 0xf
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+
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+#define MT7621_DRAM_BASE 0x0
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+#define MT7621_DDR2_SIZE_MIN 32
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+#define MT7621_DDR2_SIZE_MAX 256
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+
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+#define MT7621_CHIP_NAME0 0x3637544D
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+#define MT7621_CHIP_NAME1 0x20203132
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+
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+#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
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+
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+#endif
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--- a/arch/mips/kernel/vmlinux.lds.S
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+++ b/arch/mips/kernel/vmlinux.lds.S
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@@ -51,6 +51,7 @@ SECTIONS
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/* read-only */
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_text = .; /* Text and read-only data */
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.text : {
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+ /*. = . + 0x8000; */
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TEXT_TEXT
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SCHED_TEXT
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LOCK_TEXT
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--- a/arch/mips/ralink/Kconfig
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+++ b/arch/mips/ralink/Kconfig
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@@ -12,6 +12,11 @@ config RALINK_ILL_ACC
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depends on SOC_RT305X
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default y
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+config IRQ_INTC
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+ bool
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+ default y
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+ depends on !SOC_MT7621
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+
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choice
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prompt "Ralink SoC selection"
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default SOC_RT305X
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@@ -34,6 +39,16 @@ choice
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config SOC_MT7620
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bool "MT7620/8"
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+ config SOC_MT7621
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+ bool "MT7621"
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+ select MIPS_CPU_SCACHE
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+ select SYS_SUPPORTS_MULTITHREADING
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+ select SYS_SUPPORTS_SMP
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+ select SYS_SUPPORTS_MIPS_CPS
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+ select MIPS_GIC
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+ select COMMON_CLK
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+ select CLKSRC_MIPS_GIC
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+ select HW_HAS_PCI
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endchoice
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choice
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@@ -65,6 +80,10 @@ choice
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depends on SOC_MT7620
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select BUILTIN_DTB
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+ config DTB_MT7621_EVAL
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+ bool "MT7621 eval kit"
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+ depends on SOC_MT7621
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+
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endchoice
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endif
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--- a/arch/mips/ralink/Makefile
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+++ b/arch/mips/ralink/Makefile
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@@ -6,16 +6,24 @@
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# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
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# Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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-obj-y := prom.o of.o reset.o clk.o irq.o timer.o
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+obj-y := prom.o of.o reset.o
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+
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+ifndef CONFIG_MIPS_GIC
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+ obj-y += clk.o timer.o
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+endif
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obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
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obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
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+obj-$(CONFIG_IRQ_INTC) += irq.o
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+obj-$(CONFIG_MIPS_GIC) += irq-gic.o timer-gic.o
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+
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obj-$(CONFIG_SOC_RT288X) += rt288x.o
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obj-$(CONFIG_SOC_RT305X) += rt305x.o
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obj-$(CONFIG_SOC_RT3883) += rt3883.o
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obj-$(CONFIG_SOC_MT7620) += mt7620.o
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+obj-$(CONFIG_SOC_MT7621) += mt7621.o
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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--- a/arch/mips/ralink/Platform
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+++ b/arch/mips/ralink/Platform
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@@ -27,3 +27,8 @@ cflags-$(CONFIG_SOC_RT3883) += -I$(srctr
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#
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load-$(CONFIG_SOC_MT7620) += 0xffffffff80000000
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cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7620
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+
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+# Ralink MT7621
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+#
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+load-$(CONFIG_SOC_MT7621) += 0xffffffff80001000
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+cflags-$(CONFIG_SOC_MT7621) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
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--- /dev/null
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+++ b/arch/mips/ralink/irq-gic.c
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@@ -0,0 +1,18 @@
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+#include <linux/init.h>
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+
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+#include <linux/of.h>
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+#include <linux/irqchip.h>
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+#include <linux/irqchip/mips-gic.h>
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+
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+int get_c0_perfcount_int(void)
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+{
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+ return gic_get_c0_perfcount_int();
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+}
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+EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
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+
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+void __init
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+arch_init_irq(void)
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+{
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+ irqchip_init();
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+}
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+
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--- /dev/null
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+++ b/arch/mips/ralink/mt7621.c
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@@ -0,0 +1,223 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Parts of this file are based on Ralink's 2.6.21 BSP
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+ *
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+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/module.h>
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+
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+#include <asm/mipsregs.h>
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+#include <asm/smp-ops.h>
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+#include <asm/mips-cm.h>
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+#include <asm/mips-cpc.h>
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+#include <asm/mach-ralink/ralink_regs.h>
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+#include <asm/mach-ralink/mt7621.h>
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+
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+#include <pinmux.h>
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+
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+#include "common.h"
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+
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+#define SYSC_REG_SYSCFG 0x10
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+#define SYSC_REG_CPLL_CLKCFG0 0x2c
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+#define SYSC_REG_CUR_CLK_STS 0x44
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+#define CPU_CLK_SEL (BIT(30) | BIT(31))
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+
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+#define MT7621_GPIO_MODE_UART1 1
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+#define MT7621_GPIO_MODE_I2C 2
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+#define MT7621_GPIO_MODE_UART3_MASK 0x3
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+#define MT7621_GPIO_MODE_UART3_SHIFT 3
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+#define MT7621_GPIO_MODE_UART3_GPIO 1
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+#define MT7621_GPIO_MODE_UART2_MASK 0x3
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+#define MT7621_GPIO_MODE_UART2_SHIFT 5
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+#define MT7621_GPIO_MODE_UART2_GPIO 1
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+#define MT7621_GPIO_MODE_JTAG 7
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+#define MT7621_GPIO_MODE_WDT_MASK 0x3
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+#define MT7621_GPIO_MODE_WDT_SHIFT 8
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+#define MT7621_GPIO_MODE_WDT_GPIO 1
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+#define MT7621_GPIO_MODE_PCIE_RST 0
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+#define MT7621_GPIO_MODE_PCIE_REF 2
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+#define MT7621_GPIO_MODE_PCIE_MASK 0x3
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+#define MT7621_GPIO_MODE_PCIE_SHIFT 10
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+#define MT7621_GPIO_MODE_PCIE_GPIO 1
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+#define MT7621_GPIO_MODE_MDIO_MASK 0x3
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+#define MT7621_GPIO_MODE_MDIO_SHIFT 12
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+#define MT7621_GPIO_MODE_MDIO_GPIO 1
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+#define MT7621_GPIO_MODE_RGMII1 14
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+#define MT7621_GPIO_MODE_RGMII2 15
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+#define MT7621_GPIO_MODE_SPI_MASK 0x3
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+#define MT7621_GPIO_MODE_SPI_SHIFT 16
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+#define MT7621_GPIO_MODE_SPI_GPIO 1
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+#define MT7621_GPIO_MODE_SDHCI_MASK 0x3
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+#define MT7621_GPIO_MODE_SDHCI_SHIFT 18
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+#define MT7621_GPIO_MODE_SDHCI_GPIO 1
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+
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+static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) };
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+static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) };
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+static struct rt2880_pmx_func uart3_grp[] = {
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+ FUNC("uart3", 0, 5, 4),
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+ FUNC("i2s", 2, 5, 4),
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+ FUNC("spdif3", 3, 5, 4),
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+};
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+static struct rt2880_pmx_func uart2_grp[] = {
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+ FUNC("uart2", 0, 9, 4),
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+ FUNC("pcm", 2, 9, 4),
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+ FUNC("spdif2", 3, 9, 4),
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+};
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+static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
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+static struct rt2880_pmx_func wdt_grp[] = {
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+ FUNC("wdt rst", 0, 18, 1),
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+ FUNC("wdt refclk", 2, 18, 1),
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+};
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+static struct rt2880_pmx_func pcie_rst_grp[] = {
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+ FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),
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+ FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)
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+};
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+static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };
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+static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };
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+static struct rt2880_pmx_func spi_grp[] = {
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+ FUNC("spi", 0, 34, 7),
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+ FUNC("nand1", 2, 34, 7),
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+};
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+static struct rt2880_pmx_func sdhci_grp[] = {
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+ FUNC("sdhci", 0, 41, 8),
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+ FUNC("nand2", 2, 41, 8),
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+};
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+static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };
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+
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+static struct rt2880_pmx_group mt7621_pinmux_data[] = {
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+ GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
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+ GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
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+ GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,
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+ MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),
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+ GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,
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+ MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),
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+ GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
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+ GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
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+ MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),
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+ GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,
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+ MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),
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+ GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,
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+ MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),
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+ GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),
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+ GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,
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+ MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),
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+ GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
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+ MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),
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+ GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),
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+ { 0 }
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+};
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+
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+phys_addr_t mips_cpc_default_phys_base() {
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+ panic("Cannot detect cpc address");
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+}
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+
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+void __init ralink_clk_init(void)
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+{
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+ int cpu_fdiv = 0;
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+ int cpu_ffrac = 0;
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+ int fbdiv = 0;
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+ u32 clk_sts, syscfg;
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+ u8 clk_sel = 0, xtal_mode;
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+ u32 cpu_clk;
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+
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+ if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0)
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+ clk_sel = 1;
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+
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+ switch (clk_sel) {
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+ case 0:
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+ clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
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+ cpu_fdiv = ((clk_sts >> 8) & 0x1F);
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+ cpu_ffrac = (clk_sts & 0x1F);
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+ cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
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+ break;
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+
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+ case 1:
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+ fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
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+ syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
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+ xtal_mode = (syscfg >> 6) & 0x7;
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+ if(xtal_mode >= 6) { //25Mhz Xtal
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+ cpu_clk = 25 * fbdiv * 1000 * 1000;
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+ } else if(xtal_mode >=3) { //40Mhz Xtal
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+ cpu_clk = 40 * fbdiv * 1000 * 1000;
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+ } else { // 20Mhz Xtal
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+ cpu_clk = 20 * fbdiv * 1000 * 1000;
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+ }
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+ break;
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+ }
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+}
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+
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+void __init ralink_of_remap(void)
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+{
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+ rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
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+ rt_memc_membase = plat_of_remap_node("mtk,mt7621-memc");
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+
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+ if (!rt_sysc_membase || !rt_memc_membase)
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+ panic("Failed to remap core resources");
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+}
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+
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+void prom_soc_init(struct ralink_soc_info *soc_info)
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+{
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+ void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
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+ unsigned char *name = NULL;
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+ u32 n0;
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+ u32 n1;
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+ u32 rev;
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+
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+ n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
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+ n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
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+
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+ if (n0 == MT7621_CHIP_NAME0 && n1 == MT7621_CHIP_NAME1) {
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+ name = "MT7621";
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+ soc_info->compatible = "mtk,mt7621-soc";
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+ } else {
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+ panic("mt7621: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
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+ }
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+
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+ rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
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+
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+ snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
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+ "MediaTek %s ver:%u eco:%u",
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+ name,
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+ (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
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+ (rev & CHIP_REV_ECO_MASK));
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+
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+ soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
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+ soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
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+ soc_info->mem_base = MT7621_DRAM_BASE;
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+
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+ rt2880_pinmux_data = mt7621_pinmux_data;
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+
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+ /* Early detection of CMP support */
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+ mips_cm_probe();
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+ mips_cpc_probe();
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+
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+ if (mips_cm_numiocu()) {
|
|
+ /* mips_cm_probe() wipes out bootloader
|
|
+ config for CM regions and we have to configure them
|
|
+ again. This SoC cannot talk to pamlbus devices
|
|
+ witout proper iocu region set up.
|
|
+
|
|
+ FIXME: it would be better to do this with values
|
|
+ from DT, but we need this very early because
|
|
+ without this we cannot talk to pretty much anything
|
|
+ including serial.
|
|
+ */
|
|
+ write_gcr_reg0_base(MT7621_PALMBUS_BASE);
|
|
+ write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE | CM_GCR_REGn_MASK_CMTGT_IOCU0);
|
|
+ }
|
|
+
|
|
+ if (!register_cps_smp_ops())
|
|
+ return;
|
|
+ if (!register_cmp_smp_ops())
|
|
+ return;
|
|
+ if (!register_vsmp_smp_ops())
|
|
+ return;
|
|
+}
|
|
--- /dev/null
|
|
+++ b/arch/mips/ralink/timer-gic.c
|
|
@@ -0,0 +1,15 @@
|
|
+#include <linux/init.h>
|
|
+
|
|
+#include <linux/of.h>
|
|
+#include <linux/clk-provider.h>
|
|
+#include <linux/clocksource.h>
|
|
+
|
|
+#include "common.h"
|
|
+
|
|
+void __init plat_time_init(void)
|
|
+{
|
|
+ ralink_of_remap();
|
|
+
|
|
+ of_clk_init(NULL);
|
|
+ clocksource_of_init();
|
|
+}
|