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211 lines
4.5 KiB
Diff
211 lines
4.5 KiB
Diff
From 661edd663841d94bded4e95acfd0a4947cb079b5 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Wed, 12 Feb 2020 12:26:40 +0100
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Subject: [PATCH] ARM: dts: bcm2711: Enable the display pipeline
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Now that all the drivers have been adjusted for it, let's bring in the
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necessary device tree changes.
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 40 ++++++++++
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arch/arm/boot/dts/bcm2711.dtsi | 110 ++++++++++++++++++++++++++
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2 files changed, 150 insertions(+)
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--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
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+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
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@@ -138,6 +138,46 @@
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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};
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+&vc4 {
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+ status = "okay";
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+};
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+
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+&pixelvalve0 {
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+ status = "okay";
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+};
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+
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+&pixelvalve1 {
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+ status = "okay";
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+};
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+
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+&pixelvalve2 {
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+ status = "okay";
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+};
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+
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+&pixelvalve3 {
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+ status = "okay";
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+};
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+
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+&pixelvalve4 {
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+ status = "okay";
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+};
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+
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+&hdmi0 {
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+ status = "okay";
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+};
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+
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+&ddc0 {
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+ status = "okay";
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+};
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+
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+&hdmi1 {
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+ status = "okay";
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+};
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+
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+&ddc1 {
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+ status = "okay";
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+};
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+
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// =============================================
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// Downstream rpi- changes
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--- a/arch/arm/boot/dts/bcm2711.dtsi
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+++ b/arch/arm/boot/dts/bcm2711.dtsi
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@@ -31,6 +31,11 @@
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};
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};
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+ vc4: gpu {
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+ compatible = "brcm,bcm2711-vc5";
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+ status = "disabled";
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+ };
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+
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clk_108MHz: clk-108M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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@@ -254,6 +259,27 @@
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status = "disabled";
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};
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+ pixelvalve0: pixelvalve@7e206000 {
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+ compatible = "brcm,bcm2711-pixelvalve0";
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+ reg = <0x7e206000 0x100>;
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+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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+ pixelvalve1: pixelvalve@7e207000 {
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+ compatible = "brcm,bcm2711-pixelvalve1";
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+ reg = <0x7e207000 0x100>;
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+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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+ pixelvalve2: pixelvalve@7e20a000 {
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+ compatible = "brcm,bcm2711-pixelvalve2";
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+ reg = <0x7e20a000 0x100>;
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+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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pwm1: pwm@7e20c800 {
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compatible = "brcm,bcm2835-pwm";
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reg = <0x7e20c800 0x28>;
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@@ -264,6 +290,13 @@
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status = "disabled";
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};
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+ pixelvalve4: pixelvalve@7e216000 {
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+ compatible = "brcm,bcm2711-pixelvalve4";
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+ reg = <0x7e216000 0x100>;
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+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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emmc2: emmc2@7e340000 {
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compatible = "brcm,bcm2711-emmc2";
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reg = <0x7e340000 0x100>;
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@@ -276,6 +309,13 @@
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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};
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+ pixelvalve3: pixelvalve@7ec12000 {
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+ compatible = "brcm,bcm2711-pixelvalve3";
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+ reg = <0x7ec12000 0x100>;
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+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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dvp: clock@7ef00000 {
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compatible = "brcm,brcm2711-dvp";
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reg = <0x7ef00000 0x10>;
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@@ -283,6 +323,76 @@
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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+
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+ hdmi0: hdmi@7ef00700 {
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+ compatible = "brcm,bcm2711-hdmi0";
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+ reg = <0x7ef00700 0x300>,
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+ <0x7ef00300 0x200>,
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+ <0x7ef00f00 0x80>,
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+ <0x7ef00f80 0x80>,
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+ <0x7ef01b00 0x200>,
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+ <0x7ef01f00 0x400>,
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+ <0x7ef00200 0x80>,
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+ <0x7ef04300 0x100>,
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+ <0x7ef20000 0x100>;
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+ reg-names = "hdmi",
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+ "dvp",
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+ "phy",
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+ "rm",
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+ "packet",
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+ "metadata",
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+ "csc",
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+ "cec",
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+ "hd";
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+ clocks = <&firmware_clocks 13>;
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+ clock-names = "hdmi";
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+ resets = <&dvp 0>;
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+ ddc = <&ddc0>;
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+ status = "disabled";
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+ };
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+
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+ ddc0: i2c@7ef04500 {
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+ compatible = "brcm,bcm2711-hdmi-i2c";
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+ reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
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+ reg-names = "bsc", "auto-i2c";
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+ clock-frequency = <390000>;
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+ status = "disabled";
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+ };
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+
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+ hdmi1: hdmi@7ef05700 {
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+ compatible = "brcm,bcm2711-hdmi1";
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+ reg = <0x7ef05700 0x300>,
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+ <0x7ef05300 0x200>,
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+ <0x7ef05f00 0x80>,
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+ <0x7ef05f80 0x80>,
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+ <0x7ef06b00 0x200>,
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+ <0x7ef06f00 0x400>,
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+ <0x7ef00280 0x80>,
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+ <0x7ef09300 0x100>,
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+ <0x7ef20000 0x100>;
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+ reg-names = "hdmi",
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+ "dvp",
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+ "phy",
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+ "rm",
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+ "packet",
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+ "metadata",
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+ "csc",
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+ "cec",
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+ "hd";
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+ ddc = <&ddc1>;
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+ clocks = <&firmware_clocks 13>;
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+ clock-names = "hdmi";
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+ resets = <&dvp 1>;
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+ status = "disabled";
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+ };
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+
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+ ddc1: i2c@7ef09500 {
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+ compatible = "brcm,bcm2711-hdmi-i2c";
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+ reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
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+ reg-names = "bsc", "auto-i2c";
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+ clock-frequency = <390000>;
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+ status = "disabled";
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+ };
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};
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arm-pmu {
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