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384 lines
11 KiB
Diff
384 lines
11 KiB
Diff
From 1a90ecdfae1c0cf1b242276f6f0e3d98b5877f14 Mon Sep 17 00:00:00 2001
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From: Jim Quinlan <james.quinlan@broadcom.com>
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Date: Mon, 16 Dec 2019 12:01:10 +0100
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Subject: [PATCH] PCI: brcmstb: Add MSI support
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commit 40ca1bf580ef24df30702032ba5e40dfdcaa200b upstream.
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This adds MSI support to the Broadcom STB PCIe host controller. The MSI
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controller is physically located within the PCIe block, however, there
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is no reason why the MSI controller could not be moved elsewhere in the
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future. MSIX is not supported by the HW.
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Since the internal Brcmstb MSI controller is intertwined with the PCIe
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controller, it is not its own platform device but rather part of the
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PCIe platform device.
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Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
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Co-developed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
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Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
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Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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Reviewed-by: Marc Zyngier <maz@kernel.org>
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Reviewed-by: Andrew Murray <andrew.murray@arm.com>
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---
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drivers/pci/controller/Kconfig | 1 +
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drivers/pci/controller/pcie-brcmstb.c | 262 +++++++++++++++++++++++++-
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2 files changed, 262 insertions(+), 1 deletion(-)
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--- a/drivers/pci/controller/Kconfig
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+++ b/drivers/pci/controller/Kconfig
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@@ -285,6 +285,7 @@ config PCIE_BRCMSTB
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tristate "Broadcom Brcmstb PCIe host controller"
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depends on ARCH_BCM2835 || COMPILE_TEST
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depends on OF
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+ depends on PCI_MSI_IRQ_DOMAIN
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help
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Say Y here to enable PCIe host controller support for
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Broadcom STB based SoCs, like the Raspberry Pi 4.
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--- a/drivers/pci/controller/pcie-brcmstb.c
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+++ b/drivers/pci/controller/pcie-brcmstb.c
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@@ -2,6 +2,7 @@
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/* Copyright (C) 2009 - 2019 Broadcom */
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#include <linux/bitfield.h>
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+#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/compiler.h>
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#include <linux/delay.h>
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@@ -9,11 +10,13 @@
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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+#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/log2.h>
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#include <linux/module.h>
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+#include <linux/msi.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_pci.h>
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@@ -67,6 +70,12 @@
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#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
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#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
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+#define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
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+#define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
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+
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+#define PCIE_MISC_MSI_DATA_CONFIG 0x404c
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+#define PCIE_MISC_MSI_DATA_CONFIG_VAL 0xffe06540
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+
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#define PCIE_MISC_PCIE_CTRL 0x4064
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#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
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@@ -114,6 +123,11 @@
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/* PCIe parameters */
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#define BRCM_NUM_PCIE_OUT_WINS 0x4
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+#define BRCM_INT_PCI_MSI_NR 32
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+
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+/* MSI target adresses */
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+#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
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+#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
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/* MDIO registers */
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#define MDIO_PORT0 0x0
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@@ -135,6 +149,19 @@
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#define SSC_STATUS_SSC_MASK 0x400
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#define SSC_STATUS_PLL_LOCK_MASK 0x800
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+struct brcm_msi {
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+ struct device *dev;
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+ void __iomem *base;
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+ struct device_node *np;
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+ struct irq_domain *msi_domain;
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+ struct irq_domain *inner_domain;
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+ struct mutex lock; /* guards the alloc/free operations */
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+ u64 target_addr;
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+ int irq;
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+ /* used indicates which MSI interrupts have been alloc'd */
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+ unsigned long used;
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+};
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+
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/* Internal PCIe Host Controller Information.*/
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struct brcm_pcie {
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struct device *dev;
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@@ -144,6 +171,8 @@ struct brcm_pcie {
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struct device_node *np;
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bool ssc;
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int gen;
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+ u64 msi_target_addr;
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+ struct brcm_msi *msi;
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};
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/*
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@@ -309,6 +338,215 @@ static void brcm_pcie_set_outbound_win(s
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writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
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}
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+static struct irq_chip brcm_msi_irq_chip = {
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+ .name = "BRCM STB PCIe MSI",
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+ .irq_ack = irq_chip_ack_parent,
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+ .irq_mask = pci_msi_mask_irq,
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+ .irq_unmask = pci_msi_unmask_irq,
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+};
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+
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+static struct msi_domain_info brcm_msi_domain_info = {
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+ /* Multi MSI is supported by the controller, but not by this driver */
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+ .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
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+ .chip = &brcm_msi_irq_chip,
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+};
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+
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+static void brcm_pcie_msi_isr(struct irq_desc *desc)
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+{
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+ struct irq_chip *chip = irq_desc_get_chip(desc);
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+ unsigned long status, virq;
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+ struct brcm_msi *msi;
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+ struct device *dev;
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+ u32 bit;
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+
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+ chained_irq_enter(chip, desc);
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+ msi = irq_desc_get_handler_data(desc);
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+ dev = msi->dev;
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+
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+ status = readl(msi->base + PCIE_MSI_INTR2_STATUS);
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+ for_each_set_bit(bit, &status, BRCM_INT_PCI_MSI_NR) {
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+ virq = irq_find_mapping(msi->inner_domain, bit);
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+ if (virq)
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+ generic_handle_irq(virq);
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+ else
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+ dev_dbg(dev, "unexpected MSI\n");
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+ }
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+
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+ chained_irq_exit(chip, desc);
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+}
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+
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+static void brcm_msi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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+{
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+ struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
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+
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+ msg->address_lo = lower_32_bits(msi->target_addr);
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+ msg->address_hi = upper_32_bits(msi->target_addr);
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+ msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL) | data->hwirq;
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+}
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+
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+static int brcm_msi_set_affinity(struct irq_data *irq_data,
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+ const struct cpumask *mask, bool force)
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+{
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+ return -EINVAL;
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+}
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+
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+static void brcm_msi_ack_irq(struct irq_data *data)
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+{
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+ struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
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+
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+ writel(1 << data->hwirq, msi->base + PCIE_MSI_INTR2_CLR);
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+}
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+
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+
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+static struct irq_chip brcm_msi_bottom_irq_chip = {
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+ .name = "BRCM STB MSI",
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+ .irq_compose_msi_msg = brcm_msi_compose_msi_msg,
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+ .irq_set_affinity = brcm_msi_set_affinity,
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+ .irq_ack = brcm_msi_ack_irq,
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+};
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+
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+static int brcm_msi_alloc(struct brcm_msi *msi)
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+{
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+ int hwirq;
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+
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+ mutex_lock(&msi->lock);
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+ hwirq = bitmap_find_free_region(&msi->used, BRCM_INT_PCI_MSI_NR, 0);
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+ mutex_unlock(&msi->lock);
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+
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+ return hwirq;
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+}
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+
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+static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq)
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+{
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+ mutex_lock(&msi->lock);
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+ bitmap_release_region(&msi->used, hwirq, 0);
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+ mutex_unlock(&msi->lock);
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+}
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+
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+static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
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+ unsigned int nr_irqs, void *args)
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+{
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+ struct brcm_msi *msi = domain->host_data;
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+ int hwirq;
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+
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+ hwirq = brcm_msi_alloc(msi);
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+
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+ if (hwirq < 0)
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+ return hwirq;
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+
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+ irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq,
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+ &brcm_msi_bottom_irq_chip, domain->host_data,
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+ handle_edge_irq, NULL, NULL);
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+ return 0;
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+}
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+
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+static void brcm_irq_domain_free(struct irq_domain *domain,
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+ unsigned int virq, unsigned int nr_irqs)
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+{
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+ struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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+ struct brcm_msi *msi = irq_data_get_irq_chip_data(d);
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+
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+ brcm_msi_free(msi, d->hwirq);
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+}
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+
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+static const struct irq_domain_ops msi_domain_ops = {
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+ .alloc = brcm_irq_domain_alloc,
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+ .free = brcm_irq_domain_free,
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+};
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+
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+static int brcm_allocate_domains(struct brcm_msi *msi)
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+{
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+ struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np);
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+ struct device *dev = msi->dev;
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+
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+ msi->inner_domain = irq_domain_add_linear(NULL, BRCM_INT_PCI_MSI_NR,
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+ &msi_domain_ops, msi);
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+ if (!msi->inner_domain) {
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+ dev_err(dev, "failed to create IRQ domain\n");
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+ return -ENOMEM;
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+ }
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+
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+ msi->msi_domain = pci_msi_create_irq_domain(fwnode,
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+ &brcm_msi_domain_info,
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+ msi->inner_domain);
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+ if (!msi->msi_domain) {
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+ dev_err(dev, "failed to create MSI domain\n");
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+ irq_domain_remove(msi->inner_domain);
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+ return -ENOMEM;
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+ }
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+
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+ return 0;
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+}
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+
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+static void brcm_free_domains(struct brcm_msi *msi)
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+{
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+ irq_domain_remove(msi->msi_domain);
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+ irq_domain_remove(msi->inner_domain);
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+}
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+
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+static void brcm_msi_remove(struct brcm_pcie *pcie)
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+{
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+ struct brcm_msi *msi = pcie->msi;
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+
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+ if (!msi)
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+ return;
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+ irq_set_chained_handler(msi->irq, NULL);
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+ irq_set_handler_data(msi->irq, NULL);
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+ brcm_free_domains(msi);
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+}
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+
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+static void brcm_msi_set_regs(struct brcm_msi *msi)
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+{
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+ writel(0xffffffff, msi->base + PCIE_MSI_INTR2_MASK_CLR);
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+
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+ /*
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+ * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI
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+ * enable, which we set to 1.
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+ */
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+ writel(lower_32_bits(msi->target_addr) | 0x1,
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+ msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO);
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+ writel(upper_32_bits(msi->target_addr),
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+ msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI);
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+
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+ writel(PCIE_MISC_MSI_DATA_CONFIG_VAL,
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+ msi->base + PCIE_MISC_MSI_DATA_CONFIG);
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+}
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+
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+static int brcm_pcie_enable_msi(struct brcm_pcie *pcie)
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+{
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+ struct brcm_msi *msi;
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+ int irq, ret;
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+ struct device *dev = pcie->dev;
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+
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+ irq = irq_of_parse_and_map(dev->of_node, 1);
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+ if (irq <= 0) {
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+ dev_err(dev, "cannot map MSI interrupt\n");
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+ return -ENODEV;
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+ }
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+
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+ msi = devm_kzalloc(dev, sizeof(struct brcm_msi), GFP_KERNEL);
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+ if (!msi)
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+ return -ENOMEM;
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+
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+ mutex_init(&msi->lock);
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+ msi->dev = dev;
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+ msi->base = pcie->base;
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+ msi->np = pcie->np;
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+ msi->target_addr = pcie->msi_target_addr;
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+ msi->irq = irq;
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+
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+ ret = brcm_allocate_domains(msi);
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+ if (ret)
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+ return ret;
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+
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+ irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi);
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+
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+ brcm_msi_set_regs(msi);
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+ pcie->msi = msi;
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+
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+ return 0;
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+}
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+
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/* The controller is capable of serving in both RC and EP roles */
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static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
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{
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@@ -497,6 +735,18 @@ static int brcm_pcie_setup(struct brcm_p
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PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK);
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writel(tmp, base + PCIE_MISC_MISC_CTRL);
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+ /*
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+ * We ideally want the MSI target address to be located in the 32bit
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+ * addressable memory area. Some devices might depend on it. This is
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+ * possible either when the inbound window is located above the lower
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+ * 4GB or when the inbound area is smaller than 4GB (taking into
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+ * account the rounding-up we're forced to perform).
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+ */
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+ if (rc_bar2_offset >= SZ_4G || (rc_bar2_size + rc_bar2_offset) < SZ_4G)
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+ pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
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+ else
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+ pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB;
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+
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/* disable the PCIe->GISB memory window (RC_BAR1) */
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tmp = readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO);
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tmp &= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK;
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@@ -646,6 +896,7 @@ static void brcm_pcie_turn_off(struct br
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static void __brcm_pcie_remove(struct brcm_pcie *pcie)
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{
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+ brcm_msi_remove(pcie);
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brcm_pcie_turn_off(pcie);
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clk_disable_unprepare(pcie->clk);
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clk_put(pcie->clk);
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@@ -664,7 +915,7 @@ static int brcm_pcie_remove(struct platf
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static int brcm_pcie_probe(struct platform_device *pdev)
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{
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- struct device_node *np = pdev->dev.of_node;
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+ struct device_node *np = pdev->dev.of_node, *msi_np;
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struct pci_host_bridge *bridge;
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struct brcm_pcie *pcie;
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struct pci_bus *child;
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@@ -708,6 +959,15 @@ static int brcm_pcie_probe(struct platfo
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if (ret)
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goto fail;
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+ msi_np = of_parse_phandle(pcie->np, "msi-parent", 0);
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+ if (pci_msi_enabled() && msi_np == pcie->np) {
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+ ret = brcm_pcie_enable_msi(pcie);
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+ if (ret) {
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+ dev_err(pcie->dev, "probe of internal MSI failed");
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+ goto fail;
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+ }
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+ }
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+
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bridge->dev.parent = &pdev->dev;
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bridge->busnr = 0;
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bridge->ops = &brcm_pcie_ops;
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