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249 lines
6.4 KiB
Diff
249 lines
6.4 KiB
Diff
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
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index cfe288a..c528024 100644
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--- a/drivers/mtd/nand/Kconfig
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+++ b/drivers/mtd/nand/Kconfig
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@@ -55,6 +55,12 @@ config MTD_NAND_TOTO
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help
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Support for NAND flash on Texas Instruments Toto platform.
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+config MTD_NAND_RB500
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+ tristate "NAND Flash device on RB500 board"
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+ depends on MTD_NAND
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+ help
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+ Support for NAND flash on RB500 platform.
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+
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config MTD_NAND_IDS
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tristate
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diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
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index 4174202..2be57c1 100644
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--- a/drivers/mtd/nand/Makefile
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+++ b/drivers/mtd/nand/Makefile
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@@ -8,6 +8,7 @@ obj-$(CONFIG_MTD_NAND_IDS) += nand_ids.
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obj-$(CONFIG_MTD_NAND_SPIA) += spia.o
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obj-$(CONFIG_MTD_NAND_TOTO) += toto.o
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+obj-$(CONFIG_MTD_NAND_RB500) += rbmipsnand.o
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obj-$(CONFIG_MTD_NAND_AUTCPU12) += autcpu12.o
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obj-$(CONFIG_MTD_NAND_EDB7312) += edb7312.o
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obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o
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diff --git a/drivers/mtd/nand/rbmipsnand.c b/drivers/mtd/nand/rbmipsnand.c
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new file mode 100644
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index 0000000..6f7452a
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--- /dev/null
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+++ b/drivers/mtd/nand/rbmipsnand.c
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@@ -0,0 +1,211 @@
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+#include <linux/init.h>
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+#include <linux/mtd/nand.h>
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+#include <linux/mtd/mtd.h>
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+#include <linux/mtd/partitions.h>
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+#include <linux/delay.h>
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+#include <asm/io.h>
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+#include <asm/irq.h>
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+#include <asm/bootinfo.h>
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+//#include <asm/rb/rb100.h>
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+
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+#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
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+
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+#define SMEM1(x) (*((volatile unsigned char *) (KSEG1ADDR(SMEM1_BASE) + x)))
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+
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+#define GPIOF 0x050000
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+#define GPIOC 0x050004
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+#define GPIOD 0x050008
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+
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+#define GPIO_RDY (1 << 0x08)
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+#define GPIO_WPX (1 << 0x09)
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+#define GPIO_ALE (1 << 0x0a)
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+#define GPIO_CLE (1 << 0x0b)
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+
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+#define NAND_RW_REG 0x0 //data register
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+#define NAND_SET_CEn 0x1 //CE# low
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+#define NAND_CLR_CEn 0x2 //CE# high
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+#define NAND_CLR_CLE 0x3 //CLE low
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+#define NAND_SET_CLE 0x4 //CLE high
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+#define NAND_CLR_ALE 0x5 //ALE low
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+#define NAND_SET_ALE 0x6 //ALE high
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+#define NAND_SET_SPn 0x7 //SP# low (use spare area)
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+#define NAND_CLR_SPn 0x8 //SP# high (do not use spare area)
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+#define NAND_SET_WPn 0x9 //WP# low
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+#define NAND_CLR_WPn 0xA //WP# high
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+#define NAND_STS_REG 0xB //Status register
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+
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+#define DEV2BASE 0x010020
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+
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+#define LO_WPX (1 << 0)
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+#define LO_ALE (1 << 1)
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+#define LO_CLE (1 << 2)
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+#define LO_CEX (1 << 3)
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+#define LO_FOFF (1 << 5)
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+#define LO_SPICS (1 << 6)
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+#define LO_ULED (1 << 7)
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+
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+#define MEM32(x) *((volatile unsigned *) (x))
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+static void __iomem *p_nand;
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+
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+extern void changeLatchU5(unsigned char orMask, unsigned char nandMask);
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+
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+static int rb500_dev_ready(struct mtd_info *mtd) {
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+ return MEM32(IDT434_REG_BASE + GPIOD) & GPIO_RDY;
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+}
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+/*
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+static int rb100_dev_ready(struct mtd_info *mtd) {
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+ return SMEM1(NAND_STS_REG) & 0x80;
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+}
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+*/
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+static unsigned long iflags = 0;
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+static int ioff = 0;
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+/*
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+static void rbmips_hwcontrol400(struct mtd_info *mtd, int cmd) {
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+ switch (cmd) {
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+ case NAND_CTL_SETCLE:
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+ MEM32(IDT434_REG_BASE + GPIOD) |= GPIO_CLE;
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+ break;
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+ case NAND_CTL_CLRCLE:
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+ MEM32(IDT434_REG_BASE + GPIOD) &= ~GPIO_CLE;
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+ break;
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+ case NAND_CTL_SETALE:
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+ MEM32(IDT434_REG_BASE + GPIOD) |= GPIO_ALE;
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+ break;
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+ case NAND_CTL_CLRALE:
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+ MEM32(IDT434_REG_BASE + GPIOD) &= ~GPIO_ALE;
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+ break;
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+ default:
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+ break;
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+ }
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+}
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+*/
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+static void rbmips_hwcontrol500(struct mtd_info *mtd, int cmd) {
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+ switch (cmd) {
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+ case NAND_CTL_SETCLE:
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+ changeLatchU5(LO_CLE, 0);
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+ break;
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+ case NAND_CTL_CLRCLE:
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+ changeLatchU5(0, LO_CLE);
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+ break;
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+ case NAND_CTL_SETALE:
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+ changeLatchU5(LO_ALE, 0);
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+ break;
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+ case NAND_CTL_CLRALE:
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+ changeLatchU5(0, LO_ALE);
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+ break;
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+ default:
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+ break;
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+ }
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+}
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+/*
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+static void rbmips_hwcontrol100(struct mtd_info *mtd, int cmd){
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+ switch(cmd){
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+ case NAND_CTL_SETCLE:
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+ SMEM1(NAND_SET_CLE) = 0x01;
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+ break;
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+ case NAND_CTL_CLRCLE:
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+ SMEM1(NAND_CLR_CLE) = 0x01;
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+ break;
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+ case NAND_CTL_SETALE:
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+ SMEM1(NAND_SET_ALE) = 0x01;
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+ break;
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+ case NAND_CTL_CLRALE:
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+ SMEM1(NAND_CLR_ALE) = 0x01;
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+ break;
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+ case NAND_CTL_SETNCE:
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+ SMEM1(NAND_SET_CEn) = 0x01;
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+ break;
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+ case NAND_CTL_CLRNCE:
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+ SMEM1(NAND_CLR_CEn) = 0x01;
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+ break;
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+ }
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+}
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+*/
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+static struct mtd_partition partition_info[] = {
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+ {
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+ name: "RouterBoard NAND Boot",
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+ offset: 0,
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+ size: 4 * 1024 * 1024
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+ },
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+ {
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+ name: "RouterBoard NAND Main",
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+ offset: MTDPART_OFS_NXTBLK,
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+ size: MTDPART_SIZ_FULL
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+ }
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+};
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+
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+static struct mtd_info rmtd;
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+static struct nand_chip rnand;
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+
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+static unsigned init_ok = 0;
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+
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+unsigned get_rbnand_block_size(void) {
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+ if (init_ok) return rmtd.oobblock; else return 0;
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+}
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+
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+EXPORT_SYMBOL(get_rbnand_block_size);
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+
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+int __init rbmips_init(void) {
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+ memset(&rmtd, 0, sizeof(rmtd));
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+ memset(&rnand, 0, sizeof(rnand));
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+/*
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+ if (is_rb500()) {
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+ if (is_rb400()) {
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+ printk("RB400 nand\n");
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+ MEM32(IDT434_REG_BASE + GPIOD) |= GPIO_WPX;
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+ MEM32(IDT434_REG_BASE + GPIOD) &= ~GPIO_CLE;
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+ MEM32(IDT434_REG_BASE + GPIOD) &= ~GPIO_ALE;
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+ rnand.hwcontrol = rbmips_hwcontrol400;
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+ } else {
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+*/
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+ printk("RB500 nand\n");
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+ changeLatchU5(LO_WPX | LO_FOFF | LO_CEX,
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+ LO_ULED | LO_ALE | LO_CLE);
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+ rnand.hwcontrol = rbmips_hwcontrol500;
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+// }
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+
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+ rnand.dev_ready = rb500_dev_ready;
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+ rnand.IO_ADDR_W = (unsigned char *)
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+ KSEG1ADDR(MEM32(IDT434_REG_BASE + DEV2BASE));
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+ rnand.IO_ADDR_R = rnand.IO_ADDR_W;
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+/* } else if (is_rb100()) {
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+ printk("RB100 nand\n");
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+ MEM32(0xB2000064) = 0x100;
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+ MEM32(0xB2000008) = 0x1;
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+ SMEM1(NAND_SET_SPn) = 0x01;
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+ SMEM1(NAND_CLR_WPn) = 0x01;
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+ rnand.IO_ADDR_R = (unsigned char *)KSEG1ADDR(SMEM1_BASE);
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+ rnand.IO_ADDR_W = rnand.IO_ADDR_R;
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+ rnand.hwcontrol = rbmips_hwcontrol100;
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+ rnand.dev_ready = rb100_dev_ready;
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+ }
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+*/
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+ p_nand = (void __iomem *)ioremap(( void*)0x18a20000, 0x1000);
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+ if (!p_nand) {
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+ printk("RBnand Unable ioremap buffer");
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+ return -ENXIO;
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+ }
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+ rnand.eccmode = NAND_ECC_SOFT;
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+ rnand.chip_delay = 25;
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+ rnand.options |= NAND_NO_AUTOINCR;
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+ rmtd.priv = &rnand;
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+
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+ int *b = ( int *)KSEG1ADDR( 0x18010020);
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+ printk( "dev2base 0x%08x mask 0x%08x c 0x%08x tc 0x%08x\n", b[ 0], b[ 1], b[ 2], b[ 3]);
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+
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+ if (nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1)
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+ && nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1)) {
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+ printk("RBxxx nand device not found");
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+ iounmap ((void *)p_nand);
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+ return -ENXIO;
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+ }
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+
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+ add_mtd_partitions(&rmtd, partition_info, 2);
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+ init_ok = 1;
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+ return 0;
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+}
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+
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+module_init(rbmips_init);
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+
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+
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+
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+
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+
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