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60 lines
1.9 KiB
Diff
60 lines
1.9 KiB
Diff
From 78538d673801902108797f2c813e70cfbce280c9 Mon Sep 17 00:00:00 2001
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From: Felix Fietkau <nbd@nbd.name>
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Date: Tue, 6 Mar 2018 13:27:28 +0100
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Subject: [PATCH 26/33] MIPS: ath79: export switch MDIO reference clock
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On AR934x, the MDIO reference clock can be configured to a fixed 100 MHz
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clock. If that feature is not used, it defaults to the main reference
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clock, like on all other SoC.
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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arch/mips/ath79/clock.c | 8 ++++++++
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include/dt-bindings/clock/ath79-clk.h | 3 ++-
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2 files changed, 10 insertions(+), 1 deletion(-)
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -42,6 +42,7 @@ static const char * const clk_names[ATH7
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[ATH79_CLK_DDR] = "ddr",
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[ATH79_CLK_AHB] = "ahb",
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[ATH79_CLK_REF] = "ref",
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+ [ATH79_CLK_MDIO] = "mdio",
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};
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static const char * __init ath79_clk_name(int type)
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@@ -342,6 +343,10 @@ static void __init ar934x_clocks_init(vo
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ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
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ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
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+ clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
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+ if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
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+ ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
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+
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iounmap(dpll_base);
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}
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@@ -698,6 +703,9 @@ static void __init ath79_clocks_init_dt(
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else if (of_device_is_compatible(np, "qca,qca9560-pll"))
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qca956x_clocks_init(pll_base);
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+ if (!clks[ATH79_CLK_MDIO])
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+ clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
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+
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if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
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pr_err("%pOF: could not register clk provider\n", np);
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goto err_iounmap;
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--- a/include/dt-bindings/clock/ath79-clk.h
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+++ b/include/dt-bindings/clock/ath79-clk.h
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@@ -14,7 +14,8 @@
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#define ATH79_CLK_DDR 1
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#define ATH79_CLK_AHB 2
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#define ATH79_CLK_REF 3
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+#define ATH79_CLK_MDIO 4
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-#define ATH79_CLK_END 4
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+#define ATH79_CLK_END 5
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#endif /* __DT_BINDINGS_ATH79_CLK_H */
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