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132 lines
4.3 KiB
Diff
132 lines
4.3 KiB
Diff
From 3faf4e1c537de86058fc22a851cd979489b9185e Mon Sep 17 00:00:00 2001
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From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Date: Wed, 18 Mar 2020 10:44:45 +0100
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Subject: [PATCH] staging: mt7621-pci: fix io space and properly set resource
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limits
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Function 'mt7621_pci_parse_request_of_pci_ranges' is using
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'of_pci_range_to_resource' to get both mem and io resources.
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Internally this function calls to 'pci_address_to_pio' which
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returns -1 if io space address is an address > IO_SPACE_LIMIT
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which is 0xFFFF for mips. This mt7621 soc has io space in physical
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address 0x1e160000. In order to fix this, overwrite invalid io
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0xffffffff with properly values from the device tree and set
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mapped address of this resource as io port base memory address
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calling 'set_io_port_base' function. There is also need to properly
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setup resource limits and io and memory windows with properly
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parsed values instead of set them as 'no limit' which it is wrong.
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For any reason I don't really know legacy driver sets up mem window
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as 0xFFFFFFFF and any other value seems to does not work as expected,
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so set up also here with same values.
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Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Link: https://lore.kernel.org/r/20200318094445.19669-1-sergio.paracuellos@gmail.com
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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drivers/staging/mt7621-pci/pci-mt7621.c | 43 +++++++++++++++++++--------------
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1 file changed, 25 insertions(+), 18 deletions(-)
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--- a/drivers/staging/mt7621-pci/pci-mt7621.c
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+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
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@@ -118,6 +118,7 @@ struct mt7621_pcie_port {
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* @busn: bus range
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* @offset: IO / Memory offset
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* @dev: Pointer to PCIe device
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+ * @io_map_base: virtual memory base address for io
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* @ports: pointer to PCIe port information
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* @resets_inverted: depends on chip revision
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* reset lines are inverted.
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@@ -132,6 +133,7 @@ struct mt7621_pcie {
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resource_size_t mem;
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resource_size_t io;
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} offset;
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+ unsigned long io_map_base;
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struct list_head ports;
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bool resets_inverted;
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};
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@@ -291,22 +293,21 @@ static int mt7621_pci_parse_request_of_p
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}
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for_each_of_pci_range(&parser, &range) {
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- struct resource *res = NULL;
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-
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switch (range.flags & IORESOURCE_TYPE_BITS) {
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case IORESOURCE_IO:
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- ioremap(range.cpu_addr, range.size);
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- res = &pcie->io;
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+ pcie->io_map_base =
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+ (unsigned long)ioremap(range.cpu_addr,
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+ range.size);
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+ of_pci_range_to_resource(&range, node, &pcie->io);
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+ pcie->io.start = range.cpu_addr;
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+ pcie->io.end = range.cpu_addr + range.size - 1;
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pcie->offset.io = 0x00000000UL;
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break;
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case IORESOURCE_MEM:
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- res = &pcie->mem;
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+ of_pci_range_to_resource(&range, node, &pcie->mem);
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pcie->offset.mem = 0x00000000UL;
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break;
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}
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-
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- if (res)
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- of_pci_range_to_resource(&range, node, res);
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}
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err = of_pci_parse_bus_range(node, &pcie->busn);
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@@ -318,6 +319,8 @@ static int mt7621_pci_parse_request_of_p
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pcie->busn.flags = IORESOURCE_BUS;
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}
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+ set_io_port_base(pcie->io_map_base);
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+
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return 0;
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}
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@@ -548,6 +551,10 @@ static void mt7621_pcie_enable_ports(str
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u32 slot;
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u32 val;
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+ /* Setup MEMWIN and IOWIN */
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+ pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
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+ pcie_write(pcie, pcie->io.start, RALINK_PCI_IOBASE);
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+
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list_for_each_entry(port, &pcie->ports, list) {
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if (port->enabled) {
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mt7621_pcie_port_clk_enable(port);
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@@ -668,11 +675,17 @@ static int mt7621_pci_probe(struct platf
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return err;
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}
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+ err = mt7621_pci_parse_request_of_pci_ranges(pcie);
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+ if (err) {
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+ dev_err(dev, "Error requesting pci resources from ranges");
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+ goto out_release_gpios;
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+ }
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+
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/* set resources limits */
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- iomem_resource.start = 0;
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- iomem_resource.end = ~0UL; /* no limit */
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- ioport_resource.start = 0;
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- ioport_resource.end = ~0UL; /* no limit */
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+ iomem_resource.start = pcie->mem.start;
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+ iomem_resource.end = pcie->mem.end;
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+ ioport_resource.start = pcie->io.start;
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+ ioport_resource.end = pcie->io.end;
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mt7621_pcie_init_ports(pcie);
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@@ -685,12 +698,6 @@ static int mt7621_pci_probe(struct platf
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mt7621_pcie_enable_ports(pcie);
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- err = mt7621_pci_parse_request_of_pci_ranges(pcie);
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- if (err) {
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- dev_err(dev, "Error requesting pci resources from ranges");
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- goto out_release_gpios;
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- }
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-
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setup_cm_memory_region(pcie);
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err = mt7621_pcie_request_resources(pcie, &res);
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