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114 lines
3.9 KiB
Diff
114 lines
3.9 KiB
Diff
Status: WORKS
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PXA CPU enhancements
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from patch 1667:
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- 64K PTEs
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from hh.org-cvs:
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- support in pxa_gpio_mode for active low
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#
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# Patch managed by http://www.mn-logistik.de/unsupported/pxa250/patcher
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#
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--- a/arch/arm/mm/proc-xscale.S
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+++ b/arch/arm/mm/proc-xscale.S
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@@ -474,11 +474,62 @@ ENTRY(cpu_xscale_set_pte_ext)
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movne r2, #0 @ no -> fault
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str r2, [r0] @ hardware version
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+
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+ @ We try to map 64K page entries when possible.
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+ @ We do that for kernel space only since the usage pattern from
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+ @ the setting of VM area is quite simple. User space is not worth
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+ @ the implied complexity because of ever randomly changing PTEs
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+ @ (page aging, swapout, etc) requiring constant coherency checks.
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+ @ Since PTEs are usually set in increasing order, we test the
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+ @ possibility for a large page only when given the last PTE of a
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+ @ 64K boundary.
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+ tsteq r1, #L_PTE_USER
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+ andeq r1, r0, #(15 << 2)
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+ teqeq r1, #(15 << 2)
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+ beq 1f
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+
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mov ip, #0
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mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
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mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
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mov pc, lr
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+ @ See if we have 16 identical PTEs but with consecutive base addresses
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+1: bic r3, r2, #0x0000f000
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+ mov r1, #0x0000f000
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+2: eor r2, r2, r3
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+ teq r2, r1
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+ bne 4f
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+ subs r1, r1, #0x00001000
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+ ldr r2, [r0, #-4]!
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+ bne 2b
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+ eors r2, r2, r3
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+ bne 4f
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+
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+ @ Now create our LARGE PTE from the current EXT one.
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+ bic r3, r3, #PTE_TYPE_MASK
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+ orr r3, r3, #PTE_TYPE_LARGE
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+ and r2, r3, #0x30 @ EXT_AP --> LARGE_AP0
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+ orr r2, r2, r2, lsl #2 @ add LARGE_AP1
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+ orr r2, r2, r2, lsl #4 @ add LARGE_AP3 + LARGE_AP2
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+ and r1, r3, #0x3c0 @ EXT_TEX
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+ bic r3, r3, #0x3c0
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+ orr r2, r2, r1, lsl #(12 - 6) @ --> LARGE_TEX
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+ orr r2, r2, r3 @ add remaining bits
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+
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+ @ then put it in the pagetable
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+ mov r3, r2
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+3: strd r2, [r0], #8
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+ tst r0, #(15 << 2)
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+ bne 3b
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+
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+ @ Then sync the 2 corresponding cache lines
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+ sub r0, r0, #(16 << 2)
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+ mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
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+4: orr r0, r0, #(15 << 2)
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+ mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
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+ mov ip, #0
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+ mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
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+ mov pc, lr
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.ltorg
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--- a/include/asm-arm/arch-pxa/pxa-regs.h
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+++ b/include/asm-arm/arch-pxa/pxa-regs.h
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@@ -1345,6 +1345,7 @@
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#define GPIO_ALT_FN_2_OUT 0x280
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#define GPIO_ALT_FN_3_IN 0x300
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#define GPIO_ALT_FN_3_OUT 0x380
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+#define GPIO_ACTIVE_LOW 0x1000
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#define GPIO_MD_MASK_NR 0x07f
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#define GPIO_MD_MASK_DIR 0x080
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#define GPIO_MD_MASK_FN 0x300
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@@ -1597,6 +1598,25 @@
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#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
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#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
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+#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
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+#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
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+#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
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+#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
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+#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
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+#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
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+#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
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+#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
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+#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
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+#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
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+#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
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+#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
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+#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
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+#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
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+#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
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+#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
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+#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
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+#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
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+
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/*
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* SSP Serial Port Registers
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