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279 lines
8.3 KiB
C
279 lines
8.3 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/if_vlan.h>
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#include <asm/mach-ralink/ralink_regs.h>
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#include <mt7620.h>
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#include "ralink_soc_eth.h"
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#include "gsw_mt7620a.h"
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#define MT7620A_CDMA_CSG_CFG 0x400
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#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
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#define MT7621_CDMP_IG_CTRL (MT7620A_CDMA_CSG_CFG + 0x00)
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#define MT7621_CDMP_EG_CTRL (MT7620A_CDMA_CSG_CFG + 0x04)
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#define MT7620A_RESET_FE BIT(21)
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#define MT7621_RESET_FE BIT(6)
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#define MT7620A_RESET_ESW BIT(23)
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#define MT7620_L4_VALID BIT(23)
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#define MT7621_L4_VALID BIT(24)
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#define MT7620_TX_DMA_UDF BIT(15)
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#define MT7621_TX_DMA_UDF BIT(19)
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#define TX_DMA_FP_BMAP ((0xff) << 19)
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#define CDMA_ICS_EN BIT(2)
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#define CDMA_UCS_EN BIT(1)
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#define CDMA_TCS_EN BIT(0)
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#define GDMA_ICS_EN BIT(22)
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#define GDMA_TCS_EN BIT(21)
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#define GDMA_UCS_EN BIT(20)
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/* frame engine counters */
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#define MT7620_REG_MIB_OFFSET 0x1000
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#define MT7620_PPE_AC_BCNT0 (MT7620_REG_MIB_OFFSET + 0x00)
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#define MT7620_GDM1_TX_GBCNT (MT7620_REG_MIB_OFFSET + 0x300)
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#define MT7620_GDM2_TX_GBCNT (MT7620_GDM1_TX_GBCNT + 0x40)
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#define MT7621_REG_MIB_OFFSET 0x2000
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#define MT7621_PPE_AC_BCNT0 (MT7621_REG_MIB_OFFSET + 0x00)
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#define MT7621_GDM1_TX_GBCNT (MT7621_REG_MIB_OFFSET + 0x400)
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#define MT7621_GDM2_TX_GBCNT (MT7621_GDM1_TX_GBCNT + 0x40)
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#define GSW_REG_GDMA1_MAC_ADRL 0x508
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#define GSW_REG_GDMA1_MAC_ADRH 0x50C
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#define MT7621_FE_RST_GL (FE_FE_OFFSET + 0x04)
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#define MT7620_FE_INT_STATUS2 (FE_FE_OFFSET + 0x08)
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/*
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* FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
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* but after test it should be BIT(13).
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*/
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#define MT7620_FE_GDM1_AF BIT(13)
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#define MT7621_FE_GDM1_AF BIT(28)
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#define MT7621_FE_GDM2_AF BIT(29)
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static const u16 mt7620_reg_table[FE_REG_COUNT] = {
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[FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
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[FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
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[FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
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[FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
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[FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
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[FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
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[FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
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[FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
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[FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
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[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
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[FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
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[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
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[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
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[FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
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[FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
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[FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
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[FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
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};
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static const u16 mt7621_reg_table[FE_REG_COUNT] = {
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[FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
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[FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
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[FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
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[FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
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[FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
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[FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
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[FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
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[FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
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[FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
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[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
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[FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
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[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
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[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
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[FE_REG_FE_DMA_VID_BASE] = 0,
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[FE_REG_FE_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT,
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[FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
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[FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
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};
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static void mt7620_fe_reset(void)
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{
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fe_reset(MT7620A_RESET_FE | MT7620A_RESET_ESW);
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}
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static void mt7621_fe_reset(void)
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{
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fe_reset(MT7621_RESET_FE);
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}
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static void mt7620_rxcsum_config(bool enable)
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{
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if (enable)
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fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
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GDMA_TCS_EN | GDMA_UCS_EN),
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MT7620A_GDMA1_FWD_CFG);
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else
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fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
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GDMA_TCS_EN | GDMA_UCS_EN),
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MT7620A_GDMA1_FWD_CFG);
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}
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static void mt7620_txcsum_config(bool enable)
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{
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if (enable)
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fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
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CDMA_UCS_EN | CDMA_TCS_EN),
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MT7620A_CDMA_CSG_CFG);
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else
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fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
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CDMA_UCS_EN | CDMA_TCS_EN),
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MT7620A_CDMA_CSG_CFG);
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}
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static void mt7621_rxvlan_config(bool enable)
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{
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if (enable)
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fe_w32(1, MT7621_CDMP_EG_CTRL);
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else
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fe_w32(0, MT7621_CDMP_EG_CTRL);
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}
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static int mt7620_fwd_config(struct fe_priv *priv)
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{
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struct net_device *dev = priv_netdev(priv);
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fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
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mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
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mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
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return 0;
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}
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static int mt7621_fwd_config(struct fe_priv *priv)
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{
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struct net_device *dev = priv_netdev(priv);
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fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~0xffff, MT7620A_GDMA1_FWD_CFG);
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/* mt7621 don't have txcsum config */
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mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
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mt7621_rxvlan_config((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
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(priv->flags & FE_FLAG_RX_VLAN_CTAG));
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return 0;
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}
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static void mt7620_tx_dma(struct fe_tx_dma *txd)
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{
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}
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static void mt7621_tx_dma(struct fe_tx_dma *txd)
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{
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txd->txd4 = BIT(25);
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}
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static void mt7620_init_data(struct fe_soc_data *data,
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struct net_device *netdev)
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{
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struct fe_priv *priv = netdev_priv(netdev);
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priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
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FE_FLAG_RX_SG_DMA;
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netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
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NETIF_F_HW_VLAN_CTAG_TX;
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if (mt7620_get_eco() >= 5)
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netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
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NETIF_F_IPV6_CSUM;
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}
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static void mt7621_init_data(struct fe_soc_data *data,
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struct net_device *netdev)
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{
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struct fe_priv *priv = netdev_priv(netdev);
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priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
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FE_FLAG_RX_SG_DMA | FE_FLAG_NAPI_WEIGHT;
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netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
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NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_SG | NETIF_F_TSO |
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NETIF_F_TSO6 | NETIF_F_IPV6_CSUM;
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}
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static void mt7621_set_mac(struct fe_priv *priv, unsigned char *mac)
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{
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unsigned long flags;
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spin_lock_irqsave(&priv->page_lock, flags);
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fe_w32((mac[0] << 8) | mac[1], GSW_REG_GDMA1_MAC_ADRH);
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fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
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GSW_REG_GDMA1_MAC_ADRL);
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spin_unlock_irqrestore(&priv->page_lock, flags);
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}
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static struct fe_soc_data mt7620_data = {
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.init_data = mt7620_init_data,
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.reset_fe = mt7620_fe_reset,
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.set_mac = mt7620_set_mac,
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.fwd_config = mt7620_fwd_config,
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.tx_dma = mt7620_tx_dma,
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.switch_init = mt7620_gsw_probe,
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.switch_config = mt7620_gsw_config,
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.port_init = mt7620_port_init,
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.reg_table = mt7620_reg_table,
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.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
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.rx_int = RT5350_RX_DONE_INT,
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.tx_int = RT5350_TX_DONE_INT,
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.status_int = MT7620_FE_GDM1_AF,
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.checksum_bit = MT7620_L4_VALID,
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.has_carrier = mt7620a_has_carrier,
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.mdio_read = mt7620_mdio_read,
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.mdio_write = mt7620_mdio_write,
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.mdio_adjust_link = mt7620_mdio_link_adjust,
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};
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static struct fe_soc_data mt7621_data = {
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.init_data = mt7621_init_data,
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.reset_fe = mt7621_fe_reset,
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.set_mac = mt7621_set_mac,
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.fwd_config = mt7621_fwd_config,
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.tx_dma = mt7621_tx_dma,
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.switch_init = mt7620_gsw_probe,
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.switch_config = mt7621_gsw_config,
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.reg_table = mt7621_reg_table,
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.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
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.rx_int = RT5350_RX_DONE_INT,
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.tx_int = RT5350_TX_DONE_INT,
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.status_int = (MT7621_FE_GDM1_AF | MT7621_FE_GDM2_AF),
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.checksum_bit = MT7621_L4_VALID,
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.has_carrier = mt7620a_has_carrier,
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.mdio_read = mt7620_mdio_read,
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.mdio_write = mt7620_mdio_write,
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.mdio_adjust_link = mt7620_mdio_link_adjust,
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};
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const struct of_device_id of_fe_match[] = {
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{ .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
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{ .compatible = "ralink,mt7621-eth", .data = &mt7621_data },
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{},
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};
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MODULE_DEVICE_TABLE(of, of_fe_match);
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