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188 lines
6.0 KiB
Diff
188 lines
6.0 KiB
Diff
From 2fc26b1b6377156e07c6c9ce934c58f634fcd21b Mon Sep 17 00:00:00 2001
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From: Kuldeep Singh <kuldeep.singh@nxp.com>
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Date: Wed, 1 Apr 2020 14:51:37 +0800
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Subject: [PATCH] LF-18-3 spi: fsl-qspi: Allocate AHB memory dynamically for
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imx platforms
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LS platforms doesn't require dynamic allocaltion of AHB memory. So, let's
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define a quirk which allocates AHB memory dynamically only for imx
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platforms.
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Fixes: c70adc97("spi: spi-fsl-qspi: dynamically alloc AHB memory for QSPI")
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Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
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[rebase]
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Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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---
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drivers/spi/spi-fsl-qspi.c | 71 +++++++++++++++++++++++++++++++++++-----------
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1 file changed, 55 insertions(+), 16 deletions(-)
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--- a/drivers/spi/spi-fsl-qspi.c
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+++ b/drivers/spi/spi-fsl-qspi.c
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@@ -197,6 +197,12 @@
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*/
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#define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5)
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+/*
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+ * Use flash size for imx platforms and not for LS platforms. Define a
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+ * quirk which enables it only on imx platforms.
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+ */
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+#define QUADSPI_QUIRK_USE_FLASH_SIZE BIT(6)
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+
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#define QUADSPI_MIN_IOMAP SZ_4M
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struct fsl_qspi_devtype_data {
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@@ -213,7 +219,7 @@ static const struct fsl_qspi_devtype_dat
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.txfifo = SZ_64,
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.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
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.ahb_buf_size = SZ_1K,
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- .quirks = QUADSPI_QUIRK_SWAP_ENDIAN,
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+ .quirks = QUADSPI_QUIRK_SWAP_ENDIAN | QUADSPI_QUIRK_USE_FLASH_SIZE,
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.little_endian = true,
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};
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@@ -222,7 +228,8 @@ static const struct fsl_qspi_devtype_dat
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.txfifo = SZ_512,
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.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
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.ahb_buf_size = SZ_1K,
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- .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618,
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+ .quirks = QUADSPI_QUIRK_4X_INT_CLK | QUADSPI_QUIRK_TKT245618 |
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+ QUADSPI_QUIRK_USE_FLASH_SIZE,
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.little_endian = true,
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};
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@@ -232,7 +239,7 @@ static const struct fsl_qspi_devtype_dat
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.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
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.ahb_buf_size = SZ_1K,
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.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
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- QUADSPI_QUIRK_USE_TDH_SETTING,
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+ QUADSPI_QUIRK_USE_TDH_SETTING | QUADSPI_QUIRK_USE_FLASH_SIZE,
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.little_endian = true,
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};
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@@ -242,7 +249,7 @@ static const struct fsl_qspi_devtype_dat
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.invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID,
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.ahb_buf_size = SZ_1K,
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.quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK |
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- QUADSPI_QUIRK_USE_TDH_SETTING,
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+ QUADSPI_QUIRK_USE_TDH_SETTING | QUADSPI_QUIRK_USE_FLASH_SIZE,
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.little_endian = true,
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};
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@@ -310,6 +317,11 @@ static inline int needs_tdh_setting(stru
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return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING;
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}
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+static inline int needs_flash_size(struct fsl_qspi *q)
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+{
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+ return q->devtype_data->quirks & QUADSPI_QUIRK_USE_FLASH_SIZE;
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+}
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+
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/*
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* An IC bug makes it necessary to rearrange the 32-bit data.
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* Later chips, such as IMX6SLX, have fixed this bug.
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@@ -556,6 +568,14 @@ static void fsl_qspi_select_mem(struct f
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static int fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op)
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{
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+ if (!needs_flash_size(q)) {
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+ u32 size = q->devtype_data->ahb_buf_size;
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+ memcpy_fromio(op->data.buf.in,
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+ q->ahb_addr + q->selected * size,
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+ op->data.nbytes);
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+ return 0;
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+ }
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+
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u32 start = op->addr.val + q->selected * q->memmap_phy_size / 4;
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u32 len = op->data.nbytes;
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@@ -674,6 +694,7 @@ static int fsl_qspi_exec_op(struct spi_m
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u32 addr_offset = 0;
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int err = 0;
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int invalid_mstrid = q->devtype_data->invalid_mstrid;
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+ u32 size = q->devtype_data->ahb_buf_size;
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mutex_lock(&q->lock);
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@@ -686,8 +707,11 @@ static int fsl_qspi_exec_op(struct spi_m
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if (needs_amba_base_offset(q))
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addr_offset = q->memmap_phy;
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+ if (needs_flash_size(q))
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+ size = q->memmap_phy_size / 4;
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+
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qspi_writel(q,
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- q->selected * q->memmap_phy_size / 4 + addr_offset,
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+ q->selected * size + addr_offset,
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base + QUADSPI_SFAR);
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qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) |
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@@ -751,6 +775,7 @@ static int fsl_qspi_default_setup(struct
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void __iomem *base = q->iobase;
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u32 reg, addr_offset = 0;
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int ret;
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+ u32 size = q->devtype_data->ahb_buf_size;
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/* disable and unprepare clock to avoid glitch pass to controller */
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fsl_qspi_clk_disable_unprep(q);
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@@ -805,19 +830,22 @@ static int fsl_qspi_default_setup(struct
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addr_offset = q->memmap_phy;
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/*
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- * In HW there can be a maximum of four chips on two buses with
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- * two chip selects on each bus. We use four chip selects in SW
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- * to differentiate between the four chips.
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- * We divide the total memory region size equally for each chip
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- * and set SFA1AD, SFA2AD, SFB1AD, SFB2AD accordingly.
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+ * In HW there can be a maximum of four chips on two buses with two
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+ * chip selects on each bus. We use four chip selects in SW to
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+ * differentiate between the four chips. We divide the total memory
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+ * region/ahb_buf_size size equally for each chip and set SFA1AD,
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+ * SFA2AD, SFB1AD, SFB2AD accordingly.
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*/
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- qspi_writel(q, q->memmap_phy_size / 4 + addr_offset,
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+ if (needs_flash_size(q))
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+ size = q->memmap_phy_size / 4;
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+
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+ qspi_writel(q, size + addr_offset,
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base + QUADSPI_SFA1AD);
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- qspi_writel(q, q->memmap_phy_size / 4 * 2 + addr_offset,
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+ qspi_writel(q, size * 2 + addr_offset,
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base + QUADSPI_SFA2AD);
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- qspi_writel(q, q->memmap_phy_size / 4 * 3 + addr_offset,
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+ qspi_writel(q, size * 3 + addr_offset,
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base + QUADSPI_SFB1AD);
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- qspi_writel(q, q->memmap_phy_size / 4 * 4 + addr_offset,
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+ qspi_writel(q, size * 4 + addr_offset,
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base + QUADSPI_SFB2AD);
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q->selected = -1;
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@@ -904,6 +932,15 @@ static int fsl_qspi_probe(struct platfor
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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"QuadSPI-memory");
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+
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+ if (!needs_flash_size(q)) {
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+ q->ahb_addr = devm_ioremap_resource(dev, res);
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+ if (IS_ERR(q->ahb_addr)) {
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+ ret = PTR_ERR(q->ahb_addr);
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+ goto err_put_ctrl;
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+ }
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+ }
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+
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q->memmap_phy = res->start;
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q->memmap_phy_size = resource_size(res);
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@@ -979,8 +1016,10 @@ static int fsl_qspi_remove(struct platfo
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mutex_destroy(&q->lock);
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- if (q->ahb_addr)
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- iounmap(q->ahb_addr);
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+ if (needs_flash_size(q)) {
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+ if (q->ahb_addr)
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+ iounmap(q->ahb_addr);
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+ }
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return 0;
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}
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