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107 lines
3.4 KiB
Diff
107 lines
3.4 KiB
Diff
From 6c753f83ffc3fede13582f667a15e7f6e97f972c Mon Sep 17 00:00:00 2001
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From: Robin Gong <yibin.gong@nxp.com>
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Date: Tue, 4 Jul 2017 16:04:36 +0800
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Subject: [PATCH] MLK-15330-3 dma: fsl-edma-v3: add dual fifo support
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There is Audio dual fifo cause that fill fifo one by one and
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loop back after every minor loop:
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-- fill the first 32bit width fifo
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-- fill the next 32bit width fifo
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-- +MLOFF signed offset after the above two FIFOs filled
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-- loop back to the first step to handle the next minor loop.
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Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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(cherry picked from commit 5aa5e9663bb3a834444b75ea086bef8c37ecb636)
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---
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.../devicetree/bindings/dma/fsl-edma-v3.txt | 2 ++
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drivers/dma/fsl-edma-v3.c | 29 ++++++++++++++++++++--
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2 files changed, 29 insertions(+), 2 deletions(-)
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--- a/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
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+++ b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
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@@ -22,6 +22,8 @@ Required properties:
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0: transmit, 1: receive.
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BIT(1): local or remote access:
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0: local, 1: remote.
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+ BIT(2): dualfifo case or not(only in Audio cyclic now):
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+ 0: not dual fifo case, 1: dualfifo case.
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See the SoC's reference manual for all the supported request sources.
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- dma-channels : Number of channels supported by the controller
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--- a/drivers/dma/fsl-edma-v3.c
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+++ b/drivers/dma/fsl-edma-v3.c
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@@ -78,6 +78,9 @@
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#define EDMA_TCD_SOFF_SOFF(x) (x)
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#define EDMA_TCD_NBYTES_NBYTES(x) (x)
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+#define EDMA_TCD_NBYTES_MLOFF(x) (x << 10)
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+#define EDMA_TCD_NBYTES_DMLOE (1 << 30)
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+#define EDMA_TCD_NBYTES_SMLOE (1 << 31)
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#define EDMA_TCD_SLAST_SLAST(x) (x)
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#define EDMA_TCD_DADDR_DADDR(x) (x)
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#define EDMA_TCD_CITER_CITER(x) ((x) & 0x7FFF)
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@@ -102,6 +105,7 @@
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#define ARGS_RX BIT(0)
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#define ARGS_REMOTE BIT(1)
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+#define ARGS_DFIFO BIT(2)
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struct fsl_edma3_hw_tcd {
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__le32 saddr;
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@@ -143,6 +147,7 @@ struct fsl_edma3_chan {
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int priority;
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int is_rxchan;
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int is_remote;
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+ int is_dfifo;
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struct dma_pool *tcd_pool;
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u32 chn_real_count;
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char txirq_name[32];
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@@ -454,6 +459,19 @@ void fsl_edma3_fill_tcd(struct fsl_edma3
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tcd->soff = cpu_to_le16(EDMA_TCD_SOFF_SOFF(soff));
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+ if (fsl_chan->is_dfifo) {
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+ /* set mloff as -8 */
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+ nbytes |= EDMA_TCD_NBYTES_MLOFF(-8);
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+ /* enable DMLOE/SMLOE */
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+ if (fsl_chan->fsc.dir == DMA_MEM_TO_DEV) {
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+ nbytes |= EDMA_TCD_NBYTES_DMLOE;
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+ nbytes &= ~EDMA_TCD_NBYTES_SMLOE;
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+ } else {
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+ nbytes |= EDMA_TCD_NBYTES_SMLOE;
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+ nbytes &= ~EDMA_TCD_NBYTES_DMLOE;
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+ }
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+ }
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+
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tcd->nbytes = cpu_to_le32(EDMA_TCD_NBYTES_NBYTES(nbytes));
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tcd->slast = cpu_to_le32(EDMA_TCD_SLAST_SLAST(slast));
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@@ -540,11 +558,17 @@ static struct dma_async_tx_descriptor *f
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src_addr = dma_buf_next;
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dst_addr = fsl_chan->fsc.dev_addr;
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soff = fsl_chan->fsc.addr_width;
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- doff = 0;
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+ if (fsl_chan->is_dfifo)
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+ doff = 4;
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+ else
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+ doff = 0;
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} else if (fsl_chan->fsc.dir == DMA_DEV_TO_MEM) {
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src_addr = fsl_chan->fsc.dev_addr;
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dst_addr = dma_buf_next;
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- soff = 0;
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+ if (fsl_chan->is_dfifo)
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+ soff = 4;
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+ else
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+ soff = 0;
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doff = fsl_chan->fsc.addr_width;
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} else {
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/* DMA_DEV_TO_DEV */
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@@ -715,6 +739,7 @@ static struct dma_chan *fsl_edma3_xlate(
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fsl_chan->priority = dma_spec->args[1];
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fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX;
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fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE;
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+ fsl_chan->is_dfifo = dma_spec->args[2] & ARGS_DFIFO;
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mutex_unlock(&fsl_edma3->fsl_edma3_mutex);
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return chan;
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}
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