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122 lines
3.5 KiB
Diff
122 lines
3.5 KiB
Diff
From b2dd96ec88b7eb4288ca39a1fc78176872c0683b Mon Sep 17 00:00:00 2001
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From: Viorel Suman <viorel.suman@nxp.com>
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Date: Wed, 27 Jun 2018 10:59:12 +0300
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Subject: [PATCH] MLK-18682-2: ASoC: fsl: sai: allow dynamic pll switching
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Currently SAI master clock derives from an audio pll that cannot be
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changed at runtime. iMX8 SoC has 2 audio plls usually configured to support
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either 8000Hz (8k,16k,32k,48k,etc) or 11025Hz (11k,22k,44.1k,88.2k,etc)
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ranges of rates - thus at runtime a SAI interface is able to play only one
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range of rates. The patch allows dynamic SAI master clock reparenting to
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the appropriate audio pll as function of the audio stream rate to be
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played/recorded.
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Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
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---
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sound/soc/fsl/fsl_sai.c | 60 ++++++++++++++++++++++++++++++++++++++++++++-----
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sound/soc/fsl/fsl_sai.h | 2 ++
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2 files changed, 57 insertions(+), 5 deletions(-)
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--- a/sound/soc/fsl/fsl_sai.c
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+++ b/sound/soc/fsl/fsl_sai.c
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@@ -5,6 +5,7 @@
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// Copyright 2012-2016 Freescale Semiconductor, Inc.
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#include <linux/clk.h>
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+#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/module.h>
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@@ -234,6 +235,50 @@ static int fsl_sai_set_dai_sysclk_tr(str
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return 0;
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}
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+static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id,
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+ unsigned int freq)
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+{
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+ struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
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+ struct clk *p = sai->mclk_clk[clk_id], *pll = 0, *npll = 0;
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+ u64 ratio = freq;
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+ int ret;
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+
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+ while (p && sai->pll8k_clk && sai->pll11k_clk) {
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+ struct clk *pp = clk_get_parent(p);
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+
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+ if (clk_is_match(pp, sai->pll8k_clk) ||
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+ clk_is_match(pp, sai->pll11k_clk)) {
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+ pll = pp;
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+ break;
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+ }
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+ p = pp;
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+ }
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+
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+ if (pll) {
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+ npll = (do_div(ratio, 8000) ? sai->pll11k_clk : sai->pll8k_clk);
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+ if (!clk_is_match(pll, npll)) {
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+ if (sai->mclk_streams == 0) {
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+ ret = clk_set_parent(p, npll);
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+ if (ret < 0)
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+ dev_warn(dai->dev,
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+ "failed to set parent %s: %d\n",
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+ __clk_get_name(npll), ret);
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+ } else {
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+ dev_err(dai->dev,
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+ "PLL %s is in use by a running stream.\n",
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+ __clk_get_name(pll));
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+ return -EINVAL;
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+ }
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+ }
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+ }
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+
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+ ret = clk_set_rate(sai->mclk_clk[clk_id], freq);
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+ if (ret < 0)
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+ dev_err(dai->dev, "failed to set clock rate (%u): %d\n",
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+ freq, ret);
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+ return ret;
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+}
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+
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static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
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{
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struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
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@@ -262,12 +307,9 @@ static int fsl_sai_set_dai_sysclk(struct
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return -EINVAL;
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}
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- ret = clk_set_rate(sai->mclk_clk[clk_id], freq);
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- if (ret < 0) {
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- dev_err(cpu_dai->dev, "failed to set clock rate (%u): %d\n",
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- freq, ret);
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+ ret = fsl_sai_set_mclk_rate(cpu_dai, clk_id, freq);
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+ if (ret < 0)
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return ret;
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- }
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}
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ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
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@@ -1288,6 +1330,14 @@ static int fsl_sai_probe(struct platform
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}
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}
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+ sai->pll8k_clk = devm_clk_get(&pdev->dev, "pll8k");
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+ if (IS_ERR(sai->pll8k_clk))
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+ sai->pll8k_clk = NULL;
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+
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+ sai->pll11k_clk = devm_clk_get(&pdev->dev, "pll11k");
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+ if (IS_ERR(sai->pll11k_clk))
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+ sai->pll11k_clk = NULL;
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+
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if (of_find_property(np, "fsl,sai-multi-lane", NULL))
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sai->is_multi_lane = true;
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--- a/sound/soc/fsl/fsl_sai.h
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+++ b/sound/soc/fsl/fsl_sai.h
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@@ -239,6 +239,8 @@ struct fsl_sai {
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struct regmap *regmap;
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struct clk *bus_clk;
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struct clk *mclk_clk[FSL_SAI_MCLK_MAX];
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+ struct clk *pll8k_clk;
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+ struct clk *pll11k_clk;
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bool slave_mode[2];
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bool is_lsb_first;
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