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143 lines
4.8 KiB
Diff
143 lines
4.8 KiB
Diff
From cdebdc900ae5cb29dc1cce1c26865001534ab77d Mon Sep 17 00:00:00 2001
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From: Calvin Johnson <calvin.johnson@nxp.com>
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Date: Thu, 4 Oct 2018 09:38:34 +0530
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Subject: [PATCH] staging: fsl_ppfe/eth: replace magic numbers
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Replace magic numbers and some cosmetic changes.
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Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
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---
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drivers/staging/fsl_ppfe/pfe_eth.c | 83 ++++++++++++++++++++++++++++----------
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1 file changed, 61 insertions(+), 22 deletions(-)
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--- a/drivers/staging/fsl_ppfe/pfe_eth.c
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+++ b/drivers/staging/fsl_ppfe/pfe_eth.c
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@@ -66,6 +66,36 @@ static void pfe_eth_flush_tx(struct pfe_
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static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int tx_q_num, int
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from_tx, int n_desc);
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+/* MDIO registers */
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+#define MDIO_SGMII_CR 0x00
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+#define MDIO_SGMII_SR 0x01
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+#define MDIO_SGMII_DEV_ABIL_SGMII 0x04
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+#define MDIO_SGMII_LINK_TMR_L 0x12
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+#define MDIO_SGMII_LINK_TMR_H 0x13
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+#define MDIO_SGMII_IF_MODE 0x14
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+
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+/* SGMII Control defines */
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+#define SGMII_CR_RST 0x8000
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+#define SGMII_CR_AN_EN 0x1000
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+#define SGMII_CR_RESTART_AN 0x0200
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+#define SGMII_CR_FD 0x0100
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+#define SGMII_CR_SPEED_SEL1_1G 0x0040
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+#define SGMII_CR_DEF_VAL (SGMII_CR_AN_EN | SGMII_CR_FD | \
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+ SGMII_CR_SPEED_SEL1_1G)
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+
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+/* SGMII IF Mode */
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+#define SGMII_DUPLEX_HALF 0x10
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+#define SGMII_SPEED_10MBPS 0x00
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+#define SGMII_SPEED_100MBPS 0x04
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+#define SGMII_SPEED_1GBPS 0x08
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+#define SGMII_USE_SGMII_AN 0x02
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+#define SGMII_EN 0x01
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+
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+/* SGMII Device Ability for SGMII */
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+#define SGMII_DEV_ABIL_ACK 0x4000
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+#define SGMII_DEV_ABIL_EEE_CLK_STP_EN 0x0100
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+#define SGMII_DEV_ABIL_SGMII 0x0001
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+
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unsigned int gemac_regs[] = {
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0x0004, /* Interrupt event */
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0x0008, /* Interrupt mask */
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@@ -1042,6 +1072,10 @@ static int pfe_get_phydev_speed(struct p
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#define SCFG_RGMIIPCR_SETSP_10M (0x00000002)
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#define SCFG_RGMIIPCR_SETFD (0x00000001)
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+#define MDIOSELCR 0x484
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+#define MDIOSEL_SERDES 0x0
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+#define MDIOSEL_EXTPHY 0x80000000
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+
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static void pfe_set_rgmii_speed(struct phy_device *phydev)
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{
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u32 rgmii_pcr;
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@@ -1187,25 +1221,34 @@ static void ls1012a_configure_serdes(str
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netif_info(priv, drv, ndev, "%s\n", __func__);
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/* PCS configuration done with corresponding GEMAC */
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- pfe_eth_mdio_read(bus, 0, 0);
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- pfe_eth_mdio_read(bus, 0, 1);
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+ pfe_eth_mdio_read(bus, 0, MDIO_SGMII_CR);
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+ pfe_eth_mdio_read(bus, 0, MDIO_SGMII_SR);
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+
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+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, SGMII_CR_RST);
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- /*These settings taken from validtion team */
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- pfe_eth_mdio_write(bus, 0, 0x0, 0x8000);
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if (sgmii_2500) {
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- pfe_eth_mdio_write(bus, 0, 0x14, 0x9);
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- pfe_eth_mdio_write(bus, 0, 0x4, 0x4001);
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- pfe_eth_mdio_write(bus, 0, 0x12, 0xa120);
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- pfe_eth_mdio_write(bus, 0, 0x13, 0x7);
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+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_IF_MODE, SGMII_SPEED_1GBPS
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+ | SGMII_EN);
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+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_DEV_ABIL_SGMII,
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+ SGMII_DEV_ABIL_ACK | SGMII_DEV_ABIL_SGMII);
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+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_L, 0xa120);
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+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_H, 0x7);
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/* Autonegotiation need to be disabled for 2.5G SGMII mode*/
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- value = 0x0140;
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- pfe_eth_mdio_write(bus, 0, 0x0, value);
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+ value = SGMII_CR_FD | SGMII_CR_SPEED_SEL1_1G;
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+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, value);
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} else {
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- pfe_eth_mdio_write(bus, 0, 0x14, 0xb);
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- pfe_eth_mdio_write(bus, 0, 0x4, 0x1a1);
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- pfe_eth_mdio_write(bus, 0, 0x12, 0x400);
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- pfe_eth_mdio_write(bus, 0, 0x13, 0x0);
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- pfe_eth_mdio_write(bus, 0, 0x0, 0x1140);
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+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_IF_MODE,
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+ SGMII_SPEED_1GBPS
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+ | SGMII_USE_SGMII_AN
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+ | SGMII_EN);
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+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_DEV_ABIL_SGMII,
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+ SGMII_DEV_ABIL_EEE_CLK_STP_EN
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+ | 0xa0
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+ | SGMII_DEV_ABIL_SGMII);
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+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_L, 0x400);
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+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_H, 0x0);
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+ value = SGMII_CR_AN_EN | SGMII_CR_FD | SGMII_CR_SPEED_SEL1_1G;
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+ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, value);
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}
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}
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@@ -1235,15 +1278,15 @@ static int pfe_phy_init(struct net_devic
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(interface == PHY_INTERFACE_MODE_2500SGMII)) {
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/*Configure SGMII PCS */
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if (pfe->scfg) {
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- /*Config MDIO from serdes */
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- regmap_write(pfe->scfg, 0x484, 0x00000000);
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+ /* Config MDIO from serdes */
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+ regmap_write(pfe->scfg, MDIOSELCR, MDIOSEL_SERDES);
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}
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ls1012a_configure_serdes(ndev);
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}
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if (pfe->scfg) {
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/*Config MDIO from PAD */
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- regmap_write(pfe->scfg, 0x484, 0x80000000);
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+ regmap_write(pfe->scfg, MDIOSELCR, MDIOSEL_EXTPHY);
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}
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priv->oldlink = 0;
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@@ -2339,10 +2382,6 @@ static int pfe_eth_init_one(struct pfe *
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priv->PHY_baseaddr = cbus_emac_base[0];
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priv->GPI_baseaddr = cbus_gpi_base[id];
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-#define HIF_GEMAC_TMUQ_BASE 6
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- priv->low_tmu_q = HIF_GEMAC_TMUQ_BASE + (id * 2);
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- priv->high_tmu_q = priv->low_tmu_q + 1;
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-
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spin_lock_init(&priv->lock);
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pfe_eth_fast_tx_timeout_init(priv);
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