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139 lines
4.2 KiB
Diff
139 lines
4.2 KiB
Diff
From fb76c3ded8c771e8b9287d62b5e13666037f890e Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.org>
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Date: Tue, 17 Sep 2019 18:28:17 +0100
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Subject: [PATCH] drm/vc4: Add support for YUV color encodings and
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ranges
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The BT601/BT709 color encoding and limited vs full
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range properties were not being exposed, defaulting
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always to BT601 limited range.
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Expose the parameters and set the registers appropriately.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
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---
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drivers/gpu/drm/vc4/vc4_plane.c | 72 +++++++++++++++++++++++++++++++--
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drivers/gpu/drm/vc4/vc4_regs.h | 3 ++
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2 files changed, 72 insertions(+), 3 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_plane.c
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+++ b/drivers/gpu/drm/vc4/vc4_plane.c
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@@ -577,6 +577,53 @@ static int vc4_plane_allocate_lbm(struct
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return 0;
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}
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+/* The colorspace conversion matrices are held in 3 entries in the dlist.
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+ * Create an array of them, with entries for each full and limited mode, and
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+ * each supported colorspace.
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+ */
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+#define VC4_LIMITED_RANGE 0
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+#define VC4_FULL_RANGE 1
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+
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+static const u32 colorspace_coeffs[2][DRM_COLOR_ENCODING_MAX][3] = {
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+ {
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+ /* Limited range */
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+ {
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+ /* BT601 */
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+ SCALER_CSC0_ITR_R_601_5,
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+ SCALER_CSC1_ITR_R_601_5,
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+ SCALER_CSC2_ITR_R_601_5,
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+ }, {
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+ /* BT709 */
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+ SCALER_CSC0_ITR_R_709_3,
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+ SCALER_CSC1_ITR_R_709_3,
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+ SCALER_CSC2_ITR_R_709_3,
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+ }, {
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+ /* BT2020. Not supported yet - copy 601 */
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+ SCALER_CSC0_ITR_R_601_5,
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+ SCALER_CSC1_ITR_R_601_5,
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+ SCALER_CSC2_ITR_R_601_5,
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+ }
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+ }, {
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+ /* Full range */
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+ {
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+ /* JFIF */
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+ SCALER_CSC0_JPEG_JFIF,
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+ SCALER_CSC1_JPEG_JFIF,
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+ SCALER_CSC2_JPEG_JFIF,
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+ }, {
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+ /* BT709 */
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+ SCALER_CSC0_ITR_R_709_3_FR,
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+ SCALER_CSC1_ITR_R_709_3_FR,
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+ SCALER_CSC2_ITR_R_709_3_FR,
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+ }, {
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+ /* BT2020. Not supported yet - copy JFIF */
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+ SCALER_CSC0_JPEG_JFIF,
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+ SCALER_CSC1_JPEG_JFIF,
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+ SCALER_CSC2_JPEG_JFIF,
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+ }
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+ }
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+};
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+
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/* Writes out a full display list for an active plane to the plane's
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* private dlist state.
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*/
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@@ -856,9 +903,20 @@ static int vc4_plane_mode_set(struct drm
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/* Colorspace conversion words */
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if (vc4_state->is_yuv) {
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- vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
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- vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
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- vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
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+ enum drm_color_encoding color_encoding = state->color_encoding;
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+ enum drm_color_range color_range = state->color_range;
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+ const u32 *ccm;
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+
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+ if (color_encoding >= DRM_COLOR_ENCODING_MAX)
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+ color_encoding = DRM_COLOR_YCBCR_BT601;
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+ if (color_range >= DRM_COLOR_RANGE_MAX)
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+ color_range = DRM_COLOR_YCBCR_LIMITED_RANGE;
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+
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+ ccm = colorspace_coeffs[color_range][color_encoding];
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+
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+ vc4_dlist_write(vc4_state, ccm[0]);
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+ vc4_dlist_write(vc4_state, ccm[1]);
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+ vc4_dlist_write(vc4_state, ccm[2]);
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}
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vc4_state->lbm_offset = 0;
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@@ -1265,5 +1323,13 @@ struct drm_plane *vc4_plane_init(struct
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DRM_MODE_REFLECT_X |
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DRM_MODE_REFLECT_Y);
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+ drm_plane_create_color_properties(plane,
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+ BIT(DRM_COLOR_YCBCR_BT601) |
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+ BIT(DRM_COLOR_YCBCR_BT709),
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+ BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
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+ BIT(DRM_COLOR_YCBCR_FULL_RANGE),
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+ DRM_COLOR_YCBCR_BT709,
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+ DRM_COLOR_YCBCR_LIMITED_RANGE);
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+
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return plane;
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}
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -950,6 +950,7 @@ enum hvs_pixel_format {
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#define SCALER_CSC0_ITR_R_601_5 0x00f00000
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#define SCALER_CSC0_ITR_R_709_3 0x00f00000
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#define SCALER_CSC0_JPEG_JFIF 0x00000000
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+#define SCALER_CSC0_ITR_R_709_3_FR 0x00000000
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/* S2.8 contribution of Cb to Green */
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#define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22)
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@@ -966,6 +967,7 @@ enum hvs_pixel_format {
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#define SCALER_CSC1_ITR_R_601_5 0xe73304a8
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#define SCALER_CSC1_ITR_R_709_3 0xf2b784a8
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#define SCALER_CSC1_JPEG_JFIF 0xea34a400
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+#define SCALER_CSC1_ITR_R_709_3_FR 0xe23d0400
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/* S2.8 contribution of Cb to Red */
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#define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20)
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@@ -979,6 +981,7 @@ enum hvs_pixel_format {
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#define SCALER_CSC2_ITR_R_601_5 0x00066204
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#define SCALER_CSC2_ITR_R_709_3 0x00072a1c
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#define SCALER_CSC2_JPEG_JFIF 0x000599c5
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+#define SCALER_CSC2_ITR_R_709_3_FR 0x00064ddb
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#define SCALER_TPZ0_VERT_RECALC BIT(31)
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#define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)
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