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202 lines
6.4 KiB
Diff
202 lines
6.4 KiB
Diff
This commit adds two functions armada_370_xp_alloc_pcie_window() and
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armada_370_xp_free_pcie_window() that respectively allocate and free
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an address decoding window pointing to either a memory or I/O region
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of a PCIe device.
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Those functions will be used by the PCIe driver to create and remove
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those regions depending on the PCIe devices that are detected.
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Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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---
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arch/arm/mach-mvebu/addr-map.c | 156 ++++++++++++++++++++++++++++++++++++++--
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arch/arm/mach-mvebu/common.h | 4 ++
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2 files changed, 156 insertions(+), 4 deletions(-)
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--- a/arch/arm/mach-mvebu/addr-map.c
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+++ b/arch/arm/mach-mvebu/addr-map.c
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@@ -24,14 +24,10 @@
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#define ARMADA_XP_TARGET_DEV_BUS 1
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#define ARMADA_XP_ATTR_DEV_BOOTROM 0x1D
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#define ARMADA_XP_TARGET_ETH1 3
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-#define ARMADA_XP_TARGET_PCIE_0_2 4
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#define ARMADA_XP_TARGET_ETH0 7
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-#define ARMADA_XP_TARGET_PCIE_1_3 8
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#define ARMADA_370_TARGET_DEV_BUS 1
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#define ARMADA_370_ATTR_DEV_BOOTROM 0x1D
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-#define ARMADA_370_TARGET_PCIE_0 4
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-#define ARMADA_370_TARGET_PCIE_1 8
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#define ARMADA_WINDOW_8_PLUS_OFFSET 0x90
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#define ARMADA_SDRAM_ADDR_DECODING_OFFSET 0x180
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@@ -89,6 +85,158 @@ static struct __initdata orion_addr_map_
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.win_cfg_base = armada_cfg_base,
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};
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+#ifdef CONFIG_PCI
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+/*
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+ * PCIe windows allocation code.
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+ */
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+#define ARMADA_370_XP_PCIE_MEM_START 0xC0000000
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+#define ARMADA_370_XP_PCIE_MEM_END (ARMADA_370_XP_PCIE_MEM_START + SZ_256M)
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+#define ARMADA_370_XP_PCIE_IO_START 0xF2000000
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+#define ARMADA_370_XP_PCIE_IO_END (ARMADA_370_XP_PCIE_IO_START + SZ_1M)
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+
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+static unsigned long armada_370_xp_pcie_memaddr = ARMADA_370_XP_PCIE_MEM_START;
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+static unsigned long armada_370_xp_pcie_ioaddr = ARMADA_370_XP_PCIE_IO_START;
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+
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+/*
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+ * This structure and the following arrays allow to map a PCIe (port,
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+ * lane) tuple to the corresponding (target, attribute) tuple needed
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+ * to configure an address decoding window for the given PCIe (port,
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+ * lane).
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+ */
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+struct pcie_mapping {
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+ int port;
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+ int lane;
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+ u8 target;
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+ u8 attr;
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+};
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+
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+struct pcie_mapping armada_xp_pcie_mappings[] = {
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+ { .port = 0, .lane = 0, .target = 4, .attr = 0xE0 },
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+ { .port = 0, .lane = 1, .target = 4, .attr = 0xD0 },
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+ { .port = 0, .lane = 2, .target = 4, .attr = 0xB0 },
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+ { .port = 0, .lane = 3, .target = 4, .attr = 0x70 },
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+ { .port = 1, .lane = 0, .target = 8, .attr = 0xE0 },
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+ { .port = 1, .lane = 1, .target = 8, .attr = 0xD0 },
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+ { .port = 1, .lane = 2, .target = 8, .attr = 0xB0 },
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+ { .port = 1, .lane = 3, .target = 8, .attr = 0x70 },
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+ { .port = 2, .lane = 0, .target = 4, .attr = 0xF0 },
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+ { .port = 3, .lane = 0, .target = 8, .attr = 0xF0 },
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+ { .port = -1 },
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+};
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+
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+struct pcie_mapping armada_370_pcie_mappings[] = {
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+ { .port = 0, .lane = 0, .target = 4, .attr = 0xE0 },
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+ { .port = 1, .lane = 0, .target = 8, .attr = 0xE0 },
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+ { .port = -1 },
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+};
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+
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+/*
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+ * This function finds an available physical address range between
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+ * ARMADA_370_XP_PCIE_MEM_START and ARMADA_370_XP_PCIE_MEM_END (for
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+ * PCIe memory regions) or between ARMADA_370_XP_PCIE_IO_START and
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+ * ARMADA_370_XP_PCIE_IO_END (for PCIe I/O regions) and creates an
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+ * address decoding window from this allocated address pointing to the
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+ * right PCIe device.
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+ *
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+ * An error code is returned, the allocated base address is returned
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+ * through the 'outbase' argument.
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+ */
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+int __init armada_370_xp_alloc_pcie_window(int pcie_port, int pcie_lane,
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+ int type, u32 size,
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+ unsigned long *outbase)
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+{
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+ struct pcie_mapping *mapping, *mappings;
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+ u8 target, attr;
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+ u32 base;
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+ int ret;
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+
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+ if (of_machine_is_compatible("marvell,armadaxp"))
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+ mappings = armada_xp_pcie_mappings;
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+ else if (of_machine_is_compatible("marvell,armada370"))
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+ mappings = armada_370_pcie_mappings;
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+ else
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+ return -ENODEV;
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+
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+ for (mapping = mappings; mapping->port != -1; mapping++)
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+ if (mapping->port == pcie_port && mapping->lane == pcie_lane)
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+ break;
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+
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+ if (mapping->port == -1)
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+ return -ENODEV;
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+
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+ target = mapping->target;
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+ attr = mapping->attr;
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+
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+ if (type == IORESOURCE_MEM) {
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+ /*
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+ * Bit 3 of the attributes indicates that it is a
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+ * memory region, as opposed to an I/O region
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+ */
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+ attr |= (1 << 3);
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+
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+ if (armada_370_xp_pcie_memaddr + size >
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+ ARMADA_370_XP_PCIE_MEM_END)
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+ return -ENOMEM;
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+
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+ base = armada_370_xp_pcie_memaddr;
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+ armada_370_xp_pcie_memaddr += size;
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+
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+ ret = orion_alloc_cpu_win(&addr_map_cfg, base, size, target,
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+ attr, -1);
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+ if (ret) {
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+ armada_370_xp_pcie_memaddr -= size;
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+ return ret;
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+ }
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+ } else if (type == IORESOURCE_IO) {
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+ if (armada_370_xp_pcie_ioaddr + size >
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+ ARMADA_370_XP_PCIE_IO_END)
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+ return -ENOMEM;
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+
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+ base = armada_370_xp_pcie_ioaddr;
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+ armada_370_xp_pcie_ioaddr += size;
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+
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+ ret = orion_alloc_cpu_win(&addr_map_cfg, base, size, target,
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+ attr, -1);
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+ if (ret) {
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+ armada_370_xp_pcie_ioaddr -= size;
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+ return ret;
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+ }
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+ } else
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+ return -ENODEV;
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+
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+ *outbase = base;
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+ return 0;
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+}
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+
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+/*
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+ * Frees an address decoding window previously allocated by
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+ * armada_370_xp_alloc_pcie_window(). Note that only the last window
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+ * allocated for a given type (MEM or IO) can be freed, due to the
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+ * simplicity of the allocator. This is however sufficient to handle
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+ * the error cases when initializing one PCIe device.
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+ */
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+int __init armada_370_xp_free_pcie_window(int type, unsigned long base,
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+ u32 size)
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+{
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+ if (type == IORESOURCE_MEM) {
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+ /* We can only free the last allocated window */
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+ if (base + size != armada_370_xp_pcie_memaddr)
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+ return -EINVAL;
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+ orion_free_cpu_win(&addr_map_cfg, base);
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+ armada_370_xp_pcie_memaddr -= size;
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+ } else if (type == IORESOURCE_IO) {
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+ /* We can only free the last allocated window */
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+ if (base + size != armada_370_xp_pcie_ioaddr)
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+ return -EINVAL;
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+ orion_free_cpu_win(&addr_map_cfg, base);
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+ armada_370_xp_pcie_ioaddr -= size;
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+ } else
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+ return -EINVAL;
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+
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+ return 0;
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+}
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+#endif
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+
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static int __init armada_setup_cpu_mbus(void)
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{
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struct device_node *np;
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--- a/arch/arm/mach-mvebu/common.h
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+++ b/arch/arm/mach-mvebu/common.h
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@@ -25,4 +25,8 @@ int armada_370_xp_coherency_init(void);
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int armada_370_xp_pmsu_init(void);
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void armada_xp_secondary_startup(void);
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extern struct smp_operations armada_xp_smp_ops;
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+
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+int armada_370_xp_alloc_pcie_window(int pcie_port, int pcie_lane,
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+ int type, u32 size, unsigned long *outbase);
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+int armada_370_xp_free_pcie_window(int type, unsigned long base, u32 size);
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#endif
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