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293 lines
6.8 KiB
Diff
293 lines
6.8 KiB
Diff
From 4904337fe34fa7fc529d6f4d9ee8b96fe7db310a Mon Sep 17 00:00:00 2001
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From: Corentin Labbe <clabbe.montjoie@gmail.com>
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Date: Tue, 31 Oct 2017 09:19:12 +0100
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Subject: [PATCH] ARM: dts: sunxi: Restore EMAC changes (boards)
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The original dwmac-sun8i DT bindings have some issue on how to handle
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integrated PHY and was reverted in last RC of 4.13.
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But now we have a solution so we need to get back that was reverted.
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This patch restore all boards DT about dwmac-sun8i
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This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes")
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Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
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Acked-by: Florian Fainelli <f.fainelli@gmail.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9 +++++++
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arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 19 +++++++++++++++
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arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 29 +++++++++++++++++++++++
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arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 ++++++
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arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 +++++++
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arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8 +++++++
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arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 5 ++++
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arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8 +++++++
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arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22 +++++++++++++++++
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arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 16 +++++++++++++
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10 files changed, 131 insertions(+)
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--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
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+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
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@@ -56,6 +56,8 @@
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aliases {
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serial0 = &uart0;
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+ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
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+ ethernet0 = &emac;
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ethernet1 = &xr819;
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};
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@@ -102,6 +104,13 @@
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status = "okay";
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};
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+&emac {
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+ phy-handle = <&int_mii_phy>;
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+ phy-mode = "mii";
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+ allwinner,leds-active-low;
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+ status = "okay";
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+};
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+
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins_a>;
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--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
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+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
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@@ -52,6 +52,7 @@
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compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
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aliases {
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+ ethernet0 = &emac;
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serial0 = &uart0;
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serial1 = &uart1;
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};
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@@ -114,6 +115,24 @@
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status = "okay";
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};
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+&emac {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&emac_rgmii_pins>;
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+ phy-supply = <®_gmac_3v3>;
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+ phy-handle = <&ext_rgmii_phy>;
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+ phy-mode = "rgmii";
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+
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+ allwinner,leds-active-low;
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+ status = "okay";
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+};
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+
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+&external_mdio {
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+ ext_rgmii_phy: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <0>;
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+ };
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+};
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+
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&ir {
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pinctrl-names = "default";
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pinctrl-0 = <&ir_pins_a>;
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--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
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+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
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@@ -45,6 +45,16 @@
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/ {
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model = "FriendlyArm NanoPi M1 Plus";
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compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3";
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+
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+ reg_gmac_3v3: gmac-3v3 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "gmac-3v3";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ startup-delay-us = <100000>;
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+ enable-active-high;
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+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
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+ };
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};
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&ehci1 {
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@@ -55,6 +65,25 @@
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status = "okay";
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};
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+&emac {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&emac_rgmii_pins>;
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+ phy-supply = <®_gmac_3v3>;
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+ phy-handle = <&ext_rgmii_phy>;
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+ phy-mode = "rgmii";
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+
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+ allwinner,leds-active-low;
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+
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+ status = "okay";
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+};
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+
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+&external_mdio {
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+ ext_rgmii_phy: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <7>;
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+ };
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+};
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+
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&ohci1 {
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status = "okay";
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};
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--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
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+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
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@@ -46,3 +46,10 @@
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model = "FriendlyARM NanoPi NEO";
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compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
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};
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+
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+&emac {
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+ phy-handle = <&int_mii_phy>;
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+ phy-mode = "mii";
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+ allwinner,leds-active-low;
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+ status = "okay";
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+};
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--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
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+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
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@@ -54,6 +54,7 @@
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aliases {
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serial0 = &uart0;
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/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
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+ ethernet0 = &emac;
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ethernet1 = &rtl8189;
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};
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@@ -117,6 +118,13 @@
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status = "okay";
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};
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+&emac {
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+ phy-handle = <&int_mii_phy>;
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+ phy-mode = "mii";
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+ allwinner,leds-active-low;
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+ status = "okay";
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+};
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+
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&ir {
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pinctrl-names = "default";
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pinctrl-0 = <&ir_pins_a>;
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--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
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+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
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@@ -52,6 +52,7 @@
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compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
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aliases {
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+ ethernet0 = &emac;
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serial0 = &uart0;
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};
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@@ -97,6 +98,13 @@
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status = "okay";
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};
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+&emac {
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+ phy-handle = <&int_mii_phy>;
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+ phy-mode = "mii";
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+ allwinner,leds-active-low;
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+ status = "okay";
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+};
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+
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&mmc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
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--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
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+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
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@@ -53,6 +53,11 @@
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};
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};
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+&emac {
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+ /* LEDs changed to active high on the plus */
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+ /delete-property/ allwinner,leds-active-low;
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+};
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+
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&mmc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins_a>;
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--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
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+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
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@@ -52,6 +52,7 @@
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compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
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aliases {
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+ ethernet0 = &emac;
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serial0 = &uart0;
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};
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@@ -113,6 +114,13 @@
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status = "okay";
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};
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+&emac {
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+ phy-handle = <&int_mii_phy>;
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+ phy-mode = "mii";
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+ allwinner,leds-active-low;
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+ status = "okay";
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+};
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+
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&ir {
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pinctrl-names = "default";
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pinctrl-0 = <&ir_pins_a>;
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--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
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+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
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@@ -47,6 +47,10 @@
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model = "Xunlong Orange Pi Plus / Plus 2";
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compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
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+ aliases {
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+ ethernet0 = &emac;
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+ };
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+
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reg_gmac_3v3: gmac-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "gmac-3v3";
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@@ -74,6 +78,24 @@
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status = "okay";
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};
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+&emac {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&emac_rgmii_pins>;
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+ phy-supply = <®_gmac_3v3>;
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+ phy-handle = <&ext_rgmii_phy>;
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+ phy-mode = "rgmii";
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+
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+ allwinner,leds-active-low;
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+ status = "okay";
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+};
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+
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+&external_mdio {
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+ ext_rgmii_phy: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <0>;
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+ };
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+};
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+
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&mmc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&mmc2_8bit_pins>;
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--- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
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+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
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@@ -61,3 +61,19 @@
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gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
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};
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};
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+
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+&emac {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&emac_rgmii_pins>;
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+ phy-supply = <®_gmac_3v3>;
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+ phy-handle = <&ext_rgmii_phy>;
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+ phy-mode = "rgmii";
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+ status = "okay";
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+};
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+
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+&external_mdio {
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+ ext_rgmii_phy: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <1>;
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+ };
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+};
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