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105 lines
3.2 KiB
Diff
105 lines
3.2 KiB
Diff
From 13bec8d49bdf10aab4e1570ef42417f6bfbb6126 Mon Sep 17 00:00:00 2001
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From: Ajay Kishore <akisho@codeaurora.org>
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Date: Fri, 27 Mar 2020 23:32:08 +0100
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Subject: pinctrl: qcom: use scm_call to route GPIO irq to Apps
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For IPQ806x targets, TZ protects the registers that are used to
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configure the routing of interrupts to a target processor.
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To resolve this, this patch uses scm call to route GPIO interrupts
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to application processor. Also the scm call interface is changed.
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Signed-off-by: Ajay Kishore <akisho@codeaurora.org>
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Link: https://lore.kernel.org/r/20200327223209.20409-1-ansuelsmth@gmail.com
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Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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drivers/pinctrl/qcom/pinctrl-msm.c | 43 ++++++++++++++++++++++++++++++++------
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1 file changed, 37 insertions(+), 6 deletions(-)
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(limited to 'drivers/pinctrl/qcom/pinctrl-msm.c')
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--- a/drivers/pinctrl/qcom/pinctrl-msm.c
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+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
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@@ -22,6 +22,8 @@
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#include <linux/reboot.h>
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#include <linux/pm.h>
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#include <linux/log2.h>
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+#include <linux/qcom_scm.h>
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+#include <linux/io.h>
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#include "../core.h"
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#include "../pinconf.h"
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@@ -57,6 +59,8 @@ struct msm_pinctrl {
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struct irq_chip irq_chip;
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int irq;
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+ bool intr_target_use_scm;
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+
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raw_spinlock_t lock;
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DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
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@@ -64,6 +68,7 @@ struct msm_pinctrl {
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const struct msm_pinctrl_soc_data *soc;
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void __iomem *regs[MAX_NR_TILES];
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+ u32 phys_base[MAX_NR_TILES];
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};
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#define MSM_ACCESSOR(name) \
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@@ -832,11 +837,30 @@ static int msm_gpio_irq_set_type(struct
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else
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clear_bit(d->hwirq, pctrl->dual_edge_irqs);
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- /* Route interrupts to application cpu */
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- val = msm_readl_intr_target(pctrl, g);
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- val &= ~(7 << g->intr_target_bit);
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- val |= g->intr_target_kpss_val << g->intr_target_bit;
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- msm_writel_intr_target(val, pctrl, g);
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+ /* Route interrupts to application cpu.
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+ * With intr_target_use_scm interrupts are routed to
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+ * application cpu using scm calls.
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+ */
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+ if (pctrl->intr_target_use_scm) {
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+ u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
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+ int ret;
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+
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+ qcom_scm_io_readl(addr, &val);
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+
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+ val &= ~(7 << g->intr_target_bit);
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+ val |= g->intr_target_kpss_val << g->intr_target_bit;
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+
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+ ret = qcom_scm_io_writel(addr, val);
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+ if (ret)
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+ dev_err(pctrl->dev,
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+ "Failed routing %lu interrupt to Apps proc",
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+ d->hwirq);
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+ } else {
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+ val = msm_readl_intr_target(pctrl, g);
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+ val &= ~(7 << g->intr_target_bit);
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+ val |= g->intr_target_kpss_val << g->intr_target_bit;
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+ msm_writel_intr_target(val, pctrl, g);
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+ }
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/* Update configuration for gpio.
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* RAW_STATUS_EN is left on for all gpio irqs. Due to the
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@@ -1138,6 +1162,9 @@ int msm_pinctrl_probe(struct platform_de
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pctrl->dev = &pdev->dev;
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pctrl->soc = soc_data;
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pctrl->chip = msm_gpio_template;
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+ pctrl->intr_target_use_scm = of_device_is_compatible(
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+ pctrl->dev->of_node,
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+ "qcom,ipq8064-pinctrl");
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raw_spin_lock_init(&pctrl->lock);
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@@ -1154,6 +1181,8 @@ int msm_pinctrl_probe(struct platform_de
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pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pctrl->regs[0]))
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return PTR_ERR(pctrl->regs[0]);
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+
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+ pctrl->phys_base[0] = res->start;
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}
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msm_pinctrl_setup_pm_reset(pctrl);
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