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113 lines
4.1 KiB
Diff
113 lines
4.1 KiB
Diff
From d27c303e828d7e42f339a459d2abfe30c51698e9 Mon Sep 17 00:00:00 2001
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From: Sham Muthayyan <smuthayy@codeaurora.org>
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Date: Tue, 26 Jul 2016 12:28:31 +0530
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Subject: PCI: qcom: Programming the PCIE iATU for IPQ806x
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Resolved PCIE EP detection errors caused due to missing iATU programming.
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Change-Id: Ie95c0f8cb940abc0192a8a3c4e825ddba54b72fe
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Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
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---
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--- a/drivers/pci/controller/dwc/pcie-qcom.c
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+++ b/drivers/pci/controller/dwc/pcie-qcom.c
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@@ -76,6 +76,30 @@
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#define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14)
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#define PCIE_CAP_LINK1_VAL 0x2FD7F
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+#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10)
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+
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+#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818
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+#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
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+
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+#define PCIE20_PLR_IATU_VIEWPORT 0x900
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+#define PCIE20_PLR_IATU_REGION_OUTBOUND (0x0 << 31)
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+#define PCIE20_PLR_IATU_REGION_INDEX(x) (x << 0)
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+
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+#define PCIE20_PLR_IATU_CTRL1 0x904
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+#define PCIE20_PLR_IATU_TYPE_CFG0 (0x4 << 0)
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+#define PCIE20_PLR_IATU_TYPE_MEM (0x0 << 0)
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+
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+#define PCIE20_PLR_IATU_CTRL2 0x908
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+#define PCIE20_PLR_IATU_ENABLE BIT(31)
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+
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+#define PCIE20_PLR_IATU_LBAR 0x90C
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+#define PCIE20_PLR_IATU_UBAR 0x910
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+#define PCIE20_PLR_IATU_LAR 0x914
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+#define PCIE20_PLR_IATU_LTAR 0x918
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+#define PCIE20_PLR_IATU_UTAR 0x91c
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+
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+#define MSM_PCIE_DEV_CFG_ADDR 0x01000000
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+
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#define PCIE20_PARF_Q2A_FLUSH 0x1AC
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#define PCIE20_MISC_CONTROL_1_REG 0x8BC
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@@ -240,6 +264,57 @@ static void qcom_pcie_2_1_0_ltssm_enable
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writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
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}
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+static void qcom_pcie_prog_viewport_cfg0(struct qcom_pcie *pcie, u32 busdev)
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+{
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+ struct pcie_port *pp = &pcie->pci->pp;
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+
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+ /*
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+ * program and enable address translation region 0 (device config
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+ * address space); region type config;
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+ * axi config address range to device config address range
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+ */
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+ writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
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+ PCIE20_PLR_IATU_REGION_INDEX(0),
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+ pcie->pci->dbi_base + PCIE20_PLR_IATU_VIEWPORT);
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+
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+ writel(PCIE20_PLR_IATU_TYPE_CFG0, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL1);
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+ writel(PCIE20_PLR_IATU_ENABLE, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL2);
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+ writel(pp->cfg0_base, pcie->pci->dbi_base + PCIE20_PLR_IATU_LBAR);
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+ writel((pp->cfg0_base >> 32), pcie->pci->dbi_base + PCIE20_PLR_IATU_UBAR);
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+ writel((pp->cfg0_base + pp->cfg0_size - 1),
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+ pcie->pci->dbi_base + PCIE20_PLR_IATU_LAR);
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+ writel(busdev, pcie->pci->dbi_base + PCIE20_PLR_IATU_LTAR);
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+ writel(0, pcie->pci->dbi_base + PCIE20_PLR_IATU_UTAR);
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+}
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+
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+static void qcom_pcie_prog_viewport_mem2_outbound(struct qcom_pcie *pcie)
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+{
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+ struct pcie_port *pp = &pcie->pci->pp;
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+
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+ /*
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+ * program and enable address translation region 2 (device resource
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+ * address space); region type memory;
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+ * axi device bar address range to device bar address range
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+ */
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+ writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
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+ PCIE20_PLR_IATU_REGION_INDEX(2),
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+ pcie->pci->dbi_base + PCIE20_PLR_IATU_VIEWPORT);
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+
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+ writel(PCIE20_PLR_IATU_TYPE_MEM, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL1);
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+ writel(PCIE20_PLR_IATU_ENABLE, pcie->pci->dbi_base + PCIE20_PLR_IATU_CTRL2);
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+ writel(pp->mem_base, pcie->pci->dbi_base + PCIE20_PLR_IATU_LBAR);
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+ writel((pp->mem_base >> 32), pcie->pci->dbi_base + PCIE20_PLR_IATU_UBAR);
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+ writel(pp->mem_base + pp->mem_size - 1,
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+ pcie->pci->dbi_base + PCIE20_PLR_IATU_LAR);
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+ writel(pp->mem_bus_addr, pcie->pci->dbi_base + PCIE20_PLR_IATU_LTAR);
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+ writel(upper_32_bits(pp->mem_bus_addr),
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+ pcie->pci->dbi_base + PCIE20_PLR_IATU_UTAR);
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+
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+ /* 256B PCIE buffer setting */
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+ writel(0x1, pcie->pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
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+ writel(0x1, pcie->pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
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+}
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+
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static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
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@@ -437,6 +512,9 @@ static int qcom_pcie_init_2_1_0(struct q
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writel(CFG_BRIDGE_SB_INIT,
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pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
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+ qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR);
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+ qcom_pcie_prog_viewport_mem2_outbound(pcie);
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+
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return 0;
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err_deassert_ahb:
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